EP0877487A1 - Kohärenter, Fraktional-N-Frequenzsynthetisierer mit einer Phasenregelschleife - Google Patents

Kohärenter, Fraktional-N-Frequenzsynthetisierer mit einer Phasenregelschleife Download PDF

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Publication number
EP0877487A1
EP0877487A1 EP98401089A EP98401089A EP0877487A1 EP 0877487 A1 EP0877487 A1 EP 0877487A1 EP 98401089 A EP98401089 A EP 98401089A EP 98401089 A EP98401089 A EP 98401089A EP 0877487 A1 EP0877487 A1 EP 0877487A1
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EP
European Patent Office
Prior art keywords
counter
modulo
increment
division
divider
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Granted
Application number
EP98401089A
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English (en)
French (fr)
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EP0877487B1 (de
Inventor
Jean-Luc Thomson-CSF Prop. Intel. de Gouy
Pascal Thomson-CSF Propriete Intel. Gabet
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Thales SA
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Thomson CSF SA
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Definitions

  • the present invention relates to frequency synthesis and more specifically phase loop frequency synthesizers and not fractional.
  • a phase loop frequency synthesizer consists of a phase-controlled voltage controlled oscillator on an oscillator of reference by means of a phase loop comparing a subharmonic the output signal of the voltage-controlled oscillator obtained by whole or fractional division, at the signal of the oscillator of reference.
  • the division is made by means of a counter-divider with rank of whole division updated with each overflow, which means that the start of a wave train is always synchronized with an overflow of the counter-divider which itself occurs during a period of the signal from the reference oscillator.
  • the object of the present invention is to synthesize phase loop frequency and fractional steps capable of generating coherent signals even after a frequency excursion.
  • a frequency synthesizer with loop of phase and fractional steps comprising a reference oscillator, a voltage controlled oscillator, a phase control loop receiving as inputs the signal from the voltage controlled oscillator and that of the reference oscillator, outputting the command in voltage of the voltage controlled oscillator and comprising a phase comparator connected on the one hand, directly to the output of the reference oscillator and secondly, at the output of the oscillator voltage-controlled via a row counter-divider adjustable division integer, said counter-divider with at least two successive whole rows of division N and N + 1 switchable and a circuit control of the instantaneous division rank applied to the counter-divider performing at least a modulo P digital accumulation, at integer increment K, adjustable and less than P, and changing the said rank snapshot of division according to the overflows of said digital accumulation.
  • This synthesizer has a control circuit of the instant division rank applied to the counter-divider which includes at least one modulo P counter, with unit increment, clocked at signal frequency of the reference oscillator and used in memory of phase to allow changes, at synchronous instants of the reference oscillator, the value of the increment K of the accumulation numerical, following changes in the division ratio fractional, while keeping, for a given frequency, the same phase shift from a pilot signal.
  • the synthesizer frequency with phase loop and not fractional not has a circuit of control of the instant division rank of its counter-divider which includes, in addition to the modulo P counter with unit increment, a multiplier modulo P multiplying the modulo P counter count with unit increment by the increment K of the digital accumulation, a comparator comparing the output signal of the modulo P multiplier with the increment K of digital accumulation and generating an overflow signal each time he finds that the output signal from the modulo P multiplier is strictly less than the value of the increment K of the accumulation digital, and a synchronization means synchronizing the signal overflow of the comparator with the output signal of the counter-divider before applying it to the counter-divider as division rank change command.
  • the comparator comparing the signal of output of the modulo P multiplier at the increment K of the accumulation digital generates an overflow signal whenever it finds that the output signal from the modulo P multiplier is higher or equal to modulo P minus the increment K of the numerical accumulation at instead of being strictly less than the value of the increment K of digital accumulation.
  • the synthesizer frequency with phase loop and not fractional not has a circuit of control of the instant division rank of its counter-divider which includes, in addition to the modulo P counter with unit increment, a modulo P accumulator, with K increment, clocked at the frequency of the reference oscillator, an increment memory K which receives an order writing an overflow output from the modulo P counter to unit increment and which is connected at the data read output to a increment input of the modulo P accumulator with K increment, and a synchronization means synchronizing the overflow signal of the accumulator with the output signal of the counter-divider before apply it to the counter-divider as a change command of division rank.
  • the control circuit of the instantaneous rank of division of the counter-divider is split into a multiplicity of circuits each carrying out, implicitly or explicit, one of said digital accumulations and generating individual overflow signals added by a digital summing circuit before being applied to the command to change the rank of the counter-divider.
  • a frequency synthesizer with phase loop and not whole consists of a controlled oscillator in VCO voltage 1 phase-locked on a reference oscillator 2 at by means of a phase control loop.
  • the loop phase control includes a loop filter 3, a phase-frequency comparator 4 and a counter-divider 5.
  • the filter loop 3 is connected between the voltage control input of the voltage-controlled oscillator VCO 1 and the output of a comparator phase-frequency 4.
  • the phase-frequency comparator 4 has two inputs: one directly connected to the output of reference oscillator 2 and the other connected to the output of the voltage-controlled oscillator VCO 1 via the counter-divider 5.
  • the voltage-controlled oscillator VCO 1 delivers the output signal at the frequency F o of the frequency synthesizer.
  • the reference oscillator 2 delivers a reference signal at frequency F ref .
  • the smallest common multiple of periods between the signal the controlled oscillator VCO 1 and that of the reference oscillator 2 is equal to one period of the reference oscillator.
  • Figure 1b illustrates, in a simplified manner not holding account of the constant phase shifts introduced by the phase-frequency comparator 4 and the counter-divider 5, the time relationships between the various signals appearing at the terminals of the circuits of FIG. 1a.
  • Curve 10 represents the output signal at frequency F 0 of the voltage-controlled oscillator VCO 1, curve 11 the output signal of the counter-divider by N 5, N being taken equal to three, and curve 12 the signal at frequency F ref from reference oscillator 2.
  • all wave trains from the synthesizer at a given frequency have the same phase at the origin with respect to the signal of the reference oscillator 2, even if the synthesizer carried out frequency excursions between them. They are therefore naturally consistent.
  • it has the disadvantage of having a minimum frequency variation step equal to F ref , which is often too large.
  • phase loop frequency synthesizer To decrease the minimum step of frequency variation by phase loop frequency synthesizer there is a technique known called fractional synthesis which makes it possible to obtain a step of synthesis equal to a fraction of the frequency of the oscillator of reference. Its interest is to improve the frequency resolution of a phase loop synthesizer without degrading phase noise.
  • the fractional division is obtained by dynamically changing the value of the whole division rank of the counter-divider of the phase loop between two successive values N and N + 1.
  • N + K / P K and P whole and K ⁇ P
  • the counter-divider of the loop of phase will divide by an N ratio during P-K oscillator cycles of reference and by an N + 1 ratio during K cycles of the oscillator of reference.
  • the smallest common multiple of periods between the signal the voltage-controlled oscillator VCO 1 and the oscillator signal from reference is no longer equal to a period of reference oscillator 2 but at P periods or at a sub-multiple of P periods if the ratio K / P is not irreducible.
  • Figure 2b illustrates, still in a simplified manner not not taking into account the constant phase shifts introduced by the different circuits: phase-frequency comparator, counter-divider and digital accumulator, the temporal relationships between the different signals appearing at the terminals of the circuits of FIG. 2a.
  • Curve 20 represents the output signal at frequency F 0 of the voltage-controlled oscillator VCO 1, curve 21 the output signal of the counter-divider by N 5, N being taken equal to three, curve 22 the content of the digital accumulator 6 assuming that P is equal to four and the increment K to one, the curve 23 the overflow control and the curve 24 the signal at the frequency F ref of the reference oscillator 2.
  • the content of the digital accumulator 6 changes with each pulse at the output of the counter-divider 5.
  • the overflow of the digital accumulator 6 then takes place once every four periods of the signal from the reference oscillator 2 and causes a division by four instead of a division by three of the output signal of the oscillator controlled by voltage. Thirteen periods of frequency F o are thus obtained at the output of the voltage controlled oscillator VCO 1 for four periods of frequency F o of the reference oscillator 2, which gives the fractional ratio of 3.25.
  • the smallest common multiple of periods between the frequency signal F o of the voltage-controlled oscillator and the frequency signal F ref of the reference oscillator is thirteen periods of the signal of the oscillator controlled for four periods of the reference oscillator.
  • the change in frequency of the synthesizer when it corresponds to a change in the increment of the digital accumulator, occurs during any overflow of the counter-divider 5, that is to say with an offset phase can take indifferently four distinct values.
  • the two wave trains at frequency F 1 therefore do not necessarily have the same phase shift relative to the signal of the reference oscillator, which destroys the coherence.
  • phase memory with modulo P counter and increment unit operating at the rate of the reference oscillator to identify the moments of overflow of a digital accumulation initiated in starting the synthesizer which leads to a second mode of production.
  • FIG. 3 illustrates the first embodiment.
  • the voltage-controlled oscillator 1 and the filter loop 3 have been omitted but we find the reference oscillator 2 as well that the counter-divider 5 and the phase-frequency comparator 4 of the phase loop.
  • the counter-divider 5 has two successive whole rows division options N and N + 1 as well as a command input for tilting between these two rows.
  • This switch command from division rank of the counter-divider 5 is controlled, as previously, by an overflow output of an accumulator numerical 30 modulo P with integer increment K variable and less than P, operating at the frequency of reference oscillator 2 but this digital accumulator 30 is connected differently.
  • He is no longer clocked by the output signal of the counter-divider 5 which is not at the frequency of reference oscillator 2 only when the phase loop reaches its equilibrium but by the signal from the reference oscillator 2 himself. to reflect this change, its exit from overflow is no longer linked to the row tilt control counter-divider 5 directly but via a circuit synchronization 31. This is clocked by the output signal from the counter-divider 5 so as to sample the state of the output of overflow of the digital accumulator 30 at the rate of counter-divider overflows 5.
  • the increment input K of the digital accumulator 30 modulo P 30 is connected to the output of a digital memory increment 32 whose registration is controlled by the signal of overflow of a phase memory with incremental modulo p counter unit 33 clocked by the signal from the reference oscillator 2.
  • the digital increment memory 32 consists for example of a multiplexer 320 with two data inputs, one data output and an addressing input, and a type D logic rocker bank 321. One of the data inputs of multiplexer 320 is looped back to its output via the type D 321 logic scale bank clocked by the signal from reference oscillator 2. The other input of data from multiplexer 320 receives the increment setpoint K.
  • the input address of multiplexer 320 is connected to an output of overflow of the modulo P counter with unit increment 33 per via a D 34 type logic flip-flop clocked by the reference oscillator 2.
  • the addressing of the multiplexer 320 is such that in the absence of overflow of the modulo P increment counter unit 33, its data output is looped back on itself by through the D 321 logic flip-flop bank. thus an incremental memory updated only at each overflow of the modulo P counter with increment unit 33 which serves as phase memory and does not allow a change in K increment for the digital accumulator 30 modulo P that every P periods of the reference oscillator 2. This guarantees, as we have seen previously, the phase coherence between all the wave trains generated at the same frequency by the frequency synthesizer, even if the frequency synthesizer has made excursions frequency between generations of these wave trains.
  • the output of the D type logic flip-flop can also be connected to a reset input of the accumulator digital 30 which synchronizes the zero crossings of the digital accumulator 30 on those of the modulo P counter at increment unit 33 of the phase memory.
  • This possibility is recalled in Figure 3 by a dotted line between the outlet of the logic flip-flop type D 34 and a reset input of the modulo P 30 digital accumulator.
  • FIG. 4 shows an extension of the diagram of FIG. 3 to a frequency synthesizer with phase loop and multiple fractional steps.
  • Synthesizers with phase loop and multiple fractional steps differ from synthesizers with phase loop and simple fractional step by the fact that they use in their phase loop a counter-divider with more than two possible successive whole ranks of division: N , N + 1, N + 2, ..., N + s, the division row switching command of which is controlled by the output of a digital adder 40 receiving the overflow commands from separate digital accumulators 41, 42 , ..., 43 modulo of distinct integers P 1 , P 2, ..., P s prime to each other, all operating at the frequency of the reference oscillator 2 with variable integer increments K 0 , K 1 , ..., K s .
  • Each digital accumulator 41, 42, ..., 43 receives its increment K 0 , K 1 , ..., K s from an individual increment memory 45, 46, ..., 47 updated only at each overflow of a 48 modulo counter the product unit increment which operates at the frequency of reference oscillator 2 and serves as a common phase memory.
  • phase memory can be used to maintain coherence by only finding the times of overflow of a digital accumulation systematically initiated at the start of the synthesizer.
  • Figure 5 shows a diagram of frequency synthesizer coherent to phase loop and not fractional based on a calculation implicit overflows of a modulo P to integer increment K made at the rate of the reference oscillator and initiated when the synthesizer starts.
  • the oscillator voltage controlled 1 and loop filter 3 have been omitted but we finds the reference oscillator 2 as well as the counter-divider 5 and the phase-frequency comparator 4 of the phase loop.
  • the counter-divider 5 always has two possible successive whole rows of division N and N + 1 and a switch command input between these two rows connected at the output of a synchronization circuit 31 which is clocked by the output signal of the counter-divider 5 and which samples the state of a tilt control signal between the successive ranks of division N and N + 1 to the rhythm of the overflows of the counter-divider 5.
  • the signal to switch between successive dividing rows N and N + 1 applied at the input of the synchronization circuit 31 comes from an instantaneous division rank control circuit which calculates, implicitly, a modulo P digital accumulation, with a increment K initiated at the start of the synthesizer and which identifies the periods of the reference oscillator 2 during which this digital accumulation overflows.
  • This control circuit consists a 50 modulo P counter with unit increment, clocked by the oscillator reference 2, of a modulo P 51 digital multiplier with two inputs data and a digital comparator 52 with two parallel inputs A and B data, clock input and comparison output A ⁇ B.
  • the multiplier 51 receives on one of its inputs the account of modulo P 50 counter and on the other the numerical value of the increment K of the accumulation. It is connected at the output to the input of data A of digital comparator 52. Digital comparator 52 receives on its other data input B the numerical value of the increment K of the accumulation while its clock input is connected to the output of reference oscillator 2 and that its output of comparison A ⁇ B constitutes that of the control circuit.
  • the counter 50 modulo P with unit increment clocked by the reference oscillator 2 constitutes a phase memory. It provides a n mod P account of the periods of the reference oscillator since the synthesizer was started.
  • the modulo P 51 multiplier delivers the modulo P product from this account by the value of the increment K of the accumulation: [( not mod P ). K ) mod P that is to say, as we have just seen, the value of the digital accumulation modulo P and increment K carried out at the rate of the reference oscillator 2 since the start of the synthesizer and this, whatever the history of the changes in value of the increment K.
  • the comparator 52 detects by implementing the relation: [( not mod P ).
  • Figure 6 shows an extension of the diagram of Figure 5 to a frequency synthesizer with phase loop and not fractional multiple.
  • the phase loop counter-divider 5 has s ranks consecutive integers of division N, N + 1, ..., N + s and a command of selection of one of these division ranks connected to the output of a division instantaneous rank control circuit via a synchronization circuit 31 ensuring that a rank is taken into account of division selected in synchronism with the overflows of the counter-divider 5.
  • the instantaneous division rank control circuit comprises a bank of s partial circuits for implicit calculation of digital accumulation and for tracking overflows of the calculated accumulation, and a digital adder 40 which adds as output the s overflow detection signals. delivered by the bench of the partial circuits.
  • the s partial circuits of the bank carry out in parallel, at the rate of the reference oscillator 2, digital accumulations modulo s integers prime to each other P 1 , P 2 , ..., P s , with variable integer increments K 1 , K 2 , .., K s and identify the periods of the reference oscillator 2 during which they overflow.
  • Each of these partial circuits includes, like the instantaneous division rank control circuit of FIG.
  • a counter 60 respectively 61, ..., 62 with unit increment clocked by the signal of the reference oscillator 2
  • a digital multiplier 63 respectively 64, ..., 65 effecting the product of the increment by counting the counter 60, respectively 61, .., or 62
  • a digital comparator 66 respectively 67, ..., 68 detecting the oscillator periods preferably 2 when the product delivered by the multiplier is strictly less than the increment.
  • Each partial circuit of implicit calculation and location differs from the others by the value of the modulo with which it performs the account of periods of the reference oscillator and the product of this account with the value of the increment.
  • the i th has a counter and a multiplier modulo P i , the modulo P 1 , P 2 , .., P i , .., P s being all different and prime between them.

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EP98401089A 1997-05-07 1998-05-05 Kohärenter, Fraktional-N-Frequenzsynthetisierer mit einer Phasenregelschleife Expired - Lifetime EP0877487B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9705625A FR2763196B1 (fr) 1997-05-07 1997-05-07 Synthetiseur de frequence coherent a boucle de phase et pas fractionnaires
FR9705625 1997-05-07

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EP0877487A1 true EP0877487A1 (de) 1998-11-11
EP0877487B1 EP0877487B1 (de) 2000-07-05

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US (1) US6107843A (de)
EP (1) EP0877487B1 (de)
JP (1) JPH10327071A (de)
DE (1) DE69800197T2 (de)
FR (1) FR2763196B1 (de)
IL (1) IL124288A (de)
RU (1) RU2208904C2 (de)

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DE10016853C2 (de) * 1999-04-02 2003-04-30 Advantest Corp Verzögerungstakt-Erzeugungsvorrichtung
EP1391043A1 (de) * 2001-05-31 2004-02-25 Analog Devices, Inc. Fraktional-n-synthesizer und verfahren zur synchronisation der ausgangsphase

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JPH10247851A (ja) * 1997-03-04 1998-09-14 Hitachi Denshi Ltd フラクショナル−ｎ方式の周波数シンセサイザおよびそれを使用した中継装置
FR2785109B1 (fr) 1998-10-23 2001-01-19 Thomson Csf Compensation du retard du convertisseur analogique numerique dans les modulateurs sigma delta
FR2793972B1 (fr) 1999-05-21 2001-08-10 Thomson Csf Synthetiseur numerique a division coherente
FR2807587B1 (fr) * 2000-04-11 2002-06-28 Thomson Csf Synthetiseur fractionnaire comportant une compensation de la gigue de phase
DE60019736D1 (de) * 2000-06-02 2005-06-02 St Microelectronics Srl Schaltung zur Frequenzmultiplikation und diese Schaltung verwendendes Verfahren zur Zeitverschachtelung von Perioden in Sub-Perioden für einen bürstenlosen Motor
US6356127B1 (en) * 2001-01-10 2002-03-12 Adc Telecommunications, Inc. Phase locked loop
US7343387B2 (en) * 2002-02-26 2008-03-11 Teradyne, Inc. Algorithm for configuring clocking system
DE10234993B4 (de) * 2002-07-31 2006-02-23 Advanced Micro Devices, Inc., Sunnyvale Akkumulator gesteuerter digitaler Frequenzteiler in einer phasenverriegelten Schleife
WO2004034586A2 (en) * 2002-10-08 2004-04-22 M/A-Com, Inc. Methods and apparatus for signal modification in a fractional-n phase locked loop system
US7203262B2 (en) 2003-05-13 2007-04-10 M/A-Com, Inc. Methods and apparatus for signal modification in a fractional-N phase locked loop system
US20050036580A1 (en) * 2003-08-12 2005-02-17 Rana Ram Singh Programmable phase-locked loop fractional-N frequency synthesizer
JP3870942B2 (ja) * 2003-10-20 2007-01-24 ソニー株式会社 データ伝送システム及びデータ伝送装置
US7282967B2 (en) * 2003-10-30 2007-10-16 Avago Technologies General Ip ( Singapore) Pte. Ltd. Fixed frequency clock output having a variable high frequency input clock and an unrelated fixed frequency reference signal
JP4064338B2 (ja) * 2003-12-10 2008-03-19 松下電器産業株式会社 デルタシグマ型分数分周ｐｌｌシンセサイザ
US7555024B2 (en) 2003-12-18 2009-06-30 Yeda Research And Development Company Ltd. Resonator cavity configuration and method
FR2880219B1 (fr) * 2004-12-23 2007-02-23 Thales Sa Procede et systeme de radiocommunication numerique, notamment pour les stations sol mobiles
US7844650B2 (en) * 2006-05-26 2010-11-30 Pmc Sierra Inc. Pulse output direct digital synthesis circuit
US7956696B2 (en) * 2008-09-19 2011-06-07 Altera Corporation Techniques for generating fractional clock signals
EP2613442B1 (de) * 2012-01-06 2015-05-13 u-blox AG Verfahren zur Bestimmung eines Offset-Ausdrucks für ein Fractional-N-PLL-Synthesizersignal, Synthesizer zur Durchführung des Verfahrens, Signalverarbeitungsvorrichtung und GNSS-Empfänger
US8901974B2 (en) 2013-01-30 2014-12-02 Texas Instruments Deutschland Gmbh Phase locked loop and method for operating the same
US9479185B2 (en) * 2014-12-12 2016-10-25 Bae Systems Information And Electronic Systems Integration Inc. Modified delta-sigma modulator for phase coherent frequency synthesis applications
FR3032072B1 (fr) 2015-01-23 2018-05-11 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif de synthese de frequence a boucle de retroaction
RU2602991C1 (ru) * 2015-10-14 2016-11-20 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Московский государственный технический университет имени Н.Э. Баумана" (МГТУ им. Н.Э. Баумана) Быстродействующий синтезатор частот
FR3098664B1 (fr) 2019-07-08 2021-07-23 Commissariat Energie Atomique Dispositif de synthèse de fréquence à boucle de rétroaction
EP3855625A1 (de) 2020-01-27 2021-07-28 Stichting IMEC Nederland Volldigitaler phasenregelkreis und verfahren zu dessen betrieb

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US4468632A (en) * 1981-11-30 1984-08-28 Rca Corporation Phase locked loop frequency synthesizer including fractional digital frequency divider
EP0218508A1 (de) * 1985-09-17 1987-04-15 Thomson-Csf Schnell variierbarer Frequenzgenerator
EP0557799A1 (de) * 1992-02-27 1993-09-01 Hughes Aircraft Company Frequenzsynthetisierer mit gebrochenem Teilverhältnis mit Digitalfehlerkorrektion und Verfahren

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10016853C2 (de) * 1999-04-02 2003-04-30 Advantest Corp Verzögerungstakt-Erzeugungsvorrichtung
EP1391043A1 (de) * 2001-05-31 2004-02-25 Analog Devices, Inc. Fraktional-n-synthesizer und verfahren zur synchronisation der ausgangsphase
EP1391043A4 (de) * 2001-05-31 2004-09-29 Analog Devices Inc Fraktional-n-synthesizer und verfahren zur synchronisation der ausgangsphase

Also Published As

Publication number Publication date
FR2763196B1 (fr) 1999-07-30
FR2763196A1 (fr) 1998-11-13
RU2208904C2 (ru) 2003-07-20
IL124288A (en) 2001-01-11
JPH10327071A (ja) 1998-12-08
DE69800197T2 (de) 2001-03-22
US6107843A (en) 2000-08-22
DE69800197D1 (de) 2000-08-10
EP0877487B1 (de) 2000-07-05

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