EP0846324B1 - Circuit memoire integre a invalidation du mode principal - Google Patents
Circuit memoire integre a invalidation du mode principal Download PDFInfo
- Publication number
- EP0846324B1 EP0846324B1 EP96929053A EP96929053A EP0846324B1 EP 0846324 B1 EP0846324 B1 EP 0846324B1 EP 96929053 A EP96929053 A EP 96929053A EP 96929053 A EP96929053 A EP 96929053A EP 0846324 B1 EP0846324 B1 EP 0846324B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory
- mode
- circuit
- disable
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
Landscapes
- Dram (AREA)
Claims (16)
- Une mémoire à circuit intégré présentant une pluralité de modes de fonctionnement, la mémoire à circuit intégré comprenant :une pluralité de cellules mémoires adressables (12) pour le stockage de données;un circuit d'inhibition non volatil (15) pour inhiber sélectivement un premier mode parmi la pluralité de modes de fonctionnement ; etdes circuits de commande (13) couplés au circuit d'inhibition non volatil pour faire fonctionner le circuit mémoire intégré selon un mode parmi la pluralité de modes de fonctionnement en réponse au circuit d'inhibition non volatil.
- La mémoire à circuit intégré selon la revendication 1, dans laquelle la mémoire à circuit intégré est sous boítier.
- La mémoire à circuit intégré selon la revendication 1 ou 2, dans laquelle le circuit d'inhibition non volatil comprend un fusible à rupture sélective.
- La mémoire à circuit intégré selon la revendication 1 ou 2, dans laquelle le circuit d'inhibition non volatil comprend :un circuit de verrouillage fournissant une sortie pour indiquer qu'un premier mode parmi la pluralité de modes de fonctionnement est inhibé ; etun circuit à fusible relié au circuit de verrouillage fournissant une sortie prédéterminée utilisée pour inhiber de façon permanente le premier mode parmi la pluralité de modes de fonctionnement.
- La mémoire à circuit intégré selon la revendication 4, dans laquelle le circuit à fusible comprend un anti-fusible à rupture sélective (52).
- La mémoire à circuit intégré selon la revendication 4, dans laquelle le circuit à fusible comprend :un premier transistor MOS haute tension (56) avec son drain relié à une ligne basse tension ; etun anti-fusible (52) couplé électriquement entre une source de tension variable et une source du transistor (MOS) haute tension.
- La mémoire à circuit intégré selon la revendication 1 ou 2, dans laquelle le mode parmi la pluralité de modes de fonctionnement est un mode de fonctionnement en mode page.
- La mémoire à circuit intégré selon la revendication 1 ou 2, dans laquelle le mode parmi la pluralité de modes de fonctionnement est un mode de fonctionnement de type EDO (extended data output).
- La mémoire à circuit intégré selon la revendication 1 ou 2, dans laquelle l'un parmi la pluralité de modes de fonctionnement est un mode de fonctionnement de type BEDO (burst extended data output).
- La mémoire à circuit intégré selon la revendication 2, dans laquelle la mémoire est fabriquée par le procédé caractérisé par les étapes consistant :à mettre sous boítier la mémoire à circuit intégré ;à tester la mémoire à circuit intégré sous boítier ; età inhiber l'un parmi la pluralité de modes de fonctionnement en utilisant le circuit d'inhibition non volatil sur la base des tests de la mémoire à circuit intégré sous boítier.
- Un procédé de changement de mode de fonctionnement dans un circuit à mémoire intégré, comprenant les étapes consistant, dans l'ordre :à mettre sous boítier un circuit à mémoire intégrée (10) comprenant un circuit de commande (13) pour faire fonctionner le circuit à mémoire intégrée selon un premier mode parmi une pluralité de modes, et un circuit d'inhibition non volatil (15) couplé au circuit de commande pour inhiber de façon sélective le premier mode ;à tester le circuit à mémoire intégrée sous boítier ;à inhiber le premier mode en utilisant le circuit d'inhibition non volatil sur la base des tests du circuit mémoire intégré sous boítier ; età valider un deuxième mode parmi la pluralité de modes.
- Le procédé selon la revendication 11, dans lequel l'étape d'inhibition du premier mode comprend en outre la sous-étape consistant :à provoquer sélectivement la rupture d'un circuit à fusible pour produire une sortie prédéterminée utilisée pour inhiber de façon permanente le premier mode de fonctionnement.
- Le procédé de la revendication 11, dans lequel le circuit à fusible comprend un anti-fusible (52).
- Le procédé de la revendication 11, dans lequel le premier mode est un mode EDO (extended data output) et le deuxième mode est un mode de fonctionnement en mode page.
- Le procédé de la revendication 11, dans lequel le premier mode est un mode EDO (extended data output) et le deuxième mode est un mode BEDO (burst extended data output).
- Le procédé de la revendication 11, dans lequel le premier mode est un mode BEDO (burst extended data output) et le deuxième mode est un mode EDO (extended data output).
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/518,157 US5657293A (en) | 1995-08-23 | 1995-08-23 | Integrated circuit memory with back end mode disable |
US518157 | 1995-08-23 | ||
PCT/US1996/013711 WO1997008701A1 (fr) | 1995-08-23 | 1996-08-23 | Circuit memoire integre a invalidation du mode principal |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0846324A1 EP0846324A1 (fr) | 1998-06-10 |
EP0846324B1 true EP0846324B1 (fr) | 1999-10-27 |
Family
ID=24062806
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96929053A Expired - Lifetime EP0846324B1 (fr) | 1995-08-23 | 1996-08-23 | Circuit memoire integre a invalidation du mode principal |
Country Status (7)
Country | Link |
---|---|
US (2) | US5657293A (fr) |
EP (1) | EP0846324B1 (fr) |
JP (1) | JPH11501440A (fr) |
KR (1) | KR100301920B1 (fr) |
AU (1) | AU6859796A (fr) |
DE (1) | DE69604925T2 (fr) |
WO (1) | WO1997008701A1 (fr) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5657293A (en) * | 1995-08-23 | 1997-08-12 | Micron Technology, Inc. | Integrated circuit memory with back end mode disable |
US5768619A (en) * | 1996-02-16 | 1998-06-16 | Advanced Micro Devices, Inc. | Method and system for enabling and disabling functions in a peripheral device for a processor system |
US5831923A (en) * | 1996-08-01 | 1998-11-03 | Micron Technology, Inc. | Antifuse detect circuit |
US6023431A (en) * | 1996-10-03 | 2000-02-08 | Micron Technology, Inc. | Low current redundancy anti-fuse method and apparatus |
US5801574A (en) * | 1996-10-07 | 1998-09-01 | Micron Technology, Inc. | Charge sharing detection circuit for anti-fuses |
US5909049A (en) | 1997-02-11 | 1999-06-01 | Actel Corporation | Antifuse programmed PROM cell |
KR100487914B1 (ko) * | 1997-12-29 | 2005-08-24 | 주식회사 하이닉스반도체 | 안티퓨우즈안정화회로 |
US5978297A (en) * | 1998-04-28 | 1999-11-02 | Micron Technology, Inc. | Method and apparatus for strobing antifuse circuits in a memory device |
KR100564421B1 (ko) * | 1998-12-31 | 2006-06-23 | 주식회사 하이닉스반도체 | 메모리 소자의 데이터폭 설정회로 |
US6240033B1 (en) | 1999-01-11 | 2001-05-29 | Hyundai Electronics Industries Co., Ltd. | Antifuse circuitry for post-package DRAM repair |
US6474837B1 (en) * | 2000-11-20 | 2002-11-05 | Richard S. Belliveau | Lighting device with beam altering mechanism incorporating a plurality of light souces |
DE10146336A1 (de) * | 2001-09-20 | 2003-04-10 | Infineon Technologies Ag | Modifikation der Funktonalität eines Chips unter Einsatz eines Multichipgehäuses |
KR100452326B1 (ko) * | 2002-07-04 | 2004-10-12 | 삼성전자주식회사 | 반도체 메모리장치의 동작전압 모드 선택 방법 |
US20060109117A1 (en) * | 2004-11-22 | 2006-05-25 | International Business Machines Corporation | Apparatus and Method of Intelligent Multistage System Deactivation |
JP2009110582A (ja) * | 2007-10-29 | 2009-05-21 | Elpida Memory Inc | アンチヒューズ回路及びこれを備える半導体装置、並びに、アンチヒューズ回路へのアドレス書き込み方法 |
KR102216127B1 (ko) | 2014-08-14 | 2021-02-16 | 삼성전자주식회사 | 문자 입력 방법 및 장치 |
KR20160022097A (ko) | 2014-08-19 | 2016-02-29 | 삼성전자주식회사 | 재구성 차단 기능을 가지는 반도체 메모리 장치 및 메모리 모듈 |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4609985A (en) * | 1982-12-30 | 1986-09-02 | Thomson Components-Mostek Corporation | Microcomputer with severable ROM |
US4876671A (en) * | 1985-04-30 | 1989-10-24 | Texas Instruments Incorporated | Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode |
JPS634492A (ja) * | 1986-06-23 | 1988-01-09 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR910003593B1 (ko) * | 1987-12-30 | 1991-06-07 | 삼성전자 주식회사 | 고집적도 메모리용 모드 선택회로 |
JPH01205788A (ja) * | 1988-02-12 | 1989-08-18 | Toshiba Corp | 半導体集積回路 |
KR900008554B1 (ko) * | 1988-04-23 | 1990-11-24 | 삼성전자 주식회사 | 메모리 동작모드 선택회로 |
US4891794A (en) * | 1988-06-20 | 1990-01-02 | Micron Technology, Inc. | Three port random access memory |
US5159676A (en) * | 1988-12-05 | 1992-10-27 | Micron Technology, Inc. | Semi-smart DRAM controller IC to provide a pseudo-cache mode of operation using standard page mode draws |
JP2744115B2 (ja) * | 1990-05-21 | 1998-04-28 | 株式会社東芝 | 疑似スタティックramの制御回路 |
DE69120483T2 (de) * | 1990-08-17 | 1996-11-14 | Sgs Thomson Microelectronics | Halbleiter-Speicher mit unterdrücktem Testmodus-Eingang während des Strom-Einschaltens |
US5245577A (en) * | 1990-11-06 | 1993-09-14 | Micron Technology, Inc. | Integrated circuit two-cycle test mode activation circuit |
JP2715009B2 (ja) * | 1991-05-16 | 1998-02-16 | 三菱電機株式会社 | ダイナミックランダムアクセスメモリ装置 |
US5241496A (en) * | 1991-08-19 | 1993-08-31 | Micron Technology, Inc. | Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells |
US5110754A (en) * | 1991-10-04 | 1992-05-05 | Micron Technology, Inc. | Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM |
US5233206A (en) * | 1991-11-13 | 1993-08-03 | Micron Technology, Inc. | Double digitlines for multiple programming of prom applications and other anti-fuse circuit element applications |
US5200652A (en) * | 1991-11-13 | 1993-04-06 | Micron Technology, Inc. | Programmable/reprogrammable structure combining both antifuse and fuse elements |
TW212243B (fr) * | 1991-11-15 | 1993-09-01 | Hitachi Seisakusyo Kk | |
US5257222A (en) * | 1992-01-14 | 1993-10-26 | Micron Technology, Inc. | Antifuse programming by transistor snap-back |
US5208177A (en) * | 1992-02-07 | 1993-05-04 | Micron Technology, Inc. | Local field enhancement for better programmability of antifuse PROM |
US5148391A (en) * | 1992-02-14 | 1992-09-15 | Micron Technology, Inc. | Nonvolatile, zero-power memory cell constructed with capacitor-like antifuses operable at less than power supply voltage |
US5257225A (en) * | 1992-03-12 | 1993-10-26 | Micron Technology, Inc. | Method for programming programmable devices by utilizing single or multiple pulses varying in pulse width and amplitude |
US5375222A (en) * | 1992-03-31 | 1994-12-20 | Intel Corporation | Flash memory card with a ready/busy mask register |
US5250459A (en) * | 1992-04-14 | 1993-10-05 | Micron Technology, Inc. | Electrically programmable low resistive antifuse element |
JPH0612878A (ja) * | 1992-06-25 | 1994-01-21 | Mitsubishi Electric Corp | 半導体メモリ装置 |
US5282158A (en) * | 1992-08-21 | 1994-01-25 | Micron Technology, Inc. | Transistor antifuse for a programmable ROM |
US5301159A (en) * | 1993-02-05 | 1994-04-05 | Micron Technology, Inc. | Anti-fuse circuit and method wherein the read operation and programming operation are reversed |
US5331593A (en) * | 1993-03-03 | 1994-07-19 | Micron Semiconductor, Inc. | Read circuit for accessing dynamic random access memories (DRAMS) |
US5315177A (en) * | 1993-03-12 | 1994-05-24 | Micron Semiconductor, Inc. | One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture |
US5349566A (en) * | 1993-05-19 | 1994-09-20 | Micron Semiconductor, Inc. | Memory device with pulse circuit for timing data output, and method for outputting data |
US5335202A (en) * | 1993-06-29 | 1994-08-02 | Micron Semiconductor, Inc. | Verifying dynamic memory refresh |
US5379250A (en) * | 1993-08-20 | 1995-01-03 | Micron Semiconductor, Inc. | Zener programmable read only memory |
KR0119886B1 (ko) * | 1994-07-27 | 1997-10-17 | 김광호 | 반도체 메모리 장치의 모드설정회로 및 그 방법 |
US5657293A (en) * | 1995-08-23 | 1997-08-12 | Micron Technology, Inc. | Integrated circuit memory with back end mode disable |
-
1995
- 1995-08-23 US US08/518,157 patent/US5657293A/en not_active Expired - Lifetime
-
1996
- 1996-08-23 AU AU68597/96A patent/AU6859796A/en not_active Abandoned
- 1996-08-23 KR KR1019980701315A patent/KR100301920B1/ko not_active IP Right Cessation
- 1996-08-23 DE DE69604925T patent/DE69604925T2/de not_active Expired - Lifetime
- 1996-08-23 WO PCT/US1996/013711 patent/WO1997008701A1/fr active IP Right Grant
- 1996-08-23 JP JP9510500A patent/JPH11501440A/ja active Pending
- 1996-08-23 EP EP96929053A patent/EP0846324B1/fr not_active Expired - Lifetime
-
1997
- 1997-03-27 US US08/826,276 patent/US5793692A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR19990044082A (ko) | 1999-06-25 |
WO1997008701A1 (fr) | 1997-03-06 |
AU6859796A (en) | 1997-03-19 |
KR100301920B1 (ko) | 2001-10-29 |
US5793692A (en) | 1998-08-11 |
DE69604925D1 (de) | 1999-12-02 |
EP0846324A1 (fr) | 1998-06-10 |
US5657293A (en) | 1997-08-12 |
JPH11501440A (ja) | 1999-02-02 |
DE69604925T2 (de) | 2000-02-03 |
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