Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
  • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
  • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
  • H04N5/44504—Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/14—Display of multiple viewports
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2340/00—Aspects of display data processing
  • G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
  • G09G2340/125—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels wherein one of the images is motion video

Definitions

• the present invention relates to an onscreen display architecture, for use in television receivers, which stores display representative data in a linked list.
• OSDs onscreen displays
• an OSD displays the current channel when a user changes the channel; or displays a bar graphically illustrating the current volume of the television set when the user adjusts the volume.
• an OSD is used to assist the user in entering schedule information for unattended recording. It has been proposed to provide animated OSDs to further enhance the user interface.
• OSD display systems use a known bitmapped architecture in which the OSD image is considered to be an array of picture elements (pixels) arranged as N rows, each row containing M pixels arranged in columns. Each pixel in the OSD array can assume one of a predetermined number of colors. Data representing the image in the OSD pixel array is stored in a memory, termed an OSD memory in the remainder of this application, which is arranged in a corresponding array of N rows, each row containing M pixelrepresentative words. In a blackandwhite display, the pixelrepresentative words are 1 bit wide representing either black or white. In monochrome displays, each pixel representative word contains a plurality of bits representing the gray scale level of that pixel.
• Color pixels are represented by three sets of color level bits, one set for each of the primary colors: red, green, and blue.
• each pixel representative word can represent one of a predetermined number of colors selected from a palette.
• Most current OSDs use the palette technique.
• the image data defining the contents of the OSDs to be displayed for the next field, and the new palette and other control data are stored (in the format described above) in the OSD memory during the vertical blanking interval (VBI).
• VBI vertical blanking interval
• line and pixel counters maintain the location in the raster currently being scanned, and if an OSD is specified for that area, the OSD image data from the OSD memory is overlaid on the received video signal.
• the OSD data could replace the received video signal, or could be combined with the video signal in some manner, as is well known.
• the OSD memory must produce data with a relatively high bandwidth. This requirement has been met by the use of a specially designed video read/write memory (VRAM) which can serially shift a wide data output word in a single memory access time. This, in turn, requires that the data for the OSDs be located contiguously in the memory to minimize addressing and access time.
• VRAM video read/write memory
• FIGURE 1 is a block diagram of a portion of a television signal receiver including an onscreen display system according to the present invention.
• FIGURE 1 is a block diagram of a portion of a television signal receiver including an onscreen display system according to the present invention.
• FIGURE 1 illustrates only those elements of such a television receiver which are necessary to understand the invention.
• One skilled in the art will understand what other elements are required, and how to design, implement and interconnect such elements with the illustrated elements.
• an image signal source 10 produces an image representative signal.
• An image signal output terminal of the image signal source 10 is coupled to a first input terminal of a signal combiner 20.
• An output terminal of the signal combiner 20 is coupled to an input terminal of a display device 30.
• An onscreen display (OSD) generator 40 has a bidirectional terminal coupled to an OSD memory 50, and an output terminal coupled to a second input terminal of the signal combiner 20.
• a status output terminal of the image signal source 10 is coupled to a corresponding input terminal of the OSD generator 40.
• a control processor 60 includes a first bidirectional control terminal coupled to the image signal source 10, and a second bidirectional control terminal coupled to the OSD generator 40.
• the image signal source 10 may be a television receiver front end of known design for reception of an offair, cable or satellite transmitted signal, or may be the playback mechanism of a video cassette recorder or videodisc, also of known design.
• the control processor 60 controls the image signal source 10, for example, to tune a channel or select a prerecorded program on a videodisc or video cassette recorder.
• the image signal source 10 produces a signal representing the image the viewer desires to watch.
• the image representative signal may be a standard (e.g. NTSC) video signal, or any other image representative signal, such as the RGB drive signals for a kinescope in the television display device 30. This signal is passed to the display device 30 through the signal combiner 20.
• the image signal source 10 provides to the OSD generator 40, via signals at its status output terminal, the line and pixel currently being scanned.
• the OSD generator 40 monitors the line and pixel currently being scanned. When the scan reaches the location to be filled by the OSD represented by the first block, the OSD generator 40 retrieves the data from the block 52 representing that OSD, and generates an image representative signal representing that OSD from the bitmapped/palette data, in a known manner. This OSD image representative data from the OSD generator 40 is then supplied to the signal combiner 20 to be combined with the received or reproduced image from the image signal source 10.
• the signal combiner 20 operates in a known manner to combine the OSD image representative signal with the received or reproduced image representative signal to produce an image on the display device 30 including the received or reproduced image as the background image, with the OSDs 32 positioned within that background image.
• the signal combiner 20 may replace the background image with the OSD image, i.e. the signal combiner operates as a simple switch.
• the signal combiner 20 may mix the OSD image and the background image in a predetermined proportion.
• one color of the palette of colors defining the OSD image may represent 'transparent', and when that color is produced by the OSD generator 40, the background image is allowed to show through the OSD image, otherwise the OSD image overlays the background image.
• the OSD representative information in the block 52 in the OSD memory 50 may control the operation of the signal combiner 20.
• the OSD generator 40 may condition the signal combiner 20 to vary the proportion of the background image representative signal to the OSD image representative signal in response to data stored in the block 52 in the OSD memory 50 defining that OSD.
• the proportion may be varied from 0% (i.e. the OSD image opaquely overlays the background image), to 20% (i.e. the background image is barely visible through the OSD image, to 80% (i.e. the OSD image is barely visible through the background image), to 100% (i.e. the OSD image is invisible).
• the OSD generator 40 may also condition the signal combiner 20 to selectively enable or disable the 'transparent' color operation in response to data stored in the block 52 in the OSD memory 50 for that OSD. Further, it is possible to include data with each entry in the palette in each block 52 which defines whether the color defined by this palette entry is to be mixed with, or to overlay, the background image signal.
• FIGURE 2 is a memory layout diagram of information in the OSD memory 50 of the onscreen display system illustrated in FIGURE 1.
• the OSD memory 50 is illustrated as a rectangle and the layout of the blocks 52 of OSD data within the OSD memory 50 is illustrated by other rectangles within the OSD memory 50.
• the corresponding display 30, displaying a background image and three OSD images 32, is also illustrated in FIGURE 2.
• a pointer to the location of the first OSD block in the OSD memory 50 is contained in a data store 42.
• Data store 42 may also be a location within the OSD memory 50, or a hardware register separate from the OSD memory 50.
• Block 1 corresponds to OSD 1
• block 2, 52(2) corresponds to OSD 2
• block 3A, 52(3A) corresponds to OSD 3
• block 4, 52(4) corresponds to an OSD not illustrated on the display 30 for the sake of simplicity in the figure.
• Each block 52 includes a header, followed by the bitmapped/palette data describing the OSD image represented by this block.
• FIGURE 2 only blocks 1 and 2, 52(1) and 52(2), respectively, are shown in detail, but all blocks 52 have similar structure.
• the header contains data, denoted LOC in FIGURE 2, representing the line and pixel of the location of the OSD image on the display 30.
• control processor 60 (of FIGURE 1) generates and stores the blocks 52 in the OSD memory 50, then, during the VBI, sets the start pointer 42 and all the pointers, PTR, in the blocks 52 to form a sequence of blocks 52, representing a sequence of OSDs 32.
• the OSD generator 40 retrieves the previously stored data in the sequence of blocks 52 from the OSD memory 50 and generates an OSD image representative signal which is combined with the background image signal from the image signal source 10 in the signal combiner 20 to form a signal representing the image on the display 30 with the OSDs 32.
• each block contains the location on the display 30 of the OSD 32 represented by that block. This is indicated in FIGURE 2 by straight arrows from the display location pointer LOC in block 1, 52(1), to the location on the display 30 of OSD 1, from the LOC pointer in block 2 to OSD 2, and from the LOC pointer in block 3A to OSD 3.
• the processor 60 stores the location of block 1 in the start pointer 42, the location of block 2 in the pointer PTR of block 1, the location of block 3 A in the pointer PTR of block 2, and the location of block 4 in the pointer PTR of block 3A (all represented in FIGURE 2 by curved arrows from the location in the OSD memory 50 containing the pointer to the location pointed to by that pointer), and an outofrange value (i.e. a row and/or pixel value which is not within the display area of the display 30) in the pointer of block 4.
• This process is a relatively fast one involving only a few memory accesses, even for a display 30 containing a large number of complex OSDs 32.
• the OSD generator 40 retrieves block 1, 52(1), pointed to by the start pointer 42, and reads the header. From the header, the OSD generator 40 extracts the pointer LOC to the row and pixel location of OSD 1 on the display 30, and the palette for OSD 1 stored in the image data portion of block 1 52( 1). Then the OSD controller 40 begins to monitor the row and pixel currently being scanned, as supplied by the image signal source 10. When the row and pixel of OSD 1 is reached, the OSD generator 40 supplies the OSD 1 image data from block 1 , 52( 1), to the signal combiner 20, where it is combined with the background image representative signal, all in a known manner.
• the pointer PTR from block 1, pointing to block 2, 52(2) is extracted from the header information.
• the image data for OSD 2 is then retrieved from the OSD memory 50, and processed in the same manner described above for block 1 ,
• OSD 3 represented by block 3A, 52(3A), and the OSD (not shown) represented by block 4, 52(4), are then displayed, in that order.
• OSD 4 represented by block 4, 52(4)
• the pointer from the header of block 4, 52(4) is extracted. Because it is an outofrange value, this indicates to the OSD generator 40 that there are no more OSDs to be displayed in this field, and the OSD generator 40 stops processing blocks 52.
• OSD 3 may be an animated OSD, which in the illustrated embodiment has two images which are alternated rapidly to create the animation effect. It is also possible to have more than two images (i.e. 3A, 3B, 3C, 3D, etc.), which are displayed in order, in the animation.
• the control processor 60 can write blocks 52 into the OSD memory 50 defining all of the different images of OSD 3 to be displayed in the animation in advance. During the field described above, the first image (defined by block 3A, 52(3A)) of the OSD 3 animation was displayed.
• the OSD 3 image represented by block 3A, 52(3A) is again displayed in OSD 3 by changing the pointer PTR in block 2, 52(2) to point to the location of block 3A, 52(3A) again during the VBI. If more than two images were part of the animation, each would be displayed in its turn by placing the location of its block 52(3*) into the pointer
• OSD 3 may be an OSD displaying information which changes relatively rapidly.
• a new value is determined by the control processor 60, which generates a new OSD image representing this new value and stores the image representative data in block 3B.
• this newly generated OSD 3 image is linked into the sequence of blocks defining the OSDs, as illustrated in phantom in FIGURE 2, by placing its location in the OSD memory 50 into the pointer PTR of block 2, 52(2).
• the block 52(3A) containing the image displaying the previous value of the information may then be released and used for other purposes.
• the control processor 60 may generate a complete series of image representative blocks 52 in advance, such as for animation, or a new image representative block representing a new value of information at any time in the scan.
• the next image in the animation, or the newly generated OSD image is simply linked into the sequence of OSDs by changing only the pointers in the OSD image blocks 52.
• the time spent in updating the start pointer 42 and the pointers PTRs in the blocks 52 is minimal, and a relatively large number of OSDs of arbitrary size, and which change relatively rapidly, may be maintained in an OSD display system according to the present invention.
• the illustrated embodiment included a single start pointer 42.
• OSD blocks 52 may be used for odd and even fields for the same OSD 32.
• two start pointer data stores (corresponding to data store 42) may be maintained, one for odd fields, and one for even fields, and each pointing to the start of respectively different sequences of OSD image data blocks 52 stored in the OSD memory 50 by the control processor 60.
• odd fields the sequence pointed to by the odd field start pointer is processed, and during even fields, the sequence pointed to by the even field start pointer is processed.
• two different sequences (an odd field sequence, and an even field sequence) of data blocks 52 may be maintained in the OSD memory 50 by the control processor 60, as above, and the contents of the single start pointer data store 42 changed by the control processor 60 so that the image representative signals represented by the odd field sequence are produced during odd fields, and those represented by the even field sequence of OSD blocks 52 are produced during even fields.

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Computer Graphics (AREA)
• Controls And Circuits For Display Device (AREA)
• Television Signal Processing For Recording (AREA)

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Publications (1)

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• 1996
  • 1996-07-24 CN CN96197121A patent/CN1197570A/zh active Pending
  • 1996-07-24 WO PCT/US1996/012164 patent/WO1997005743A1/en not_active Application Discontinuation
  • 1996-07-24 KR KR1019980700753A patent/KR19990036087A/ko not_active Application Discontinuation
  • 1996-07-24 JP JP9507705A patent/JPH11510269A/ja active Pending
  • 1996-07-24 BR BR9610169A patent/BR9610169A/pt not_active Application Discontinuation
  • 1996-07-24 EP EP96925453A patent/EP0842582A1/en not_active Withdrawn
  • 1996-07-24 AU AU65961/96A patent/AU6596196A/en not_active Abandoned

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