EP0838746A1 - Spannungsregler mit interner Erzeugung eines logischen Signals - Google Patents

Spannungsregler mit interner Erzeugung eines logischen Signals Download PDF

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Publication number
EP0838746A1
EP0838746A1 EP97410121A EP97410121A EP0838746A1 EP 0838746 A1 EP0838746 A1 EP 0838746A1 EP 97410121 A EP97410121 A EP 97410121A EP 97410121 A EP97410121 A EP 97410121A EP 0838746 A1 EP0838746 A1 EP 0838746A1
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EP
European Patent Office
Prior art keywords
voltage
transistors
transistor
circuit
regulator
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EP97410121A
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English (en)
French (fr)
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EP0838746B1 (de
Inventor
Marc Gens
François Van Zanten
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STMicroelectronics SA
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STMicroelectronics SA
SGS Thomson Microelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/59—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load

Definitions

  • the present invention relates to a voltage regulator for supplying a regulated supply voltage to a load from an input voltage.
  • An example of application of the present invention concerns integrated circuits for telephone sets remotely powered where power is supplied by the telephone line, either by the ringing circuit when the set is not not off-hook, either by the speech circuit when the station is off the hook, or even by a power supply specific to the telephone set (for example, a stack).
  • Figure 1 shows a classic diagram of a regulator intended to supply a regulated voltage at a value specified from a single supply voltage.
  • Such a regulator receives, on an input terminal E, a supply voltage to be regulated V, and delivers, on an output terminal S, a regulated voltage V R.
  • the regulator comprises a circuit 1 providing a reference voltage, and a circuit 2 for controlling a P-channel power MOS transistor M10, the source of which is connected to terminal E and the drain of which constitutes terminal S.
  • Circuit 1 has the role of setting a precise reference voltage V BG to control, via the control circuit 2, the output voltage V R.
  • Circuit 1 comprises two bipolar PNP type transistors Q1 and Q2, the respective transmitters of which are connected to terminal E and the respective collectors of which constitute two output terminals 3, 4 of circuit 1 intended to control circuit 2 as will be seen by the following.
  • the bases of the transistors Q1 and Q2 are connected to the collector of the transistor Q1.
  • the collectors of the transistors Q1 and Q2 are respectively connected to the collectors of bipolar transistors of the NPN type Q3 and Q4, the bases of which are connected and constitute a terminal 5 at the reference potential V BG .
  • the emitter of transistor Q4 is connected to ground via two resistors R1 and R2 connected in series.
  • the emitter of transistor Q3 is connected to the midpoint of the series association of resistors R1 and R2.
  • the resistors R1 and R2 and the surface ratio of the transistors Q3 and Q4 are chosen to obtain the desired voltage V BG with a given current in the transistors Q1, Q2, Q3 and Q4.
  • Circuit 1 comprises a starting circuit consisting of a current source I, the output of which is connected, to ground via a diode D and, at the base of a bipolar transistor of NPN QD type, the collector is connected to terminal 4 and whose transmitter is connected to the midpoint of the series association of resistors R1 and R2.
  • Circuit 1 shown in Figure 1 is generally designated by its Anglo-Saxon name “band gap” and its operation is well known.
  • the circuit 2 for controlling the transistor M10 consists of two bipolar PNP transistors of the Q5 and Q6 type, the respective emitters of which are connected to the terminal E and the bases of which are respectively connected to the terminals 4 and 3.
  • the collectors of the transistors Q5 and Q6 are connected to the respective drains of two N-channel MOS transistors M11 and M3 mounted in current mirror, the sources of the transistors M11 and M3 being connected to ground and the transistor M11 being mounted as a diode.
  • the collector of transistor Q6 constitutes an output terminal of circuit 2 connected to the gate of transistor M10.
  • a resistive bridge consisting of resistors R3 and R4 is generally connected between terminal S and ground when the desired voltage V R is different from the reference voltage V BG .
  • This divider bridge is connected to terminal 5 of circuit 1 to form a feedback loop making it possible to maintain the reference voltage V BG on the bases of the transistors Q3 and Q4.
  • This reference voltage ensures the equality of the currents in the transistors Q3 and Q4.
  • This current imbalance is amplified by circuit 2 and modifies the potential V G for controlling the transistor M10 to restore, via the resistive bridge R3-R4, the voltage V BG which ensures the equality of the currents in the transistors Q3 and Q4.
  • the voltage V R is equal to V BG . (R3 + R4) / R4.
  • a capacitor C is generally provided at the outlet of the regulator and is connected between terminal S and earth. The role of this capacitor is, in particular, to ensure the stability of the feedback loop.
  • a drawback of a regulator as shown in FIG. 1 is that, if the voltage V becomes lower than the regulated voltage V R , the terminals E and S are short-circuited by the transistor M10.
  • the substrate of the MOS transistor M10 or its well is generally connected to its source, that is to say to the potential V.
  • the substrate of a MOS transistor or its well is generally designated by the "body” of the transistor ("bulk” in its Anglo-Saxon name) to distinguish it from the overall substrate of the integrated circuit on which the various components are made.
  • the body of a MOS transistor is generally symbolized by an arrow whose direction indicates the P or N type of the transistor channel.
  • the PN junction between the drain and the body of the transistor M10 is directly biased and the transistor is then short-circuited by the drain / body diode.
  • the drain and the source of the transistor M10 are exchanged (the current being reversed), which transforms the feedback from the circuit 1 into reaction.
  • This short circuit harms a second role of the capacitor C which is to temporarily supply the load in the event of insufficient or disappearance of the supply voltage V.
  • the regulator when used to supply a microprocessor, one seeks to be able to maintain the supply of the microprocessor while it can save the data, following an insufficiency or the disappearance of the supply voltage.
  • the voltage V R is generally compared with respect to a threshold by means of a circuit external to the regulator to detect a decrease in the voltage V R and then use the capacitor C to temporarily supply the microprocessor before the voltage V R disappears.
  • a drawback of such a solution is that it introduces a voltage drop of about 0.7 volts between the input and output terminals of the regulator.
  • Isolation diodes are also used when we want to be able to power the regulator as shown in FIG. 1 from different voltages by selecting, as the voltage to be regulated, the one with the greatest potential Student.
  • FIG. 2 represents a classic example of a voltage regulator automatically selecting, from two supply voltages V M and V L arriving at two input terminals EM and E L , the highest voltage.
  • the circuits 1 and 2 represented in FIG. 1 have been shown diagrammatically in FIG. 2 by a reference voltage source 1 and by an amplifier 2 receiving, as input, the reference voltage V BG and the potential of the midpoint of the resistive divider bridge R3-R4.
  • Amplifier 2 and generator 1 are polarized by the highest supply voltage V M or V L by means of diodes, respectively D1, D2 and D3, D4 interposed in series between each terminal E M or E L and the generator 1 or amplifier 2 bias terminal.
  • the present invention aims to propose a new regulator voltage to automatically generate a signal logic indicating, while the supply voltage is not sufficient to supply the desired regulated voltage, that the voltage output is less than a determined threshold.
  • the present invention also aims to optimize the use of a decoupling capacitor placed at the outlet of the regulator to temporarily supply the load when the unregulated supply voltage is less than the supply voltage regulated output.
  • the present invention provides a voltage regulator comprising at least one terminal input suitable for receiving a supply voltage, a circuit of generating a reference voltage proportional to a desired regulated output voltage, signal amplifier error between said reference voltage and the output affected by a proportionality coefficient, a capacitor connected between an output terminal and ground, and means for supplying at least said circuit and said amplifier with the output voltage in case of insufficient or disappearance of the supply voltage present on the terminal entry.
  • the regulator also includes a comparator capable of delivering, when the regulator is supplied by the output voltage, a logic signal that the output voltage becomes lower at a threshold value proportional to said voltage of reference.
  • the regulator includes a conduction means for connecting the output voltage at reference voltage in case of insufficiency or disappearance of the supply voltage present on the input terminal.
  • connection between the output voltage and the reference voltage is resistive.
  • the regulator comprises at least a first power transistor having a first power electrode connected directly to the input terminal and a second electrode connected to the output terminal, the conduction means consisting of a second low power transistor in series with a first resistance mounted in parallel on at least one second resistance contributing to fix the proportionality coefficient.
  • the regulator has a specific circuit to make the transistor associated with the highest voltage among the voltage power supply and output voltage.
  • At least the first power transistor is a MOS transistor P-channel whose body is polarized by means of the voltage la higher between the input voltage and the output voltage.
  • FIG. 3 represents a first embodiment of a voltage regulator according to the invention.
  • This regulator comprises an input terminal E L , suitable for receiving a supply voltage V L , and an output terminal S, associated with a decoupling capacitor C and delivering a regulated voltage V R.
  • the regulator comprises a P-channel power MOS transistor M10L having a first power electrode connected to the terminal E L and a second power electrode connected to the terminal S.
  • a circuit 1 ′ provides a voltage of reference V BG and is associated with a 2 'amplifier.
  • a resistive divider bridge, made up of resistors R3A, R3B and R4, is connected in series between terminal S and ground. The midpoint of the association of the resistors R3A and R3B with the resistor R4 is connected to a first input of the amplifier 2 ', a second input of which receives the voltage V BG .
  • the regulator further includes a comparator 12 associated with a low-power P-channel transistor M10R to generate a RESET logic signal.
  • This RESET signal is intended to indicate a regulator supply fault by means of the voltage V L , that is to say that the highest voltage of the regulator is the voltage V R , and that the output voltage V R is less than a determined threshold.
  • This RESET signal is, for example, used to signal to the load (not shown), for example a microprocessor, that the voltage which it receives is now only supplied by the capacitor C and is therefore only temporary.
  • the transistor M10R is connected, by its source, to the terminal S and, by its drain, to a first input terminal of the comparator 12 as well as, via a resistor R5, at the midpoint of the series association of resistors R3A and R3B with resistance R4.
  • the gate of the transistor M10R is connected to a selection circuit 10 associated with the amplifier 2 'to select the transistor to be made conductive from among the transistors M10L and M10R as a function of that of the voltages V L and V R which is the highest.
  • the tipping point of comparator 12 is fixed by the values of resistors R3A, R3B, R4 and R5. Its value corresponds to: V BQ . [(R5 / R4). (R3A + R3B) / (R5 + R3B) + 1].
  • An advantage of the present invention is that the transistor M10R makes it possible to maintain the feedback loop even when the voltage V R is the highest voltage, thus allowing the regulator to integrate the generation of a RESET signal when the voltage V R corresponds to the discharge of capacitor C and becomes less than a threshold voltage. This makes it possible to determine this threshold voltage very precisely insofar as it is linked to the voltage V BG fixed by the circuit 1 '. In addition, this minimizes the consumption linked to the generation of the RESET signal insofar as the components of the regulator are used which are generally chosen for their low consumption.
  • a characteristic of the present invention is that the circuits 1 ′, 2 ′ and 10 are supplied by the highest voltage among the voltages V L and V R by means of a comparator 11, two inputs of which are respectively connected to the terminals E L and S.
  • the body (substrate or well) of the MOS transistor M10L is connected to the highest potential among the voltages V L and V R. This connection has been symbolized in FIG. 3 by a connection between the body of the transistor M10L and the output of the comparator 11. Thus, even if the voltage V R is greater than the voltage V L , the transistor M10L is not short- circulated insofar as its body is also at the voltage V R , which prohibits any direct polarization of the drain / body and source / body junctions.
  • FIG. 4 represents a second embodiment of the present invention, in which the regulator further comprises a second P-channel power MOS transistor M10M having a first power electrode connected to a second supply terminal E M and a second power electrode connected to terminal S.
  • the terminals E M and E L are intended to receive supply voltages independent of each other and the circuit 11 has three inputs receiving the voltages V M , V L and V R.
  • the circuit 10 selects the transistor to be made conductive from among the transistors M10M, M10L and M10R and the body of the transistor M10M is connected to the output of the comparator 11.
  • the transistor M10L or M10M associated with the lower supply voltage V L or V M is blocked by the circuit 10 and, even if this lower voltage V L or V M is lower than the voltage V R , this transistor is not short-circuited insofar as its body is brought to the highest potential.
  • An advantage of this embodiment is that the lowest supply voltage V M or V L is isolated from the regulator.
  • Another advantage of the present invention is that the voltage drop between regulator input and output terminals is weak. Indeed, it is limited to about 0.1 volts corresponding to the voltage drop in the MOS transistors of power in the on state.
  • means for selecting the voltage higher are provided separately for the circuit 1 ', circuits 2' and 10 and for the polarization of the bodies of M10M and M10L transistors.
  • a bias circuit is provided bodies intended for M10M and M10L transistors as well than other regulator P-channel MOS transistors.
  • FIG. 5 represents an embodiment of the circuit 1 'for generating the reference voltage V BG , as well as the control circuit 2' and the selection circuit 10 associated therewith.
  • FIG. 6 represents an embodiment of a circuit 13 for biasing the bodies of the P-channel MOS transistors, as well as the transistors M10L, M10M and M10R and the resistive means 14 associated with the comparator 12 and the feedback of the regulator .
  • the circuit 1 ' consists of a current source I, a diode D, resistors R1 and R2, and transistors Q D , Q3 and Q4 as described above in relation to FIG. 1.
  • the transistors Q1 and Q2 of FIG. 1 are, for example, each replaced by three bipolar PNP type transistors respectively associated with the terminals E M , E L and S or, as shown, by two multi-emitter transistors whose respective collectors are connected to the collectors of the transistors Q3 and Q4 and respectively define the output terminals 3 and 4 of the circuit 1 '.
  • a first transmitter, respectively Q1M or Q2M, of the multi-transmitter transistors is connected to the terminal E M
  • a second transmitter, respectively Q1L or Q2L is connected to the terminal E L
  • a third transmitter, respectively Q1R or Q2R is connected to terminal S.
  • the operation of circuit 1 ' is similar to that of circuit 1 exposed in relation to FIG. 1 with the difference that its supply voltage is always the highest voltage among the voltages V M , V L and V R.
  • Terminal 4 is connected to the respective bases of three bipolar PNP transistors Q5M, Q5R and Q5L of circuit 2 'whose emitters are respectively connected to terminals E M , S and E L.
  • the respective collectors of the transistors Q5M, Q5R and Q5L are connected to the drains of N-channel MOS transistors M11M, M11R and M11L, the respective sources of which are connected to ground.
  • N-channel MOS transistors M3L, M3R and M3M, the respective sources of which are connected to ground, are mounted as a diode on the transistors M11L, M11R and M11M.
  • the respective drains of the transistors M3L and M3M are connected, via an N-channel MOS transistor M4L, M4M, the gate of which is connected to the respective M3L or M3M transistor, to the collector of a bipolar PNP transistor Q6L, Q6M (or to the common collector of a multi-emitter transistor).
  • the drain of the transistor M3R is directly connected to the collectors of the transistors Q6L and Q6M.
  • the respective drains of the transistors M3L and M3M are also connected to the collector of a bipolar transistor of PNP type, respectively Q6RA or Q6RB, the emitter of which is connected to the terminal S.
  • the respective bases of the transistors Q6RA, Q6RB, Q6L and Q6M are connected to terminal 3.
  • the collectors of the transistors Q6RA and Q6RB deliver, respectively, control potentials V GL and V GM on the gates of the transistors M10L and M10M (FIG. 6).
  • the collector of the multi-emitter transistor Q6L-Q6M delivers a control potential V GR on the gate of the transistor M10R ( Figure 6).
  • circuit 2 The operation of circuit 2 'described above is deduced from that of circuit 2 of FIG. 1 with regard to the transistors Q5, Q6, M3 and M11 assigned the respective letters M, R and L, the higher of the voltages V M , V L , V R causing the transistors Q5, Q6, M3 and M11 to carry the corresponding letter and blocking the other transistors.
  • the circuit 10 comprises two P-channel MOS transistors M12L and M12M connected in series between the respective collectors of the transistors Q6RA and Q6RB.
  • the common electrode of the transistors M12L and M12M is connected to the common collector of the transistors Q6L and Q6M.
  • the role of the transistors M12L and M12M is to block the two power transistors among the transistors M10L, M10M and M10R which are associated with the two lowest voltages among the voltages V M , V L and V R.
  • Two P-channel MOS transistors M14 and M15 are connected in series and in a diode between a terminal V B and the common gates of the transistors M12L and M12M.
  • the terminal V B represents the output terminal of the circuit 13 for biasing the bodies of the P channel transistors which will be described hereinafter in relation to FIG. 6.
  • the terminal V B is at the potential of the highest voltage among the voltages V M , V L and V R.
  • the drain of transistor M15 is connected to the common drain of three N-channel MOS transistors M13L, M13R and M13M which are mounted as a current mirror on the respective transistors M11L, M11R and M11M.
  • circuits 2 ′ and 10 will be better understood in relation to FIGS. 7 and 8.
  • the circuit 13 for biasing the bodies of the P-channel transistors, in particular the M10L and M10M transistors, at the highest voltage among the voltages V M , V L and V R comprises three similar arrangements each made up of: three P-channel MOS transistors and one N-channel MOS transistor.
  • Each group of four transistors includes a P-channel transistor, M16M, M16R or M16L, respectively, connected between terminal E M , S or E L and terminal V B.
  • the respective gates of the transistors M16M, M16R and M16L are connected to the source of the N-channel MOS transistor M9M, M9R and M9L of the corresponding group.
  • the transistors M9M, M9R and M9L are mounted as a current mirror on the respective transistors M11M, M11R and M11L (FIG. 5).
  • the respective gates of the transistors M11M, M11R and M11L have been designated by terminals V BM , V BR and V BL to allow the transfer of the connections between FIGS. 5 and 6.
  • the two other MOS channel transistors P, respectively M7M and M8M, M7R and M8R, M7L and M8L, of each group of the circuit 13 have a first electrode connected to the terminal, respectively E M , S or E L , their gates being connected to the drain of the transistor M9 of the group corresponding.
  • a second electrode of the transistors M7M and M7R is connected to the drain of the transistor M9L.
  • a second electrode of the transistors M8L and M8R is connected to the drain of the transistor M9M.
  • a second electrode of the transistor M7L and M8M is connected to the drain of the transistor M9R.
  • the transistor M16 of the corresponding group establishes the potential of the terminal V B at the highest voltage and the transistors M7 and M8 of this group block the six P-channel MOS transistors of the other two groups by bringing their respective gates to the highest potential. Student. All the bodies of the P-channel transistors of circuit 13 are connected to terminal V B to prevent any short-circuit by the drain / body or source / body diodes.
  • the comparator 12 responsible for producing the RESET signal is biased by being connected to the terminal V B.
  • This comparator 12 having a very low consumption, the potential of the terminal V B is not substantially modified.
  • the comparator 12 can also be powered only by the voltage V R. Indeed, when generating the RESET logic signal, the highest voltage will always be the voltage V R.
  • FIG. 7 illustrates the operation of the voltage regulator according to the present invention when the highest voltage of the circuit corresponds to one of the supply voltages V M and V L. The operation is similar regardless of the higher voltage V M or V L.
  • FIG. 7 corresponds to normal operation of the regulator where the regulated voltage V R is produced from the voltage V L.
  • the blocked transistors which do not intervene in the operation have been eliminated, and the terminals V B and E L have been confused.
  • Circuit 1 has only been partially shown.
  • the transistor Q6L is found in series with the transistor M12L, the gate of which is biased by the transistors M14 and M15, and with the transistor M3L.
  • the transistor Q6L associated with the transistor M12L therefore constitutes a cascode current source charged by the transistor M3L, which is controlled by the transistors Q2L, Q5L and MllL, and whose output V GL is connected to the gate of the transistor M10L.
  • the operation described in relation to FIG. 1 is thus reproduced.
  • the potential of the gates of the transistors M12L and M12M is substantially equal to V L - 2V TH , where V TH represents the threshold voltage of the transistors M14 and M15.
  • the potential V GR present on the source of the transistor M12L is therefore substantially equal to V L - 2V TH , increased by the gate-source voltage drop of the transistor M12L.
  • This voltage drop is equal to the threshold voltage V TH of the transistor M12L plus a term due to the drain-source current of the transistor M12L and corresponding to the parabolic component of its gate-source voltage.
  • the potential V GR is greater than V L - V TH .
  • the potential V GM is, by the same reasoning, equal to the potential V GR , the transistor M12M being conductive but not crossed by any current.
  • V GR V GM > V L - V TH
  • the transistors M10R and M10M are blocked because their respective sources are at potentials lower than the voltage V L. Blocking the transistor M10M isolates the power supply V M , while blocking the transistor M10R causes the resistance of the feedback loop to correspond to the resistance R3 (R3A + R3B).
  • the output voltage V R is equal to V BG . (R3 + R4) / R4. It will be noted that, as the body of the transistor M10M is connected to the potential V L , the terminal E M is well completely isolated from the regulator and there is no short circuit between the terminals E M and S.
  • the potential difference between the source and the drain of the transistor M10L is too small to supply sufficient current to the load connected to the terminal S.
  • the loop feedback consisting of resistors R3A and R3B, transistor Q3 (not shown in Figure 6), transistor Q6L and transistor M12L, then lowers the potential V GL to a value near ground.
  • the transistor M3L then operates in triode, which unlocks the transistor M4L.
  • the unlocking of the transistor M4L leads to the conduction of the transistor M10R which then short-circuits the resistors R3A and R3B.
  • the voltage V R cannot in this case be maintained at the desired nominal value and decreases.
  • the feedback loop continues to operate by the transistor M10R and the resistor R5, which guarantees that the voltage V BG is maintained at the chosen reference value.
  • the regulator When the voltage V L becomes lower than the voltage V R or disappears, the regulator is then in an operating mode where it is supplied by the voltage V R and where it is capable of generating the RESET signal which will be described later in relation to figure 8.
  • FIG. 8 does not represent the transistors of FIGS. 5 and 6 which are blocked and which do not intervene in the operation. In the case shown in FIG. 8, it is considered that the voltage V R is greater than the voltages V L and V M.
  • the two transistors Q6RA and Q6RB have their base-emitter junctions in parallel and their currents are therefore equal.
  • a current flows here in the two transistors M12L and M12M, we obtain as before, from a functional point of view, a source of current cascode.
  • the upper part (Q6RA, M12L and Q6RB, M12M) is here divided into two and produces, on the respective sources of the transistors M12L and M12M, the two blocking voltages V GL and V GM which are both greater than V R - V TH .
  • the transistors M10M and M10L are therefore blocked and, as their respective bodies are at potential V R , the terminals E M and E L are completely isolated from the regulator.
  • the lower part (M12L, M12M and M3R) of the cascode current source supplies the voltage V GR , determined by the feedback loop comprising the transistor M10R and the resistor R5.
  • V BG is well maintained at the specified value.
  • the voltage V BG is then used to index the threshold from which the RESET signal is produced by means of the comparator 12.
  • the switching of the comparator 12 occurs when the voltage V R becomes lower than V BG . [(R5 / R4). (R3A + R3B) / (R5 + R3B) + 1].
  • all the bodies of the N-channel MOS transistors are connected to their source.
  • all the bodies of the P-channel MOS transistors of circuit 13 as well as the bodies of the transistors M12L and M12M and the power transistors M10L and M10M are connected to the terminal V B at the potential of the highest voltage.
  • the body of transistor M14 is also connected to voltage V B as its source, and the bodies of transistors M10R and M15 are connected to their respective sources.
  • FIG. 3 The production and operation of a regulator as shown in FIG. 3 is deduced from the description of FIGS. 5 to 8. It suffices to modify the diagrams by removing all the transistors associated with the supply terminal E M (c 'ie all the transistors referenced by the letter M) and the transistor Q6RB ( Figure 5). Note, however, that a regulator produced in accordance with Figures 5 and 6 also operates with a single supply voltage.
  • Figures 9 and 10 illustrate another embodiment according to which the upper transistors of circuits 1 ′, 2 'and 10 are P-channel MOS transistors. In FIGS. 9 and 10, only the upper parts of circuits 1 ', 2' and 10 have been represented.
  • the transistors Q1R, Q1L and Q1M are replaced, respectively, by P-channel MOS transistors M1M, M1L and M1R (FIG. 9).
  • the transistors Q2M, Q2L and Q2R are replaced, respectively, by transistors M2M, M2L and M2R.
  • the bodies of these P channel MOS transistors are all connected to the terminal V B to guarantee the isolation between the voltages V M , V L and V R.
  • the bipolar transistors of circuit 2 ′ are replaced by P-channel MOS transistors whose references in FIG. 10 are similar by replacing the letter Q with the letter M. All the bodies of these P-channel MOS transistors are then connected to the terminal V B.
  • the present invention is capable of various variants and modifications which will appear to the man of art.
  • the sizing of the transistors and resistances are within the reach of those skilled in the art in function desired functional characteristics.
  • the regulator according to the invention can be fully realized in bipolar technology by replacing P channel MOS transistors by PNP transistors and N-channel MOS transistors by NPN transistors. In this case, it is not necessary to provide a bias circuit 13 bodies of P-channel MOS transistors. MOS transistors however constitute a preferred embodiment according to the invention insofar as they are controllable in voltage, which results in less consumption of the regulator.
  • the invention also applies to the realization of a negative voltage regulator. It is enough to do this, replace the P-channel MOS transistors with N channel transistors and vice versa, and replace the PNP-type bipolar transistors by type-transistors NPN and vice versa. The voltage selection is then made on the voltage with the most negative value.
EP97410121A 1996-10-25 1997-10-24 Spannungsregler Expired - Lifetime EP0838746B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9613281 1996-10-25
FR9613281A FR2755317B1 (fr) 1996-10-25 1996-10-25 Regulateur de tension a generation interne d'un signal logique

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EP0838746A1 true EP0838746A1 (de) 1998-04-29
EP0838746B1 EP0838746B1 (de) 2001-12-12

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DE (1) DE69709030D1 (de)
FR (1) FR2755317B1 (de)

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DE69925593D1 (de) * 1999-09-08 2005-07-07 St Microelectronics Srl Verfahren und Schaltungsanordnung zum Testen der Anwesenheit von mehreren Versorgungsspannungen in einer integrierten Schaltung
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Also Published As

Publication number Publication date
US6084389A (en) 2000-07-04
FR2755317A1 (fr) 1998-04-30
DE69709030D1 (de) 2002-01-24
EP0838746B1 (de) 2001-12-12
FR2755317B1 (fr) 1999-01-15

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