EP0808022B1 - Circuit de verrouillage fonctionant en synchronisme avec des signaux d'horloge - Google Patents

Circuit de verrouillage fonctionant en synchronisme avec des signaux d'horloge Download PDF

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Publication number
EP0808022B1
EP0808022B1 EP96118635A EP96118635A EP0808022B1 EP 0808022 B1 EP0808022 B1 EP 0808022B1 EP 96118635 A EP96118635 A EP 96118635A EP 96118635 A EP96118635 A EP 96118635A EP 0808022 B1 EP0808022 B1 EP 0808022B1
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EP
European Patent Office
Prior art keywords
inverter
circuit
level
switching unit
unit
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EP96118635A
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German (de)
English (en)
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EP0808022A2 (fr
EP0808022A3 (fr
Inventor
Koji Nii
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356026—Bistable circuits using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Definitions

  • the present invention relates to a semiconductor integrated circuit, particularly to a latch circuit operating in synchronization with clock signals.
  • FIG. 10 is a circuit diagram showing a conventional latch circuit.
  • a latch circuit 100 shown in Fig. 10 comprises five inverters 101, 102, 103, 104, and 105, two N-channel MOS (referred to as NMOS herein after) 106 and 107, and two P-channel MOS (referred to as PMOS herein after) 108 and 109.
  • the drains of the NMOS transistor 107 and the PMOS transistor 109 are connected to each other; their sources are also connected to each other.
  • the connected drains of the NMOS transistor 107 and the PMOS transistor 109 are connected to the input terminal of the inverter 103.
  • the connected sources of the NMOS transistor 107 and the PMOS transistor 109 are connected to the output terminal of the inverter 104.
  • the output terminal of the inverter 103 is connected to the input terminal of the inverter 104 so that the inverters 103 and 104 and the NMOS transistor 107 and the PMOS transistor 109 form a memory circuit 110.
  • the drains of the NMOS transistor 106 and the PMOS transistor 108 are connected to each other; their sources are also connected to each other.
  • the connected drains of the NMOS transistor 106 and the PMOS transistor 108 are connected to the input terminal of the inverter 103.
  • the connected sources of the NMOS transistor 106 and the PMOS transistor 108 are connected to the input terminal IN of the latch circuit 100.
  • the gates of the NMOS transistor 107 and the PMOS transistor 108 are connected together to the output terminal of the inverter 101.
  • the inverter 101 receives external clock signals through the clock input terminal CLK.
  • the gates of the NMOS transistor 106 and the PMOS transistor 109 are connected together to the output terminal of the inverter 102.
  • the input terminal of the inverter 102 is connected to the output terminal of the inverter 101.
  • the connection point of the output terminal of the inverter 103 and the input terminal of the inverter 104 is connected to the input terminal of the inverter 105.
  • the output of the inverter 105 is also the output of the latch circuit 100 and is sent out through the OUT terminal.
  • the connection point of the input terminal of the inverter 103, the drain of the NMOS transistor 107, and the drain of the PMOS transistor 109 is referred to as the point A.
  • the connection point of the output terminal of the inverter 103 and the input terminal of the inverter 104 is referred to as the point B.
  • the NMOS transistor 106 and the PMOS transistor 108 form a transmission gate; similarly, the NMOS transistor 107 and the PMOS transistor 109 form another transmission gate.
  • the inverter 101 When an "L" signal enters into the clock input terminal CLK, the inverter 101 produces an “H” output and the inverter 102 produces an “L” output. Accordingly, the NMOS transistor 106 and the PMOS transistor 108 go off; and the NMOS transistor 107 and the PMOS transistor 109 come on.
  • the memory circuit 110 maintains the data signal levels at the points A and B. The data signal levels held at the trailing edge of the clock signal received at the clock input CLK terminal are stored in the memory circuit 110 while the clock signal is "L". Even if a new signal is received at the data input terminal IN, the output through the data output terminal OUT does not change as long as the clock signal is "L".
  • the latch circuit 100 In a case in which the latch circuit 100 is used as a sense latch of a sense amplifier of a memory, a desired memory cell of a memory cell array is designated with word lines and the stored data of the memory cell is transferred to the data input terminal IN of the latch circuit 100 through bit lines, data lines, and the sense amplifier. As described above, a conventional latch circuit 100 holds data at the trailing edge of a clock signal. Therefore, when the latch circuit is used as a sense latch, the data to be stored in the latch circuit 100 or the data to be read from the desired memory cell must exist at the data input terminal IN before the clock signal starts to fall.
  • the object of the present invention is to solve the aforementioned problem and to provide a latch circuit that operates properly regardless of the timing of change in the level of the clock signal.
  • the present invention relates to a latch circuit operating in synchronization with clock signals.
  • the latch circuit of the present invention comprises (a) a memory unit including a first inverter and a second inverter, the output terminal of the first inverter being connected to the input terminal of the second inverter and the output terminal of the second inverter being connected to the input terminal of the first inverter, (b) a first switching unit, comprising a MOS transistor, for example, which couples the input terminal of the first inverter with the ground, (c) a second switching unit and a third switching unit, each comprising a MOS transistor, for example, which are connected together in series between the ground and the input terminal of the second inverter of the memory unit, (d) a first control unit for controlling the first switching unit according to binary data signals received from outside, (e) a second control unit for controlling the second switching unit according to data signals, (f) a delay unit for transmitting, with delay, the signal level at the input terminal of the second inverter of the memory unit, and (g) a third control unit for controlling the third switching unit according to both the clock
  • the second control unit controls the second switching unit according to the external data signals so that the second switching unit operates in a complementary way to the first switching unit.
  • the memory unit holds the level of the data signal written therein when both the first and third switching units are off.
  • the third control unit comprises a two-input AND circuit and turns on the third switching unit when the levels of both the two inputs of the AND circuit are "H", that is, when both the clock signal received from outside and the signal transferred through the delay circuit have "H" levels.
  • the present invention also provides a latch circuit, operating in synchronization with clock signals, comprising (a) a memory unit including a first inverter and a second inverter, the output terminal of the first inverter being connected to the input terminal of the second inverter and the output terminal of the second inverter being connected to the input terminal of the first inverter, (b) a first switching unit, comprising a MOS transistor, for example, which couples the input terminal of the first inverter of the memory unit with the ground, (c) a second switching unit, comprising a MOS transistor, for example, which is connected between the ground and the input terminal of the second inverter of the memory unit, (d) a first control unit for controlling the first switching unit according to binary data signals received from outside, (e) a delay unit for transmitting, with delay, the signal level at the input terminal of the second inverter of the memory unit, and (f) a second control unit for controlling the second switching unit according to the data signals from outside, the clock signals also received from outside, and
  • the second control unit turns off the second switching unit when the first switching unit is on.
  • the memory unit holds the level of the data signal written therein when both the first and second switching units are off.
  • the second control unit comprises a three-input AND circuit and turns on the second switching unit when the level of each input terminal of the AND circuit is "H", that is, when the data signal from outside, the clock signal received also from outside, and the signal level transmitted through the delay unit are all "H".
  • the aforementioned latch circuit may further comprise a fourth switching unit connected between the input terminal of the second inverter and the power supply, and a fourth control unit for controlling the fourth switching unit according to the binary data signals received from outside.
  • the fourth control unit controls the fourth switching unit, comprising a MOS transistor, for example, so that the fourth switching unit operates, according to the data signals received from outside, in the same way as the first switching unit does.
  • the present invention further provides a latch circuit, operating in synchronization with clock signals, comprising (a) a memory unit including a first inverter and a second inverter, the output terminal of the first inverter being connected to the input terminal of the second inverter and the output terminal of the second inverter being connected to the input terminal of the first inverter, (b) a first switching unit, comprising a MOS transistor, for example, which couples the input terminal of the second inverter with the power supply, (c) a second switching unit, comprising a MOS transistor, for example, which is connected between the ground and the input terminal of the first inverter of the memory unit; (d) a first control unit for controlling the first switching unit according to binary data signals received from outside, (e) a delay unit for transmitting, with delay, the signal level at the input terminal of the second inverter of the memory unit, and (f) a second control unit for controlling the second switching unit according to the data signals from outside, the clock signals also received from outside, and the signal levels
  • the second control unit turns off the second switching unit when the first switching unit is on.
  • the memory unit holds the level of the data signal written therein when both the first and second switching units are off.
  • the second control unit comprises a three-input AND circuit and turns on the second switching unit when the level of each input terminal of the AND circuit is "H", that is, when the data signal from outside, the clock signal from outside, and the signal level transmitted through the delay unit are all "H".
  • the input terminal of the delay circuit of the aforementioned latch circuit may be connected to the output terminal of the second inverter of the memory unit through at least one inverter.
  • the present invention further provides a latch circuit, operating in synchronization with clock signals, comprising (a) a memory unit including an inverter, a first switching unit, comprising, for example, a plurality of MOS transistors connected in series, which is connected between the input terminal of the inverter and the power supply, and a second switching unit, comprising for example, a plurality of MOS transistors connected in series, which is connected between the output terminal of the inverter and the ground, (b) a third switching unit, comprising a MOS transistor, for example, which is connected between the input terminal of the inverter and the power supply, (c) a fourth switching unit, comprising a MOS transistor, for example, which is connected between the input terminal of the inverter and the ground, (d) a first control unit for controlling the third switching unit according to binary data signals received from outside, (e) a delay unit for transmitting, with delay, the signal level at the input terminal of the inverter of the memory unit, and (f) a second control unit for
  • the first switching unit operates according to the signal level of the output terminal of the inverter and the output control signal level produced by the second control unit.
  • the second switching unit operates according to the signal level of the output terminal of the inverter and the output control signal level produced by the first control unit.
  • the first switching unit is off when the fourth switching unit is on, while the second switching unit is off when the third switching unit is on, the second switching unit operating in a complementary way to the first switching unit.
  • the first control unit turns off the third switching unit when the fourth switching unit is on, while the second control unit turns off the fourth switching unit when the third switching unit is on.
  • the memory unit holds the level of the data signal written therein when both the third and fourth switching units are off.
  • the second control unit comprises a three-input AND circuit and turns on the fourth switching unit when the level of each input terminal of the AND circuit is "H", that is, when the data signal from outside, the clock signal from outside, and the signal level transmitted through the delay unit are all "H".
  • the input terminal of the delay circuit may be connected to the output terminal of the inverter of the memory unit through at least one inverter.
  • Fig. 1 is a circuit diagram of the latch circuit of Embodiment 1 of the present invention.
  • Latch circuit 1 in Fig. 1 comprises a two-input AND circuit 2, six inverters 3, 4, 5, 6, 7, and 8, three NMOS transistors 9, 10, and 11, and a delay circuit 12.
  • the delay circuit 12 is formed, for example, of a plurality of inverters in series so that the input signal is not inverted, or with an extended patterned wiring for producing a larger capacitance.
  • the inverters 4 and 3 function as the first and second inverters in this embodiment.
  • the memory circuit 15 forms the memory unit of this embodiment.
  • the NMOS transistor 11 functions as the first switching unit of this embodiment; the NMOS transistor 10, the second switching unit of this embodiment; the NMOS transistor 9, the third switching unit of this embodiment; the inverter 6, the first control unit of this embodiment; the inverters 5 and 6, the second control unit of this embodiment; the AND circuit 2, the third control unit of this embodiment; and the delay circuit 12, the delay unit of this embodiment.
  • the output terminal of the inverter 3 is connected to the input terminal of the inverter 4, and the output terminal of the inverter 4, in turn, is connected to the input terminal of the inverter 4.
  • the inverters 3 and 4 form a memory circuit 15.
  • the drain of the NMOS transistor 9 and the input terminal of the delay circuit 12 are connected together to the connection point of the input terminal of the inverter 3 and the output terminal of the inverter 4.
  • the drain of the NMOS transistor 10 is connected to the source of the NMOS transistor 9, and the source of the NMOS transistor 10 is grounded.
  • the output terminal of the delay circuit 12 is connected to one of the input terminals of the AND circuit 2.
  • the other terminal of the AND circuit 2 is connected to the clock input terminal CLK which receives the external clock signal.
  • the output terminal of the AND circuit 2 is connected to the gate of the NMOS transistor 9.
  • the drain of the NMOS transistor 11 is connected to the connection point of the output terminal of the inverter 3 and the input terminal of the inverter 4 and the source of the NMOS transistor 11 is grounded.
  • the gate of the NMOS transistor 11 is connected to the input terminal of the inverter 5 and the output terminal of the inverter 6.
  • the output terminal of the inverter 5 is connected to the gate of the NMOS transistor 10.
  • the input terminal of the inverter 6 is connected to the data input terminal IN of the latch circuit 1 which receives external data signals.
  • the inverters 7 and 8 are connected in series forming a series circuit.
  • the input terminal of the inverter 7 is connected to the connection point of the output terminal of the inverter 3 and the input terminal of the inverter 4.
  • the output terminal of the inverter 8 is connected to the data output terminal OUT of the latch circuit 1.
  • the connection point of the input terminal of the inverter 3 and the output terminal of the inverter 4 is referred to as the point A; the connection point of the output terminal of the inverter 3 and the input terminal of the inverter 4, the point B; and the output terminal of the delay circuit 12, the point D.
  • Fig. 2 is a timing chart of the latch circuit 1 as shown in Fig. 1.
  • the operations of the latch circuit 1 will be described in detail with reference to Figs. 1 and 2.
  • the data input terminal IN is set at "H” by a precharger circuit (not shown) as an initial state. Accordingly, the output terminals of the inverters 6 and 5 are set at "L” and "H” respectively. Then the NMOS transistor 11 is off while the NMOS transistor 10 is on.
  • the output of the AND circuit 2 is always “L” regardless of the levels of the point D or the point A.
  • the NMOS transistor 9 is off. Therefore, the memory circuit 15 does not have a path to connect itself to the ground and hence holds the initial data. Accordingly the data output terminal OUT has the same level as the initial data stored in the memory circuit.
  • the level of the signal input to the data input terminal IN changes depending upon the data of the memory cell to be read.
  • the latch circuit 1 does nothing and the "H” level data is output from the data output terminal OUT.
  • the level of the signal provided to the data input terminal IN is switched from “H” to "L”.
  • the NMOS transistor 10 goes off and the NMOS transistor 11 comes on. Accordingly, the point B is grounded through the NMOS transistor 11. Therefore the levels of the points B and A become “L” and “H” respectively and the levels of those points become stable.
  • the output from the data output terminal OUT changes from "H” to "L”.
  • the precharger circuit switches the level of the data input terminal IN to "H".
  • the latch circuit 1 performs the reset operation and the output is reset.
  • the timing is shown as “a” in Fig. 2.
  • the delay circuit 12 must delay the signal transmission long enough so that the "H" level of the point A of the memory circuit 15 completely changes to the "L” level.
  • the delay time of the delay circuit 12 must be set to ensure that transition. The time required to complete the operation of the latch circuit 1 can be adjusted only with the delay time of the delay circuit 12. Hence one does not have to be concerned about other timings.
  • the duration of the "H" level of the clock signal should be longer than the time required for the memory circuit 15 to be reset.
  • Fig. 3 is a circuit diagram of the inverters used in the latch circuit 1 of Embodiment 1.
  • the inverter shown in Fig. 3 comprises a PMOS transistor 20 and an NMOS transistor 21.
  • the power supply voltage Vcc is applied to the source of the PMOS transistor 20.
  • the drain of the PMOS transistor 20 is connected to the drain of the NMOS transistor 21 and the connection point is an output of the inverter.
  • the source of the NMOS transistor 21 is grounded.
  • the gates of the PMOS transistor 20 and the NMOS transistor 21 are connected to form an input of the inverter.
  • Embodiment 2 when the level of the point A of the memory circuit 15 changes from “L” to “H”, the PMOS transistor 20 of the inverter 4 comes on and the NMOS transistor 21 goes off thus causing the output level of the inverter 4 to change to "H".
  • the PMOS transistor 20 which has a narrower gate width so that its "on” resistance is large, together with a MOS transistor, which has a wider gate width so that its "on” resistance is small.
  • Embodiment 2 The latch circuit using these kind of inverters is referred to as Embodiment 2.
  • Fig. 4 is a circuit diagram of a latch circuit 25 of Embodiment 2 of the present invention.
  • the like reference numerals of Figs. 1 and 4 indicate identical or functionally similar elements. Thus an explanation of those elements will not be repeated and only the differences with Fig. 1 will be described below.
  • the latch circuit 25 in Fig. 4 is obtained by adding a PMOS transistor 26 to the latch circuit 1 of Fig. 1.
  • the drain of the PMOS transistor 26 is connected to the point A of the memory circuit 15 and the gate of the PMOS transistor 26 is connected to the output terminal of the inverter 6.
  • the power supply voltage Vcc is applied to the source of the PMOS transistor 26.
  • the PMOS transistor 26 forms the fourth switch of Claim 10 and the inverter 6 forms the fourth control unit of Claim 10.
  • Fig. 5 is a circuit diagram of a latch circuit 30 of Embodiment 3 of the present invention.
  • the like reference numerals of Figs. 1 and 5 indicate identical or functionally similar elements. Thus an explanation of those elements is not given and only the differences with Fig. 1 will be described below.
  • the latch circuit 30 as shown in Fig. 5 is obtained by removing the AND circuit 2, the inverter 5, and the NMOS transistor 10 from the latch circuit 1 shown in Fig. 1 and by adding a two-input NAND circuit 31 and a two-input NOR circuit 32.
  • the output terminal of the inverter 6 is connected to the gate of the NMOS transistor 11 and also to one of the two input terminals of the NOR circuit 32.
  • the other input terminal of the NOR circuit 32 is connected to the output terminal of the NAND circuit 31.
  • One of the two input terminals of the NAND circuit 31 is connected to the output terminal of the delay circuit 12 while the other input terminal of the NAND circuit 31 is connected to the clock input terminal CLK.
  • the output terminal of the NOR circuit 32 is-connected to the gate of the NMOS transistor 9.
  • the drain of the NMOS transistor 9 is connected to the point A of the memory circuit 15 and its source is grounded.
  • the inverter 6 forms the first control unit of this embodiment.
  • the inverter 6, the NAND circuit 31, and the NOR circuit 32 form the second control unit of this embodiment.
  • the NMOS transistor 11 forms the first switching unit of this embodiment; the NMOS transistor 9, the second switching unit of this embodiment; and the memory circuit 15, the memory unit of this embodiment.
  • the timing chart for the latch circuit 30 is the same as that shown in Fig. 2.
  • the data input terminal IN is set to "H” by a precharger circuit (not shown) as an initial state. Accordingly, the level of the output terminal of the inverter 6 is "L” and the NMOS transistor 11 is off.
  • the output of the NAND circuit 31 is "H” regardless of the level of the output terminal D of the delay circuit 12 or the level of the terminal A of the memory circuit 15.
  • the output of the NOR circuit 32 is "L” and hence the NMOS transistor 9 is off. Therefore, the memory circuit 15 does not have a path to connect itself to the ground and therefore holds the initial data. Accordingly the data output terminal OUT has the same level as the initial data stored in the memory circuit.
  • the level of the signal input to the data input terminal IN changes depending upon the data of the memory cell to be read.
  • the latch circuit 30 does nothing and the "H” level data (the reset level) is output from the data output terminal OUT.
  • the level of the signal provided to the data input terminal IN is switched from “H” to "L”.
  • the NMOS transistor 11 is turned on. Accordingly the point B of the memory circuit 15 is grounded through the NMOS transistor 11. Therefore the levels of the points B and A become “L” and “H” respectively and the levels of those points become stable.
  • the output level from the data output terminal OUT changes from "H” to "L”.
  • the precharger circuit After the data latched in the memory circuit 15 is output from the data output terminal OUT, the precharger circuit switches the level of the data input terminal IN to "H".
  • the latch circuit 30 performs the reset operation again and the output is reset.
  • the timing is shown as "a” in Fig. 2.
  • the time required to complete the reset operation of the latch circuit 30 can be adjusted only with the delay time of the delay circuit 12. Hence one does not have to be concerned about other timings.
  • the latch circuit 30 of Embodiment 3 of the present invention provides the same effect as Embodiment 1. Further, the level of the point A of the memory circuit 15 changes its level from “H” to “L” through only one transistor, namely the NMOS transistor 9. Therefore, the transition of the level of the point A of the memory circuit 15 from “H” to "L” and that for the point B from “L” to “H” are faster. That is, the write performance of the circuit 15 has been improved.
  • Embodiment 3 when the level of the point A of the memory circuit 15 changes from “L” to “H", the PMOS transistor 20 of the inverter 4 comes on and the NMOS transistor 21 goes off to cause the output level of the inverter 4 to change to "H".
  • the PMOS transistor 20 and the NMOS transistor 21 which have narrower gate widths so that their "on" resistances are larger, together with a MOS transistor, which has a wider gate width so that its "on” resistance is small.
  • the latch circuit using these kinds of inverters is referred to as Embodiment 4.
  • Fig. 6 is a circuit diagram of a latch circuit 35 of Embodiment 4 of the present invention.
  • the like reference numerals of Figs. 5 and 6 indicate identical or functionally similar elements. Thus an explanation of those elements will not be repeated and only the differences with Fig. 5 will be described below.
  • the latch circuit 35 in Fig. 6 is the same as the latch circuit 30 shown in Fig. 5 except that the latch circuit 35 has an additional PMOS transistor 36 and an inverter 37.
  • the drain of the PMOS transistor 36 is connected to the point A of the memory circuit 15; the gate of the PMOS transistor 36 is connected to the output terminal of the inverter 37; and the input terminal of the inverter 37 is connected to the output terminal of the inverter 6.
  • the power supply voltage Vcc is applied to the source of the PMOS transistor 36.
  • the PMOS transistor 36 forms the fourth switching unit of this embodiment and the inverters 6 and 37 form the fourth control unit of this embodiment.
  • Fig. 7 is a circuit diagram of a latch circuit 40 of Embodiment 5 which has this modification.
  • the like reference numerals of Figs. 6 and 7 indicate identical or functionally similar elements. Thus an explanation of those elements will not be repeated and only the differences with Fig. 6 will be described below.
  • the latch circuit 40 is obtained by removing the NMOS transistor 11 from the latch circuit 35 shown in Fig. 6 and by connecting the output terminal of inverter 6 to one of the input terminals of the NOR circuit 32 and to the input terminal of the inverter 37.
  • the PMOS transistor 36 forms the first switching unit of this embodiment and the NMOS transistor 9 forms the second switching unit of this embodiment.
  • the inverters 6 and 37 form the first control unit of this embodiment; the inverter 6, the NAND circuit 31, and the NOR circuit 32, the second control unit of this embodiment; and the memory circuit 15, the memory unit of this embodiment.
  • the timing chart for the latch circuit 40 is the same as that shown in Fig. 2. Since the reset operation is similar to that for the latch circuit 35 in Fig. 6 except that the latch circuit 40 does not include the NMOS transistor 11, the description of the reset operation of the latch circuit 40 will not be given.
  • the data latch operation of the latch circuit 40 will be described. After the completion of the reset operation, the level of the signal input to the data input terminal IN changes depending upon the data of the memory cell to be read. When data with an "H" level is read from the memory cell, the latch circuit 30 does nothing.
  • the latch circuit 40 of Embodiment 5 has the same structure as the latch circuit 35 except that the latch circuit 40 does not include the NMOS transistor 11 and it works the same way as the latch circuit 35. That is, the latch circuit 40 provides the same effect as the latch circuit 1 of Embodiment 1.
  • Fig. 8 is a circuit diagram of a latch circuit 45 of Embodiment 6.
  • the like reference numerals of Figs. 7 and 8 indicate identical or functionally similar elements. Thus an explanation of those elements will not be repeated and only the differences with Fig. 7 will be described below.
  • the latch circuit 45 is obtained by removing the inverter 4 from the latch circuit 40 shown in Fig. 7 and by adding to the latch circuit 40 PMOS transistors 46 and 47 and NMOS transistors 48 and 49.
  • the memory circuit 15 of the latch circuit 40 is now referred to as the memory circuit 50.
  • the memory circuit 50 comprises the inverter 3, the PMOS transistors 46 and 47, and the NMOS transistors 48 and 49.
  • the PMOS transistors 46 and 47 and the NMOS transistors 48 and 49 are connected in series: the drain of the PMOS transistor 46 is connected to the source of the PMOS transistor 47; the drain of the PMOS transistor 47, to the drain of the NMOS transistor 48; and finally the source of the NMOS transistor 48, to the drain of the NMOS transistor 49. Further the power supply voltage Vcc is applied to the source of the PMOS transistor 46 and the source of the NMOS transistor 49 is grounded.
  • the connection point of the drain of the PMOS transistor 47 and the drain of the NMOS transistor 48 is connected to the input terminal of the inverter 3. This connection point is referred to as the point A of the memory circuit 50.
  • the gates of the PMOS transistor 46 and the NMOS transistor 49 are connected together to the output terminal of the inverter 3. This connection point is referred to as the point B of the memory circuit 50.
  • the gate of the PMOS transistor 47 is connected to the output terminal of the NOR circuit 32 and the gate of the NMOS transistor 48 is connected to the output terminal of the inverter 37.
  • the drain of the PMOS transistor 36, the drain of the NMOS transistor 9, and the input terminal of the delay circuit 12 are connected together to the point A of the memory circuit 50.
  • the input terminal of the inverter 7 is connected to the point B of the memory circuit 50.
  • the PMOS transistors 46 and 47 form the first switching unit of this embodiment and the NMOS transistors 48 and 49 form the second switching unit of this embodiment.
  • the inverter 3 forms the inverter of the memory unit of this embodiment and the memory circuit 50 forms the memory unit of this embodiment.
  • the PMOS transistor 36 forms the third switching unit of this embodiment; the NMOS transistor 9, the fourth switching unit of this embodiment; the inverters 6 and 37, the first control unit of this embodiment; and the inverter 6, the NAND circuit 31, and the NOR circuit 32, the second control unit of this embodiment.
  • the timing chart for the latch circuit 45 is the same as that shown in Fig. 2.
  • the data input terminal IN is set to "H” by a precharger circuit (not shown) as an initial state. Accordingly, the level of the output terminal of the inverter 37 is "H” causing the PMOS transistor 36 to be off and the NMOS transistor 48 to be on.
  • the level of the point A of the memory circuit 50 is "L"
  • the level of the point B is "H”
  • the level of the point B is "H"
  • the level of one of the input terminals of the NAND circuit 31 is “L” and hence the level of its output is “H” regardless of the level of the clock signal. Therefore, the output level of the NOR circuit 32 is "L”, which causes the NMOS transistor 9 to be off and the PMOS transistor 47 to be on.
  • the NMOS transistor 9 and the PMOS transistors 36 and 46 are off, and the PMOS transistor 47 and the NMOS transistors 48 and 49 are on. Therefore, the point A remains at "L” level and the memory circuit 50 can hold the initial data.
  • the level of the point B is "L" which causes the PMOS transistor 46 to be on and the NMOS transistor 49 to be off.
  • the level of the output terminal D of the delay circuit 12 is the same as the level of the point A of the memory circuit 50. Accordingly one of the input terminals of the NAND circuit 31 is "H”.
  • the other input terminal of the NAND circuit 31 is fed with the clock signal. If the level of the clock signal is "L”, the output level of the NOR circuit 32 is "L” and the NMOS transistor 9 is off while the PMOS transistor 47 is on. Thus the NMOS transistors 9 and 49 and the PMOS transistors 36 are off while the PMOS transistors 46 and 47 are on. Hence the level of the point A does not change.
  • the data latch operation After the completion of the reset operation described above, the level of the signal input to the data input terminal IN changes depending upon the data of the memory cell to be read.
  • the latch circuit 30 When data of an "H” level is read from the memory cell, the latch circuit 30 does nothing and the "H” level data (the reset level) is output from the data output terminal OUT.
  • the precharger circuit After the data latched in the memory circuit 50 is output from the data output terminal OUT, the precharger circuit switches the level of the data input terminal IN to "H".
  • the latch circuit 45 performs the reset operation again and the output is reset.
  • the timing is shown as "a” in Fig. 2.
  • the time required to complete the reset operation of the latch circuit 45 can be adjusted only with the delay time of the delay circuit 12. Hence one does not have to be concerned about other timings.
  • the latch circuit 45 of Embodiment 6 of the present invention provides the same effect as Embodiment 1. Further, the NMOS transistor 9 and the PMOS transistor 47 will not be on at the same time. Nor will the PMOS transistor 36 and the NMOS transistor 48 be on at the same time. Nor will the NMOS transistor 9 and the PMOS transistor 36 be on. Therefore, when the PMOS transistor 36 is on, the point A is assured to be disconnected to the ground, and when the NMOS transistor 9 is on, the point A is assured to be cut off from the power supply voltage Vcc. Thus, the level of the point A and the level of the point B are switched more securely and faster from "H" to "L” and from "L” to “H” respectively.
  • Embodiment 7 of the present invention is a latch circuit with this structure.
  • Fig. 9 is a circuit diagram of a latch circuit 60 of Embodiment 7 of the present invention.
  • the like reference numerals of Figs. 9 and 1 indicate identical or functionally similar elements. Thus an explanation of those elements will not be repeated and only the differences with Fig. 1 will be described below.
  • Fig. 9 and Fig. 1 The difference between Fig. 9 and Fig. 1 is that the input of the delay circuit 12 is connected to the connection point of the output terminal of the inverter 7 and the input terminal of the inverter 8 instead of to the connection point of the input terminal of the inverter 3 and the output terminal of the inverter 4.
  • the present embodiment has been described based on Embodiment 1 shown in Fig. 1, the present embodiment includes Embodiments 2 - 6 modified by changing the connection points of the input of the delay circuit in a similar way as described above.
  • the operation of the latch circuit 60 differs from that of latch circuit 1 in that the delay circuit 12 of the latch circuit 1 receives the change in the level of the point A directly while the delay circuit 12 of the latch circuit 60 receives the change through the inverters 3 and 7.
  • the delay time of the latch circuit 1 is determined only by the delay circuit 12, whereas the delay time of the latch circuit 60 is determined by the inverters 3 and 7 as well as by the delay circuit 12, which makes the delay operation more reliable. Further, this allows the delay time of the delay circuit to be shorter, which may reduce the number of inverters used therein and may shorten its patterned wiring so that the area of the print circuit board occupied by the wiring is reduced. This will reduce the production cost of the delay circuit 12.
  • a latch circuit of the present invention comprises a memory unit including a first inverter and a second inverter, the output terminal of the first inverter being connected to the input terminal of the second inverter and the output terminal of the second inverter being connected to the input terminal of the first inverter.
  • the input terminal of the first inverter is grounded through a first switching unit comprising, for example, an NMOS transistor.
  • the input terminal of the second inverter is also grounded through a second switching unit and a third switching unit, connected together in series, each comprising, for example, a MOS transistor.
  • the first switching unit and the second switching unit operate in a complementary way according to the binary data signals received from outside.
  • the third switching unit operates according to both the clock signals received from outside and the signal levels transmitted through the delay unit.
  • the second switching unit is controlled so that it operates in a complementary way to the first switching unit according to the binary data signals received from outside.
  • the memory unit holds the level of the data signal written therein when both the first and third switching units are off.
  • the third control unit is controlled by a two-input AND circuit and turns on the third switching unit when the levels of both the two inputs of the AND circuit are "H", that is, when both the clock signal received from outside and the signal transferred through the delay circuit have "H" levels.
  • the external clock signal may change its level before or after the external binary data signal changes its level. Therefore, one need not be concerned about the timing of the change of the clock signal level with regard to the timing of the change of the level of the data signal. This not only makes the circuit design simple but also allows the common clock signals of a 50% duty cycle to be used.
  • Another latch circuit of the present invention may comprise a memory unit including a first inverter and a second inverter, the output terminal of the first inverter being connected to the input terminal of the second inverter and the output terminal of the second inverter being connected to the input terminal of the first inverter.
  • the input terminal of the first inverter is grounded through a first switching unit comprising, for example, an NMOS transistor.
  • the input terminal of the second inverter is also grounded through a second switching unit comprising, for example, an NMOS transistor.
  • the first switching unit operates according to the binary data signals received from outside
  • the second switching unit operates according to the data signals, the clock signals received from outside, and the signal levels transmitted through the delay unit.
  • the second switching unit is off when the first switching unit is on.
  • the memory unit holds the level of the data signal written therein when both the first and second switching units are off.
  • a three-input AND circuit controls the second switching unit and turns on the second switching unit when the level of each input terminal of the AND circuit is "H", that is, when the data signal from outside, the clock signal received also from outside, and the signal level transmitted through the delay unit are all "H".
  • the aforementioned latch circuit may include a fourth switching unit, comprising, for example, an NMOS transistor through which the input terminal of the second inverter is connected to the power supply.
  • the fourth switching unit is controlled by the data signal received from outside. More specifically the fourth switching unit operates as the first switching unit does and turns on when the input terminal of the first inverter changes its level from "L" to "H".
  • Yet another latch circuit of the present invention may comprise a memory unit including a first inverter and a second inverter, the output terminal of the first inverter being connected to the input terminal of the second inverter and the output terminal of the second inverter being connected to the input terminal of the first inverter.
  • the input terminal of the first inverter is connected to the power supply through a first switching unit comprising an NMOS transistor, for example, and it is grounded through a second switching unit comprising, for example, an NMOS transistor.
  • the first switching unit operates according to the binary data signals received from outside
  • the second switching unit operates according to the data signals, the clock signals from outside, and the signal levels transmitted through the delay unit.
  • the second switching unit is off when the first switching unit is on.
  • the memory unit holds the level of the data signal written therein when both the first and second switching units are off.
  • a three-input AND circuit controls the second switching unit and turns on the second switching unit when the level of each input terminal of the AND circuit is "H", that is, when the data signal from outside, the clock signal from outside, and the signal level transmitted through the delay unit are all "H".
  • the external clock signal may change its level before or after the external binary data signal changes its level. Therefore, one need not be concerned about the timing of the change of the clock signal level with regard to the timing of the change of the level of the data signal. This not only makes the circuit design simple but also allows the common clock signals of a 50% duty cycle to be used.
  • the input terminal of the delay circuit of each of the aforementioned latch circuits may be connected to the output terminal of the second inverter of the memory unit through at least one inverter.
  • the delay time of the latch circuit is the sum of the delay time of the delay unit, the delay time of the second inverter of the memory unit, and the delay time of the inverter placed between the output terminal of the second inverter and the input of the delay unit. This allows the delay time of the delay unit to be shorter, which may reduce the number of inverters used in the delay unit and may shorten its patterned wiring so that the area of the print circuit board occupied by the wiring is reduced. This will reduce the production cost of the delay unit.
  • Still another latch circuit of the present invention comprises a memory unit including an inverter; a first switching unit comprising, for example, a plurality of MOS transistors connected in series, which is connected between the input terminal of the inverter and the power supply; and a second switching unit comprising, for example, a plurality of MOS transistors connected in series, which is connected between the output terminal of the inverter and the ground. It also comprises a third switching unit comprising, for example, a MOS transistor, which is connected between the input terminal of the inverter and the power supply; and a fourth switching unit comprising, for example, a MOS transistor, which is connected between the input terminal of the inverter and the ground.
  • the first switching unit operates according to the signal level of the output terminal of the inverter and the output control signal level produced by the second control unit.
  • the second switching unit operates according to the signal level of the output terminal of the inverter and the output control signal level produced by the first control unit.
  • the third switching unit operates according to the data signals received from outside.
  • the fourth switching unit operates according to the data signals, the clock signals from outside, and the level of the signal transmitted through the delay unit.
  • the first switching unit is off when the fourth switching unit is on whereas the second switching unit is off when the third switching unit is on, the second switching unit operating in a complementary way to the first switching unit.
  • the third switching unit is turned off when the fourth switching unit is on while the fourth switching unit is turned off when the third switching unit is on.
  • the memory unit holds the level of the data signal written therein when both the third and fourth switching units are off.
  • a three-input AND circuit controls the fourth switching unit and turns it on when the level of each input terminal of the AND circuit is "H", that is, when the data signal from outside, the clock signal received also from outside, and the signal level transmitted through the delay unit are all "H".
  • the input terminal of the delay unit of the above latch circuit may be connected to the output terminal of the inverter of the memory unit through at least one inverter.
  • the delay time of the latch circuit is the sum of the delay times of the delay unit, the inverter of the memory unit, and the inverter placed between the output terminal of the inverter of the memory unit and the input of the delay unit. This allows the delay time of the delay unit to be shorter, which may reduce the number of inverters used in the delay unit and may shorten its patterned wiring so that the area of the print circuit board occupied by the wiring is reduced. This will reduce the production cost of the delay unit.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)

Claims (11)

  1. Circuit de verrouillage (1; 25; 30; 35; 40; 45; 60) fonctionnant en synchronisme avec des signaux d'horloge (CLK) comprenant :
    une unité de mémoire (15; 50) incluant un premier inverseur et un deuxième inverseur (3, 4), la borne de sortie dudit premier inverseur étant connecté à la borne d'entrée dudit deuxième inverseur et la borne de sortie dudit deuxième inverseur étant connectée à la borne d'entrée dudit premier inverseur ;
    une première unité de commutation (11; 36) couplant ladite unité de mémoire soit à l'alimentation (Vcc), soit à la masse ;
    une deuxième unité de commutation (10) connectée entre la masse et la borne d'entrée dudit deuxième inverseur de ladite unité de mémoire ;
    une première unité de commande (6, 37) destinée à commander ladite première unité de commutation en fonction des signaux de données binaires reçus depuis l'extérieur ;
    une unité de retard (12) pour transmettre, avec un retard, le niveau du signal au niveau de la borne d'entrée dudit deuxième inverseur de ladite unité de mémoire ; et
    une deuxième unité de commande (2, 5, 31, 32) destinée à commander ladite deuxième unité de commutation en fonction des signaux de données provenant de l'extérieur, des signaux d'horloge provenant de l'extérieur et des niveaux de signaux transmis à travers ladite unité de retard.
  2. Circuit de verrouillage selon la revendication 1, dans lequel une première unité de commutation (11) relie la borne d'entrée dudit premier inverseur de ladite unité de mémoire à la masse.
  3. Circuit de verrouillage selon la revendication 1, dans lequel ladite première unité de commutation (36) relie la borne de sortie dudit premier inverseur de ladite unité de mémoire à l'alimentation.
  4. Circuit dé verrouillage selon la revendication 2 ou 3, dans lequel ladite deuxième unité de commande désactive ladite deuxième unité de commutation lorsque ladite première unité de commutation est active.
  5. Circuit de verrouillage selon la revendication 2 ou 3, dans lequel ladite unité de mémoire conserve le niveau du signal de données écrit dans celle-ci lorsque lesdites première et deuxième unités de commutation sont toutes deux désactivées.
  6. Circuit de verrouillage selon la revendication 2 ou 3, dans lequel lesdites première et deuxième unités de commutation comprennent chacune un transistor MOS.
  7. Circuit de verrouillage selon la revendication 1, dans lequel ladite deuxième unité de commande comprend une troisième unité de commutation (9) connectée entre la borne d'entrée dudit premier inverseur de ladite mémoire et la deuxième unité de commutation, une troisième unité de commande (5, 6) destinée à commander ladite deuxième unité de commutation en fonction desdits signaux de données et une quatrième unité de commande (2) destinée à commander ladite troisième unité de commutation en fonction des signaux d'horloge reçus depuis l'extérieur et des niveaux de signaux transmis à travers ladite unité de retard.
  8. Circuit de verrouillage selon la revendication 7, dans lequel ladite deuxième unité de commande commande ladite deuxième unité de commutation, en fonction des signaux de données externes, de telle sorte que ladite deuxième unité de commutation fonctionne de manière inverse par rapport à ladite première unité de commutation.
  9. Circuit de verrouillage selon la revendication 7, dans lequel ladite unité de mémoire conserve le niveau du signal de données écrit dans celle-ci lorsque ladite première et ladite troisième unités de commutation sont toutes deux désactivées.
  10. Circuit de verrouillage selon la revendication 7, dans lequel lesdites première, deuxième et troisième unités de commutation comprennent chacune un transistor MOS.
  11. Circuit de verrouillage selon la revendication 7, dans lequel ladite quatrième unité de commande (2) comprend un circuit ET à deux entrées et, de plus, active ladite troisième unité de commutation lorsque le niveau de chacune des deux entrées dudit circuit ET est haut («H»).
EP96118635A 1996-05-16 1996-11-20 Circuit de verrouillage fonctionant en synchronisme avec des signaux d'horloge Expired - Lifetime EP0808022B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP12174196 1996-05-16
JP121741/96 1996-05-16
JP12174196A JP3630847B2 (ja) 1996-05-16 1996-05-16 ラッチ回路

Publications (3)

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EP0808022A2 EP0808022A2 (fr) 1997-11-19
EP0808022A3 EP0808022A3 (fr) 1999-07-07
EP0808022B1 true EP0808022B1 (fr) 2003-10-01

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EP96118635A Expired - Lifetime EP0808022B1 (fr) 1996-05-16 1996-11-20 Circuit de verrouillage fonctionant en synchronisme avec des signaux d'horloge

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US (1) US5748541A (fr)
EP (1) EP0808022B1 (fr)
JP (1) JP3630847B2 (fr)
KR (1) KR100229857B1 (fr)
CN (1) CN1113464C (fr)
DE (1) DE69630203T2 (fr)
TW (1) TW320722B (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5898640A (en) * 1997-09-26 1999-04-27 Advanced Micro Devices, Inc. Even bus clock circuit
US6556060B1 (en) * 2002-06-06 2003-04-29 Analog Devices, Inc. Latch structures and systems with enhanced speed and reduced current drain
DE10343565B3 (de) * 2003-09-19 2005-03-10 Infineon Technologies Ag Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop
US20080258790A1 (en) * 2007-04-17 2008-10-23 Texas Instruments Incorporated Systems and Devices for Sub-threshold Data Capture
JP6974549B1 (ja) * 2020-07-17 2021-12-01 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. メモリ装置およびその入出力バッファ制御方法
CN114567299B (zh) * 2022-04-28 2022-09-09 深圳比特微电子科技有限公司 具有多路选择器功能的反相锁存器

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Publication number Priority date Publication date Assignee Title
US4160173A (en) * 1976-12-14 1979-07-03 Tokyo Shibaura Electric Co., Ltd. Logic circuit with two pairs of cross-coupled nand/nor gates
JPS6257196A (ja) * 1985-09-05 1987-03-12 Toshiba Corp 半導体メモリ
JP2969630B2 (ja) * 1988-10-25 1999-11-02 日本電気株式会社 読出し回路
JPH02141993A (ja) * 1988-11-21 1990-05-31 Toshiba Corp 半導体記憶装置
EP0650257A2 (fr) * 1988-12-16 1995-04-26 Advanced Micro Devices, Inc. Circuit d'initialisation
US5086236A (en) * 1990-08-27 1992-02-04 Advanced Micro Devices, Inc. Synchronizing circuit of two clock signals
US5257236A (en) * 1991-08-01 1993-10-26 Silicon Engineering, Inc. Static RAM
JP2826238B2 (ja) * 1992-10-22 1998-11-18 川崎製鉄株式会社 半導体メモリ
US5568429A (en) * 1995-07-05 1996-10-22 Sun Microsystems, Inc. Low power data latch with overdriven clock signals

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Publication number Publication date
EP0808022A2 (fr) 1997-11-19
CN1113464C (zh) 2003-07-02
DE69630203T2 (de) 2004-09-16
JPH09307410A (ja) 1997-11-28
TW320722B (fr) 1997-11-21
JP3630847B2 (ja) 2005-03-23
DE69630203D1 (de) 2003-11-06
KR970076821A (ko) 1997-12-12
CN1166033A (zh) 1997-11-26
US5748541A (en) 1998-05-05
EP0808022A3 (fr) 1999-07-07
KR100229857B1 (ko) 1999-11-15

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