EP0807314B1 - Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ - Google Patents

Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ Download PDF

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Publication number
EP0807314B1
EP0807314B1 EP96905347A EP96905347A EP0807314B1 EP 0807314 B1 EP0807314 B1 EP 0807314B1 EP 96905347 A EP96905347 A EP 96905347A EP 96905347 A EP96905347 A EP 96905347A EP 0807314 B1 EP0807314 B1 EP 0807314B1
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EP
European Patent Office
Prior art keywords
layer
filament
insulating layer
apertures
gate
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Expired - Lifetime
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EP96905347A
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German (de)
English (en)
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EP0807314A1 (fr
Inventor
David L. Bergeron
John M. Macaulay
Roger W. Barton
Jeffrey D. Morse
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Candescent Technologies Inc
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Candescent Technologies Inc
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Priority claimed from US08/383,408 external-priority patent/US5578185A/en
Priority claimed from US08/383,409 external-priority patent/US7025892B1/en
Application filed by Candescent Technologies Inc filed Critical Candescent Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/304—Field emission cathodes
    • H01J2201/30446—Field emission cathodes characterised by the emitter material
    • H01J2201/30453—Carbon types
    • H01J2201/30457—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/319—Circuit elements associated with the emitters by direct integration

Definitions

  • This invention relates to a method of creating a gated filament structures for a field emission display with filaments positioned in apertures.
  • the relative position of the majority of each filament tip to its associated aperture is substantially the same for a majority of the filament tips of the display. This relationship is maintained even for large displays where there are nonuniformities in the thickness of the insulating layer or in the plating of the filaments.
  • Field emission displays include a faceplate, a backplate and connecting walls around the periphery of the faceplate and backplate, forming a sealed vacuum envelope.
  • the envelope is held at vacuum pressure, which can be about 1 x 10 -7 torr or less.
  • the interior surface of the faceplate is coated with light emissive elements, such as phosphor or phosphor patterns, which define an active region of the display.
  • Field emission cathodes such as cones and filaments, are located adjacent to the backplate.
  • Application of an appropriate voltage at the extraction electrode releases electrons which are accelerated toward the phosphors on the faceplate. The accelerated electrons strike their targeted phosphors, causing the phosphors to emit light seen by the viewer at the exterior of the faceplate. Emitted electrons for each of the sets of emitters are intended to strike only certain targeted phosphors.
  • U.S. Patent No. 3,655,241 discloses fabricating field emitters using a screen with arrays of circular or square openings that is placed above a substrate electrode.
  • a deposition is performed simultaneously from two sources.
  • One of the sources consists of an emitter-forming metal, such as molybdenum, and atoms are deposited in a direction perpendicular to the substrate electrode.
  • the other source consists of a closure material, such as a molybdenum-alumina composite. Atoms of the closure material are caused to impinge on the screen at a small angle to the substrate. The closure material progressively closes the openings in the screen.
  • the emitter-forming metal is deposited in the shape of cones or pyramids, depending on whether the screen openings are circular or square.
  • U.S. Patent No. 5,164,632 Part of an aluminum plate is anodically oxidized to create a thin alumina layer having pores that extend nearly all the way through the alumina. An electrolytic technique is used to fill the pores with gold for the field emitters. An address line is formed over the filled pores along the alumina side of the structure, after which the remaining aluminum and part of the adjoining alumina are removed along the opposite side of the structure to re-expose the gold in the pores. Part of the re-exposed gold is removed during an ion-milling process utilized to sharpen the field emitters. Gold is then evaporatively deposited onto the alumina and partly into the pores to form the gate electrode.
  • Field emitters are fabricated in U.S. Patent No. 5,150,192 by creating openings partway through a substrate by etching through a mask formed on the bottom of the substrate. Metal is deposited along the walls of the openings and along the lower substrate surface. A portion of the thickness of the substrate is removed along the upper surface. A gate electrode is then formed by a deposition/planarization procedure. Cavities are provided along the upper substrate surface after which the hollow metal portions in the openings are sharpened to complete the field emitter structures.
  • large area field emission displays require a relatively strong substrate for supporting the field emitters extending across the large emitter area.
  • the requisite substrate thickness is typically several hundred microns to 10 mm or more.
  • a gated area field emitter consists of cones formed on a highly resistive layer that overlies a highly conductive layer situated on an electrically insulating supporting structure.
  • the highly resistive layer has a resistivity of 10 4 to 10 5 ohm-cm. The resistive layer limits the currents through the electron-emissive cones so as to protect the field emitter from breakdown and short circuits.
  • a field emission cathode relies on there being a very strong electric field at the surface of a filament or generally on the surface of the cathode. Creation of the strong field is dependent on, (i) the sharpness of the cathode tip and (ii) the proximity of the extraction electrode (gate) and the cathode. Application of the voltage between these two electrodes produces the strong electric field. Emission nonuniformity is related to the nonuniformity in the relative positions of the emitter tip and the gate. Emission nonuniformity can also result from differences in the sharpness of the emitting tips.
  • Busta "Vacuum Microelectronics-1992,” J. Micromech. Microeng ., Vol. 2, 1992 pp. 43- 74 provides a general review of field-emission devices. Among other things, Busta discusses Utsumi, "Keynote Address, Vacuum Microelectronics: What's New and Exciting," IEEE Trans. Elect. Dev. , Oct. 1990, pp. 2276-2283, who suggests that a filament with a rounded end is the best shape for a field emitter. Also of interest is Fischer et al., "Production and Use of Nuclear Tracks: Imprinting Structure on Solids," Rev. Mod. Phys. , Oct. 1983, pp. 907- 948, which deals with the use of charged-particle tracks in manufacturing field emitters according to a replica technique.
  • a well collimated source of evaporant as taught in U.S. Patent No. 3,655,241, is necessary in order to obtain uniformity of cone or filament formation across the entire field emission display.
  • the majority of evaporant is deposited on interior surfaces of the evaporation equipment.
  • the combination of the expensive of the evaporation equipment, and the wastage of evaporant, is undesirable for commercial manufacturing and is compounded as the size of the display increases. With large displays, there are nonuniformities in the thickness of the insulating layer and the plating of the filaments.
  • WO94/28569 describes a microtip display device and method of manufacture using heavy ion lithography.
  • a microtip electron source and a cathodoluminescent anode are produced and then assembled.
  • the source is manufactured by forming a stack of layers, forming holes therein and then forming microtips in said holes.
  • latent traces randomly distributed in a superficial layer of the stack are formed by irradiating the layer with heavy ions. The traces are then exposed by etching until holes appear in said layer.
  • the invention provides a method of creating gated filament structures for a field emission display, comprising the consecutive or non-consecutive steps of:
  • the invention provides a field emission display device comprising a gated filament structure formed using a method as aforesaid.
  • An advantage of the invention is that it can provide gated filament structures for large field emission displays.
  • a further advantage of the invention is that it can provide gated filament structures that are electroplated.
  • Another advantage of the invention is that it can provide a commercial manufacturing process for forming filaments in a large field emission display.
  • Yet another advantage of the invention is that it can provide a commercial manufacturing process for forming filaments in a large field emission display using electroplating.
  • Still a further advantage of the invention is that it can provide a method for forming filaments in a field emission display which uses spacers as an etch mask and as part of the mold for plating the filament structures.
  • a multi-layer structure in one preferred embodiment for creating gated filament structures in a field emission display, includes a substrate, an insulating layer and a metal gate layer positioned on at least a portion of a top surface of the insulating layer.
  • an insulating substrate is, (i) a conductive or semi-conductive substrate with an insulating layer on a top surface of the substrate, (ii) a conductive or semi-conductive substrate with patterned insulating regions on a top surface of the substrate or (iii) an insulating substrate.
  • a plurality of patterned gates are provided and define a plurality of gate apertures on the top surface of the insulating layer.
  • a plurality of spacers are formed in the gate apertures at edges of the patterned gates on the top surface of the insulating layer.
  • the patterned gates can be part of the initial multi-layer structure, or formed thereafter.
  • a plurality of spacers are formed in the gate apertures at edges of the patterned gates on the top surface of the insulating layer.
  • the spacers are used as masks for etching the insulating layer and forming a plurality of pores in the insulating layer.
  • the pores are plated with a filament material that extends form the pores, into the gate apertures, and creates a plurality of filaments.
  • the spacers are then removed.
  • the multi-layer structure can include a conductivity layer on at least a portion of a top surface of the substrate.
  • a multi-layer structure in another preferred embodiment for creating gated filament structures in a field emission display, includes a substrate, an insulating layer, a metal gate layer positioned on a top surface of the insulating layer and a gate encapsulation layer positioned on a top surface of the metal gate layer.
  • a plurality of patterned gate are provided and define a plurality of gate apertures on the top of the insulating layer.
  • a plurality of spacers are formed in the gate apertures at edges of the patterned gates on the top surface of the insulating layer. The spacers are used as masks for etching the insulating layer and forming a plurality of pores in the insulating layer. The pores are plated with a filament material to create a plurality of filaments.
  • the majority of filament tips can, (i) extend between the top and bottom metal gate layer surfaces, (ii) extend below the bottom metal gate layer surface, or (iii) extend above the top metal gate layer surface.
  • Each filament of the display can be electroplated.
  • the gated filament structure for a field emission device includes a substrate.
  • the majority of the filament tips can extend beyond the top metal gate layer planar surface, or below the bottom metal gate layer planar surface.
  • each filament can be electroplated.
  • Each filament is vertically self aligned in its associated aperture.
  • the resulting gated filament structure for a field emission display includes a plurality of filaments. Included is a substrate, an insulating layer positioned adjacent to the substrate, and a metal gate layer including a plurality of gates positioned adjacent to the insulating layer.
  • the metal gate layer has an average thickness "s" and a top metal layer planar surface that is substantially parallel to a bottom metal gate layer planar surface.
  • a plurality of apertures extending through each gate formed in the metal gate layer. Each aperture has an average width "r" along a bottom planar surface of the aperture. Each aperture defines a midpoint plane positioned parallel to and equally distant from the top metal gate layer planar surface and the bottom metal gate layer planar surface.
  • a plurality of gated filaments are individually positioned in an aperture.
  • Each filament has a filament axis. The intersection of the filament axis and the midpoint plane defines a point "O". Each filament includes a filament tip terminating at a point "A". A majority of all filament tips of the display have a length "L” between each filament tip at point A and point O along the filament axis where, L ⁇ (s + r)/2
  • At least 75% of all filament tips of the display have this relationship for points A and O, more preferably at least 90% of the filament tips have this relationship.
  • a large area field emission display is defined as having at least a 6 inch diagonal screen, more preferably at least an 8 inch diagonal screen, yet more preferably at least a 10 inch diagonal screen, and still more preferably at least a 12 inch diagonal screen.
  • the ratio of length to maximum diameter of a filament is at least 2, and normally at least 3.
  • the length-to-maximum-diameter ratio is preferably 5 or more.
  • a gated filament structure 10 is created, as illustrated in Figure 1, from a multi-layer structure which includes a substrate 12, a metal row electrode 14, a resistive layer 16 on top of row electrode 14, an insulating layer 18 on a top surface of resistive layer 16, a metal gate layer 20, and a filament 22 in an insulating pore.
  • Insulating layer 18 is positioned between substrate 12 and metal gate layer 20. It will be appreciated that insulating layer 18 is positioned adjacent to substrate 12 and there can be additional layers between insulating layer 18 and substrate 12 in this adjacent relationship. Thus, adjacent is used herein to mean one layer on top of another layer as well as the possibly of adjacent layers can have intervening layers between them. A portion of insulating layer 18 adjacent to filament 22 has been removed.
  • Filaments are typically cylinders of circular transverse cross section. However, the transverse cross section can be somewhat non-circular.
  • the insulating pore is formed with spacers and reactive ion etching.
  • substrate means, (i) a conductive or semi-conductive substrate with an insulating layer on a top surface of the substrate, (ii) a conductive or semi-conductive substrate with patterned insulating regions or (iii) an insulating substrate.
  • the initial multi-layer structure also includes a tracking resist layer 24 positioned on a top surface of metal gate 20.
  • Suitable materials for the multi-layer structure include the following:
  • Multi-layer structure of Figure 2 can be irradiated with energetic charged particles, such as ions, to produce charged particle tracks in tracking resist layer 24.
  • the other methods include but are not limited to conventional lithography, such as photolithography, x-ray lithography and electron beam lithography.
  • tracking resist layer 24 When charged particles are used, they impinge on tracking resist layer 24 in a direction that is substantially perpendicular to a flat lower surface of substrate 12, and therefore are generally perpendicular to tracking resist layer 24. The charged particles pass through tracking resist layer 24 in a straight path creating a continuous damage zone along the path. Particle tracks are randomly distributed across the multi-layer structure with a well defined average spacing. The track density can be as much as 10 11 tracks/cm 2 . A typical value is 10 8 tracks/cm 2 , which yields an average track spacing of 1 micron.
  • a charged particle accelerator forms a well collimated beam of ions which are used to form tracks.
  • the ion beam is scanned uniformly across tracking resist layer 24.
  • a preferred charged particle species is ionized Xe with an energy typically in the range of about 4 MeV to 16 MeV.
  • charged particle tracks can be created from a collimated source of nuclear fission particles produced, for example, by the radioactive element Californium 252.
  • a chemical etch including but not limited to KOH or NaOH, etches and can over-etch the track formed in tracking resist layer 24 (Figure 3). Instead of forming a cylindrical pore etched along the track, it is widened to open up an aperture 28 in tracking resist layer 24 that is conical with a generally trapezoidal cross-section. Aperture 28 has a diameter of about 50 to 1000 nm, such as by way of example 200 nm, at gate layer 20. Tracking resist layer 24 is used as a mask to etch gate layer 20 to produce, in one embodiment a 200 nm diameter gate hole 28 ( Figure 4). The etching can be reactive ion etching such as Cl 2 for Cr and SF 6 for Mo.
  • the depth of reactive ion etching into insulating layer 18 is minimized.
  • a variety of mechanisms are available to ensure that the reactive ion etching stops at insulating layer 18 including but not limited to, monitoring the process and stopping it at the appropriate time, the use of feedback devices, such as sensors, and use of a selective etch. Excess tracking resist 24 material is stripped away, leaving a gate 30 on the top of insulating layer 18.
  • a conformal layer 32 is applied on top of gates 30 and into apertures 28.
  • Suitable materials for conformal layer 32 include but are not limited to silicon nitride, amorphous or small grained polycrystalline Si, and SiO 2 .
  • Methods for applying conformal layer include but are not limited to CVD.
  • spacer 36 leaves an aperture 38 at the top of insulating layer 18.
  • the size of spacers 36 is controlled to define the size of aperture 38, which can be, in one instance about 100 nm in width.
  • spacers 36 are used as a mask for etching, e.g., a highly anisotropic selective etch in order to etch substantially only insulating layer 18 and form an insulating pore 40.
  • Other structures are minimally etched.
  • polymer is formed on the walls of insulating pores due to the use of CH 4 in the plasma. This forms a polymer on side and bottom walls of insulating pores 40.
  • the polymer protects the walls from chemical attack but does not protect the walls from the energetic particles. Because the energetic particles come straight down and hit only the bottom of insulating pore 40, the polymer is removed only from the bottom of insulating pore 40 and not along the sidewalls.
  • the walls are protected from chemical attack, and etching is only in a direction towards resistive layer 16 because of the anisotropic nature of the reactive ion etching.
  • the control of limiting the etching of resistive layer 16 is accomplished with a variety of mechanisms, including but not limited to, (i) employing a selective etch that etches resistive layer 16 very slowly, (ii) determination of an end point when the etching will be completed by timing and the like, and (iii) monitoring to determine the point when resistive layer 16 begins to be etched.
  • a chemical treatment on insulating pore 40 to remove the polymer.
  • Suitable chemical treatments include but are not limited to, a plasma of CF 4 with O 2 , or commercially available polymer strippers used in the semiconductor industry well known to those skilled in the art. Thereafter, an electrochemical cell is used, such as shown in Figure 7.
  • insulating pore 40 is then filled with a filament material.
  • the plating extends into patterned gate 30.
  • Suitable plating materials include but are not limited to Ni, Pt and the like.
  • Plating can be achieved by pulse plating, with resistance layer 16 as the cathode, and an external anode. The voltage of resistive layer 16 and patterned gate 30 is controlled so that plating does not occur on metal gate layer 20.
  • Spacers 36 are subsequently removed with a removal process, including but not limited to selective plasma etching and wet etching. Thereafter, insulating layer 18 adjacent to filament 22 can be removed with an isotropic plasma or wet chemical (dilute HF) etch. The amount of insulating layer 18 removed is almost down to resistive layer 16.
  • spacers 36 along with reactive ion etching defines insulating pores 40 which are used to create filaments 22.
  • An alternative process is to use tracking of the insulating layer 18 and chemical etching along the particle tracks.
  • filament 22 is created and its tip preferably is between a top planar surface 41 of gate layer 20, and a bottom planar surface 43 of gate layer 20.
  • the filament tip is formed above planer surface 41.
  • filament tip is formed below planar surface 43.
  • the tip of filament 22 can be polished/etched to form a desired tip geometry.
  • Filaments 22 can have a variety of geometries such as flat topped cylinders, rounded top cylinders, sharp cones and the like, which can be created by polishing/etching.
  • FIG. 10 If there are nonuniformities in the thickness of insulating layer 18, or nonuniformities in plating, another embodiment of the invention, illustrated in Figures 10 through 21, may be more suitable for producing filaments 22 with the same position relative to each respective gate 30, as more fully described hereafter.
  • filament 22 is formed above patterned gate 30 by the inclusion of a gate encapsulation layer 42.
  • patterned gate 30 is then used to define the point of filament 22, e.g., the tip geometry of filament 22, which allows for accommodation of non-uniformity in plating and non-uniformity in thickness of the dielectric. This defines the self-alignment of filament 22.
  • Suitable gate encapsulation layer 42 materials include but are not limited to Si, SiO 2 and Si 3 N 4 .
  • the initial multi-layer structure is illustrated in Figure 10 and includes a substrate 12, a metal row electrode 14 positioned on a top surface of substrate 12, a resistive layer 16 on a top surface of metal row electrode 14, an insulating layer 18 on a top surface of resistive layer 16, a metal gate layer 20 positioned on a top surface of insulating layer 18, a gate encapsulation layer 42 positioned on a top surface of metal gate layer 20 and optionally a tracking resist layer 24 positioned on a top surface of gate encapsulation layer 42. It will be appreciated that tracking resist layer 24 need not be included in this embodiment.
  • the appropriate choice of material for gate encapsulation layer 42 may permit gate encapsulation layer 42 to be used also as the tracking resist layer.
  • gate encapsulation layer 42 provides two functions, (i) it encapsulates patterned gate 30 and (ii) allows for the formation of taller spacers 36, permitting plating filament 22 above patterned gate 30.
  • Particle tracking is utilized, as practiced in the first embodiment, and tracking resist layer 24 is etched ( Figure 11). A reactive ion etch through gate encapsulation layer 42 and gate layer 20 is performed ( Figure 12), creating gate hole 28 and patterned gate 30. Tracking resist layer 24 need not be included if gate encapsulation layer 42 can be tracked, etched and used as a resist for patterning gate 30. It will be appreciated that the same methods employed in the embodiment illustrated in Figures 1 through 9 are employed in this second embodiment, illustrated in Figures 10 through 21. The detailed descriptions of the multiplicity of steps utilized will not be repeated here.
  • gate layer 20 is completely insulated; therefore eliminating concerns regarding controlling voltage on patterned gate 30 to ensure that plating will not occur on patterned gate 30.
  • the resulting spacers 36 have a height equal to the height of gate layer 20 plus encapsulation layer 42 ( Figure 14).
  • Insulating pore 40 is formed ( Figure 15) and can have a width in the range of 50 to 1000 nm. A suitable width is about 100 nm. Insulating pore 40 is then filled ( Figure 16).
  • Patterned gate 30 can be used to electro-polish filament 22. Thus, patterned gate 30 is used to define the point where a tip 44 of filament 22 will be ( Figure 20). Patterned gate 30 serves as the cathode for the electro-polishing. A suitable electrolyte is well known to those skilled in the art. This essentially pinches off filament 22 so that excess material becomes free and can be washed away. The remaining filament 22 has a tip 44 geometry that is sharp.
  • Tip 44 of filament 22 is now located at the position of patterned gate 30.
  • Filament 22 and filament tip 44 are positioned in gate aperture 28 to establish a relative position for filament tip 44 with its associated gate aperture 28.
  • the relative position of filament tip 44 to its associated gate aperture 28 is defined as the position of tip 44 relative to a top planar surface 41 of gate layer 20 and a bottom planar surface 43 of gate layer 20.
  • Metal gate layer 20 has an average thickness "s" and a top metal gate planar surface 20(a) that is substantially parallel to a bottom metal gate planar surface 20(b).
  • Metal gate layer 20 includes a plurality of pores 40 extending through metal gate 30. Each pore 40 has an average width "r" along a bottom planar surface of the aperture. Each pore defines a midpoint plane 46 positioned parallel to and equally distant from top metal gate planar surface 20(a) and bottom metal gate planar surface 20(b).
  • a plurality of filaments 22 each have a filament tip 44 which terminates at a point "A" and a filament axis 48 that extends along a length of the filament through filament tip 44. At the intersection of filament axis 48 and midpoint plane 46, a point "O" is defined.
  • a majority of all filament tips 44 of the display have a length "L” between each filament tip 44 at point A and point O along filament axis 48, where, L ⁇ (s+r)/2.
  • At least 75% of all filament tips 44 have this relationship between point A and point O, more particularly, it is at least 90%.
  • the majority of filament tips 44 of the display can have, (i) point A above top metal gate layer planar surface 20(a), (ii) point A between top metal gate layer planar surface 20(a) and bottom metal gate layer planar surface 20(b), or (iii) point A below bottom metal gate layer planar surface 20(b).
  • Patterned gate 30 is used to do the polishing/etching. With the inclusion of gate encapsulation layer 42 filament 22 is plated above patterned gate 30. Additionally, there may be more plating at the edges of the field emission display than in the middle. This can occur because of (i) current crowding effects and (ii) electrolytic depletion effects. As long as the plating is above patterned gate 30 in all places two advantages are achieved, (i) a tolerance on thickness uniformity of deposited insulating layer 18 is provided, and (ii) a high tolerance for the uniformity of plating is possible.
  • the gate can be patterned and used as a mask to completely etch the insulating layer.
  • the conformal layer is then deposited into the created pore. This can lead to complete encapsulation of the gate, making plating easier. Excess material formed on a bottom of the pore is removed with a suitable method including but not limited to plasma or wet etch. The pore is then overplated.
  • Conformal layer is subsequently substantially removed chemically, and the desired filament tip is then electrochemically etched to created the desired geometry.

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  • Manufacturing & Machinery (AREA)
  • Cold Cathode And The Manufacture (AREA)
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Claims (29)

  1. Procédé de création de structures de filaments à grille pour un affichage à émission de champ, comprenant les étapes consécutives ou non consécutives consistant à :
    fournir une structure multicouche comprenant un substrat (12), une couche isolante (18) positionnée sur le substrat (12) et une couche de grille métallique (20) positionnée sur au moins une partie d'une surface supérieure de la couche isolante (18) ;
    fournir une pluralité d'ouvertures (28) dans la couche de grille, chaque ouverture s'étendant à travers la couche de grille à partir de la surface supérieure de la couche de grille,
       caractérisée par :
    la formation d'une pluralité d'espaceurs (36) adjacents aux bords des ouvertures et s'étendant dans les ouvertures ;
    l'utilisation des espaceurs en tant que masques pour attaquer chimiquement la couche isolante (18) de manière à former une pluralité de pores (40) dans la couche isolante ; et
    la métallisation de la pluralité de pores (40) dans la couche isolante de manière à former des filaments (22).
  2. Procédé selon la revendication 1, dans lequel la structure multicouche comprend en outre :
    une couche conductrice (14) sur au moins une partie de la surface supérieure du substrat.
  3. Procédé selon la revendication 1, comprenant en outre :
    l'élimination des espaceurs (36).
  4. Procédé selon la revendication 1, dans lequel la structure multicouche comprend en outre :
    une électrode de ligne métallique (14) positionnée sur une surface supérieure du substrat ; et
    une couche résistive (16) au moins partiellement positionnée sur une surface supérieure de l'électrode de ligne métallique, la couche isolante (18) étant positionnée sur une surface supérieure de la couche résistive.
  5. Procédé selon la revendication 4, dans lequel la structure multicouche comprend en outre :
    une couche de résist de poursuite (24) positionnée sur une surface supérieure de la couche de grille métallique.
  6. Procédé selon la revendication 5, comprenant en outre :
    l'irradiation de la structure multicouche avec des particules d'énergie chargées pour produire une pluralité de pistes dans la couche de résist de poursuite.
  7. Procédé selon la revendication 1, comprenant en outre :
    l'élimination d'une partie de la couche isolante (18) adjacente aux filaments.
  8. Procédé selon la revendication 5, comprenant en outre :
    l'irradiation de la structure multicouche avec des particules d'énergie chargées pour produire une pluralité de pistes dans la couche de résist de poursuite ;
    l'attaque chimique de la pluralité de pistes pour former une pluralité d'ouvertures (26) dans la couche de résist de poursuite ; et
    l'attaque chimique de la couche de grille métallique pour former la pluralité d'ouvertures (28).
  9. Procédé selon la revendication 3, dans lequel la formation de la pluralité d'espaceurs comprend :
    l'application d'une couche conforme dans les ouvertures (28) ; et
    l'élimination de la couche conforme (32) tout en laissant le matériau espaceur dans les ouvertures.
  10. Procédé selon la revendication 5, dans lequel la couche de résist de poursuite (24) se compose de polycarbonate.
  11. Procédé selon la revendication 5, comprenant en outre :
    l'irradiation de la structure multicouche avec du Xe chargé en énergie.
  12. Procédé selon la revendication 6, dans lequel la pluralité de pistes est attaquée chimiquement pour former la pluralité d'ouvertures (26) dans la couche de résist de poursuite avec une taille d'ouverture au niveau de la couche de grille métallique comprise entre environ 0,05 et 2,0 microns.
  13. Procédé selon la revendication 1, dans lequel la couche de grille métallique (20) est attaquée chimiquement par attaque par ions réactifs qui ne s'étend sensiblement pas dans la couche isolante (18).
  14. Procédé selon la revendication 1, dans lequel la couche de grille métallique (20) est attaquée chimiquement par attaque par ions réactifs qui attaque la couche isolante (18) à une vitesse moins rapide qu'une vitesse d'attaque de la couche de grille métallique.
  15. Procédé selon la revendication 9, dans lequel la couche conforme (32) se compose d'un matériau sélectionné parmi le nitrure de silicium, le Si ou le SiO2 amorphe polycristallin à petits grains.
  16. Procédé selon la revendication 1, dans lequel la couche de grille métallique (20) présente une épaisseur comprise entre environ 500 et 2000 A.
  17. Procédé selon la revendication 9, dans lequel l'épaisseur de la couche conforme (32) est d'environ 50 nm.
  18. Procédé selon la revendication 1, dans lequel une attaque par ions réactifs anisotropes est utilisée pour créer la pluralité de pores (40) dans la couche isolante.
  19. Procédé selon la revendication 1, dans lequel le dégagement de la couche isolante (18) est minimisé.
  20. Procédé selon la revendication 4, dans lequel l'attaque chimique de la couche isolante (18) pour former la pluralité de pores isolants ne s'étend sensiblement pas dans la couche résistive (16).
  21. Procédé selon la revendication 4, dans lequel les tensions sur la couché résistive (16) et sur la couche de grille métallique (20) sont contrôlées de manière à minimiser le matériau de filament de métallisation sur la couche de grille métallique.
  22. Procédé selon la revendication 1, comprenant en outre :
    le traitement des filaments (22) pour former une géométrie de bout de filament souhaitée.
  23. Procédé selon la revendication 1, dans lequel la formation des filaments comprend la galvanoplastie.
  24. Procédé selon la revendication 23, dans lequel la structure multicouche comprend une électrode de ligne (14) positionnée en dessous de la couche isolante, et la galvanoplastie comprend l'application d'un potentiel à l'électrode de ligne.
  25. Procédé selon la revendication 1, comprenant en outre :
    le polissage par anodisation d'un filament ou d'une pluralité de filaments.
  26. Procédé selon la revendication 25, dans lequel le polissage par anodisation comprend l'application d'un potentiel à la couche de grille.
  27. Procédé selon la revendication 1, comprenant en outre :
    le pincement du bout de filament pour doter le bout de filament d'une géométrie pointue.
  28. Procédé selon la revendication 1, dans lequel les filaments sont formés dans les pores de telle sorte que les filaments s'étendent dans les ouvertures et que les espaceurs masquent les bords des ouvertures de la formation des filaments.
  29. Dispositif d'affichage à émission de champ comprenant une structure de filaments à grille formée en utilisant un procédé tel que défini dans l'une quelconque des revendications précédentes.
EP96905347A 1995-01-31 1996-01-31 Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ Expired - Lifetime EP0807314B1 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US383408 1982-06-01
US383409 1982-06-01
US383410 1982-06-01
US08/383,408 US5578185A (en) 1993-09-08 1995-01-31 Method for creating gated filament structures for field emision displays
US08/383,409 US7025892B1 (en) 1993-09-08 1995-01-31 Method for creating gated filament structures for field emission displays
US08/383,410 US5801477A (en) 1993-09-08 1995-01-31 Gated filament structures for a field emission display
PCT/US1996/001461 WO1996024152A1 (fr) 1995-01-31 1996-01-31 Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ

Publications (2)

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EP0807314A1 EP0807314A1 (fr) 1997-11-19
EP0807314B1 true EP0807314B1 (fr) 2002-04-24

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EP (1) EP0807314B1 (fr)
JP (1) JP3832840B2 (fr)
AU (1) AU4913496A (fr)
WO (1) WO1996024152A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6031250A (en) * 1995-12-20 2000-02-29 Advanced Technology Materials, Inc. Integrated circuit devices and methods employing amorphous silicon carbide resistor materials
JP3171121B2 (ja) * 1996-08-29 2001-05-28 双葉電子工業株式会社 電界放出型表示装置
FR2766011B1 (fr) * 1997-07-10 1999-09-24 Alsthom Cge Alcatel Cathode froide a micropointes
FR2770683B1 (fr) * 1997-11-03 1999-11-26 Commissariat Energie Atomique Procede de fabrication d'une source d'electrons a micropointes

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3340777A1 (de) * 1983-11-11 1985-05-23 M.A.N. Maschinenfabrik Augsburg-Nürnberg AG, 8000 München Verfahren zur herstellung von duennfilm-feldeffekt-kathoden
DE4209301C1 (en) * 1992-03-21 1993-08-19 Gesellschaft Fuer Schwerionenforschung Mbh, 6100 Darmstadt, De Manufacture of controlled field emitter for flat display screen, TV etc. - using successive etching and deposition stages to form cone shaped emitter peak set in insulating matrix together with electrodes
US5320570A (en) * 1993-01-22 1994-06-14 Motorola, Inc. Method for realizing high frequency/speed field emission devices and apparatus
FR2705830B1 (fr) * 1993-05-27 1995-06-30 Commissariat Energie Atomique Procédé de fabrication de dispositifs d'affichage à micropointes, utilisant la lithographie par ions lourds.

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WO1996024152A1 (fr) 1996-08-08
JPH10513304A (ja) 1998-12-15
EP0807314A1 (fr) 1997-11-19
AU4913496A (en) 1996-08-21
JP3832840B2 (ja) 2006-10-11

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