EP0807314A1 - Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ - Google Patents

Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ

Info

Publication number
EP0807314A1
EP0807314A1 EP96905347A EP96905347A EP0807314A1 EP 0807314 A1 EP0807314 A1 EP 0807314A1 EP 96905347 A EP96905347 A EP 96905347A EP 96905347 A EP96905347 A EP 96905347A EP 0807314 A1 EP0807314 A1 EP 0807314A1
Authority
EP
European Patent Office
Prior art keywords
layer
filament
metal gate
insulating layer
field emission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96905347A
Other languages
German (de)
English (en)
Other versions
EP0807314B1 (fr
Inventor
David L. Bergeron
John M. Macaulay
Roger W. Barton
Jeffrey D. Morse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Candescent Technologies Inc
Original Assignee
Candescent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/383,408 external-priority patent/US5578185A/en
Priority claimed from US08/383,409 external-priority patent/US7025892B1/en
Application filed by Candescent Technologies Inc filed Critical Candescent Technologies Inc
Publication of EP0807314A1 publication Critical patent/EP0807314A1/fr
Application granted granted Critical
Publication of EP0807314B1 publication Critical patent/EP0807314B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/304—Field emission cathodes
    • H01J2201/30446—Field emission cathodes characterised by the emitter material
    • H01J2201/30453—Carbon types
    • H01J2201/30457—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/319—Circuit elements associated with the emitters by direct integration

Definitions

  • This invention relates to gated filament structures for a field emission display with filaments positioned in apertures.
  • the relative position of the majority of each filament tip to its associated aperture is substantially the same for a majority of the filament tips of the display. This relationship is maintained even for large displays where there are nonuniformities in the thickness of the insulating layer or in the plating of the filaments.
  • Field emission displays include a faceplate, a backplate and connecting walls around the periphery of the faceplate and backplate, forming a sealed vacuum envelope.
  • the envelope is held at vacuum pressure, which can be about 1 x 10 "7 torr or less.
  • the interior surface of the faceplate is coated with light emissive elements, such as phosphor or phosphor patterns, which define an active region of the display.
  • Field emission cathodes such as cones and filaments, are located adjacent to the backplate.
  • Application of an appropriate voltage at the extraction electrode releases electrons which are accelerated toward the phosphors on the faceplate. The accelerated electrons strike their targeted phosphors, causing the phosphors to emit light seen by the viewer at the exterior of the faceplate. Emitted electrons for each of the sets of emitters are intended to strike only certain targeted phosphors.
  • U.S. Patent No. 3,655,241 discloses fabricating field emitters using a screen with arrays of circular or square openings that is placed above a substrate electrode. A deposition is performed simultaneously from two sources. One of the sources consists of an emitter-forming metal, such as molybdenum, and atoms are deposited in a direction perpendicular to the substrate electrode. The other source consists of a closure material, such as a molybdenum-alumina composite. Atoms of the closure material are caused to impinge on the screen at a small angle to the substrate. The closure material progressively closes the openings in the screen. Thus the emitter- forming metal is deposited in the shape of cones or pyramids, depending on whether the screen openings are circular or square. Another method of creating field emitters is disclosed in U.S. Patent No.
  • Part of an aluminum plate is anodically oxidized to create a thin alumina layer having pores that extend nearly all the way through the alumina.
  • An electrolytic technique is used to fill the pores with gold for the field emitters.
  • An address line is formed over the filled pores along the alumina side of the structure, after which the remaining aluminum and part of the adjoining alumina are removed along the opposite side of the structure to re-expose the gold in the pores.
  • Part of the re-exposed gold is removed during an ion-milling process utilized to sharpen the field emitters.
  • Gold is then evaporatively deposited onto the alumina and partly into the pores to form the gate electrode.
  • Field emitters are fabricated in U.S. Patent No. 5J50J92 by creating openings partway through a substrate by etching through a mask formed on the bottom of the substrate. Metal is deposited along the walls of the openings and along the lower substrate surface. A portion of the thickness of the substrate is removed along the upper surface. A gate electrode is then formed by a deposition/planarization procedure. Cavities are provided along the upper substrate surface after which the hollow metal portions in the openings are sharpened to complete the field emitter structures.
  • large area field emission displays require a relatively strong substrate for supporting the field emitters extending across the large emitter area.
  • the requisite substrate thickness is typically several hundred microns to 10 mm or more.
  • a gated area field emitter consists of cones formed on a highly resistive layer that overlies a highly conductive layer situated on an electrically insulating supporting structure.
  • the highly resistive layer has a resistivity of 10 4 to 10 5 ohm-cm. The resistive layer limits the currents through the electron-emissive cones so as to protect the field emitter from breakdown and short circuits.
  • a field emission cathode relies on there being a very strong electric field at the surface of a filament or generally on the surface of the cathode. Creation of the strong field is dependent on, (i) the sharpness of the cathode tip and (ii) the proximity of the extraction electrode (gate) and the cathode. Application of the voltage between these two electrodes produces the strong electric field. Emission nonuniformity is related to the nonuniformity in the relative positions of the emitter tip and the gate. Emission nonuniformity can also result from differences in the sharpness of the emitting tips. Busta, "Vacuum Microelectronics- 1992," J. Micromech. Microeng.. Vol.
  • Busta discusses Utsumi, "Keynote Address, Vacuum Microelectronics: What's New and Exciting," IEEE Trans. Elect. Dev.. Oct. 1990, pp. 2276 - 2283, who suggests that a filament with a rounded end is the best shape for a field emitter. Also of interest is Fischer et al., "Production and Use of Nuclear Tracks: Imprinting Structure on Solids,” Rev. Mod. Phvs.. Oct. 1983, pp. 907 -948, which deals with the use of charged-particle tracks in manufacturing field emitters according to a replica technique.
  • a well collimated source of evaporant as taught in U.S. Patent No. 3,655,241 , is necessary in order to obtain uniformity of cone or filament formation across the entire field emission display.
  • the majority of evaporant is deposited on interior surfaces of the evaporation equipment.
  • the combination of the expensive of the evaporation equipment, and the wastage of evaporant, is undesirable for commercial manufacturing and is compounded as the size of the display increases. With large displays, there are nonuniformities in the thickness of the insulating layer and the plating of the filaments.
  • a further object of the invention is to provide gated filament structures that are electroplated.
  • Another object of the invention is to provide a commercial manufacturing process for forming filaments in a large field emission display. Yet another object of the invention is to provide a commercial manufacturing process for forming filaments in a large field emission display using electroplating. Still a further object of the invention is to provide a method for forming filaments in a field emission display which uses spacers as an etch mask and as part of the mold for plating the filament structures.
  • a gated filament structure for a field emission display includes a plurality of filaments. Included is a substrate, an insulating layer positioned adjacent to the substrate, and a metal gate layer including a plurality of gates positioned adjacent to the insulating layer.
  • the metal gate layer has an average thickness "s" and a top metal gate layer planar surface that is substantially parallel to a bottom metal gate layer planar surface.
  • a plurality of apertures extending through each gate formed in the metal gate layer. Each aperture has an average width "r" along a bottom planar surface of the aperture.
  • Each aperture defines a midpoint plane positioned parallel to and equally distant from the top metal gate layer planar surface and the bottom metal gate layer planar surface.
  • a plurality of gated filaments are individually positioned in an aperture. Each filament has a filament axis. The intersection of the filament axis and the midpoint plane defines a point "O".
  • Each filament includes a filament tip terminating at a point "A”.
  • a majority of all filapement tips of the display have a length "L" between each filament tip at point A and point O along the filament axis where, L -. (s + r)/2. It is prefe-red that at least 75% of all filament tips of the display have this relationship for points A and O, more preferably at least 90% of the filament tips have this relationship.
  • a multi-layer structure in one method for creating gated filament structures in a field emission display, includes a substrate, an insulating layer and a metal gate layer positioned on at least a portion of a top surface of the insulating layer.
  • an insulating substrate is, (i) a conductive or semi- conductive substrate with an insulating layer on a top surface of the substrate, (ii) a conductive or semi-conductive substrate with patterned insulating regions on a top surface of the substrate or (iii) an insulating substrate.
  • a plurality of patterned gates are provided and define a plurality of gate apertures on the top surface of the insulating layer. The patterned gates can be part of the initial multi-layer structure, or formed thereafter.
  • a plurality of spacers are formed in the gate apertures at edges of the patterned gates on the top surface of the insulating layer.
  • the spacers are used as masks for etching the insulating layer and forming a plurality of pores in the insulating layer.
  • the pores are plated with a filament material that extends from the pores, into the gate apertures, and creates a plurality of filaments.
  • the spacers are then removed.
  • the multi-layer structure can include a conductivity layer on at least a portion of a top surface of the substrate.
  • a multi-layer structure in another method for creating gated filament structures in a field emission display, includes a substrate, an insulating layer, a metal gate layer positioned on a top surface of the insulating layer and a gate encapsulation layer positioned on a top surface of the metal gate layer.
  • a plurality of patterned gate are provided and define a plurality of gate apertures on the top of the insulating layer.
  • a plurality of spacers are formed in the gate apertures at edges of the patterned gates on the top surface of the insulating layer. Spacers are used as masks for etching the insulating layer and forming a plurality of pores in the insulating layer.
  • the pores are plated with a filament material to create a plurality of filaments.
  • the majority of filament tips can, (i) extend between the top and bottom metal gate layer surfaces, (ii) extend below the bottom metal gate layer surface, or (iii) extend above the top metal gate layer surface.
  • Each filament of the display can be electroplated.
  • the gated filament structure for a field emission device includes a substrate.
  • the majority of the filament tips can extend beyond the top metal gate layer planar surface, or below the bottom metal gate layer planar surface.
  • each filament can be electroplated.
  • Each filament is vertically self aligned in its associated aperture. DESCRIPTION OF THE DRAWINGS
  • Figure 1 is a cross-sectional view of a multi layer structure with a gated filament in an insulating pore.
  • Figure 2 is a cross-sectional view of an initial multi-layer structure used to create the gated filaments.
  • Figure 3 is a cross-sectional view of the structure of Figure 2, after the tracking resist layer has been etched to open up an aperture at the gate.
  • Figure 4 is a cross-sectional view of the structure of Figure 3 following reactive ion etching of the metal gate layer , and the creation of gates and apertures.
  • Figure 5(a) is a cross-sectional view of the structure of Figure 4 with a conformal layer applied over the gates and into the apertures.
  • Figure 5(b) is a cross-sectional view of the structure of Figure 5(a) when conforming layer 32 is anisotropicaly etched and material is removed. The anisotropic etching step removes the material, thus forming a spacer at a step.
  • Figure 6 is a cross-sectional view of the structure of Figure 5 following anisotropic etching of the conformal layer, leaving spacers in the apertures at their edges on the top surface of the insulating layer.
  • Figure 7 is a cross-sectional view of the structure of Figure 6 illustrating the use of the spacers as masks for reactive ion etching the insulating layer through the spacing over the insulating layer, to the resistive layer, and the formation of an insulating layer pore.
  • the schematic of an electrochemical cell is also shown with an anode positioned over the gates, and the cathode connected to the metal row electrode and its associated resistive layer.
  • the schematic also includes a voltage supply.
  • Figure 8 is a cross-sectional view of the structure of Figure 7 after the insulating layer pore has been filled with a filament material that extends through the insulating layer pore to a height generally not greater than the height of the spacers, creating the filament.
  • Figure 9 is a cross-sectional view of a gated filament structure with a sharpened tip that can extend into the gate.
  • Figure 10 is a second embodiment of the invention illustrating an initial multi ⁇ layer structure that includes a gate encapsulation layer positioned on a top surface of the metal gate layer and a tracking resist layer positioned on a top surface of the gate encapsulation layer.
  • Figure 11 is a cross-section view of the structure of Figure 10 after the tracking resist layer has been etched to open up an aperture at the gate encapsulation layer.
  • Figure 12 is a cross-sectional view of the structure of Figure 1 1 following reactive ion etching of the gate encapsulation layer and the metal gate layer, to create gates and apertures.
  • Figure 13 is a cross-sectional view of the structure of Figure 12 with a conformal layer applied on top of the gate and into the aperture.
  • Figure 14 is a cross-sectional view of Figure 13 following anisotropic etching of the conforming member, leaving spacer material in the apertures at their edges on the top surface of the insulating layer to form a plurality of spacers.
  • Figure 15 is a cross-sectional view of the structure of Figure 14 using the spacers as masks for etching the insulating layer through the spacing over the insulating layer to the resistive layer, and form an insulating layer pore.
  • the schematic of an electrochemical cell is also shown with an anode positioned over the gates, and the cathode connected to the metal row electrode and its associated resistive layer.
  • the schematic also includes a voltage supply.
  • Figure 16 is a cross-sectional view of the structure of Figure 15 after the insulating layer pore has been filled with a filament material which extends through the insulating layer pore to a height above the gate.
  • Figure 17 is a cross-sectional view of a structure, similar to that of Figure 16 except the thickness of the insulating layer is non-uniform. The relationship between the filament tip and the gate is still maintained even with the nonuniformity.
  • Figure 18 is a cross-sectional view of the structure of Figure 16. The relationship between the filament tip and the gate is still maintained even with nonuniformity of plating of the filaments.
  • Figure 19 is a cross-sectional view of a gated filament following removal of the gate encapsulation layer and the spacers. Also illustrated is a schematic of an electrochemical cell with the gate as the cathode, and the overgrown filament as the anode.
  • Figure 20 is a cross-sectional view of the structure of Figure 19 illustrating the creation of a gated sharpened filament.
  • Figure 21 is a cross-sectional view of the filament positioned in its aperture.
  • a large area field emission display is defined as having at least a 6 inch diagonal screen, more preferably at least an 8 inch diagonal screen, yet more preferably at least a 10 inch diagonal screen, and still more preferably at least a 12 inch diagonal screen.
  • the ratio of length to maximum diameter of a filament is at least 2, and normally at least 3.
  • the length-to-maximum-diameter ratio is preferably 5 or more.
  • a gated filament structure 10 is created, as illustrated in Figure 1. from a multi ⁇ layer structure which includes a substrate 12, a metal row electrode 14, a resistive layer 16 on top of row electrode 14, an insulating layer 18 on a top surface of resistive layer 16, a metal gate layer 20, and a filament 22 in an insulating pore.
  • Insulating layer 18 is positioned between substrate 12 and metal gate layer 20. It will be appreciated that insulating layer 18 is positioned adjacent to substrate 12 and there can be additional layers between insulating layer 18 and substrate 12 in this adjacent relationship. Thus, adjacent is used herein to mean one layer on top of another layer as well as the possibly of adjacent layers can have intervening layers between them. A portion of insulating layer 18 adjacent to filament 22 has been removed. Filaments are typically cylinders of circular transverse cross section. However, the transverse cross section can be somewhat non-circular. The insulating pore is formed with spacers and reactive ion etching.
  • substrate means, (i) a conductive or semi- conductive substrate with an insulating layer on a top surface of the substrate, (ii) a conductive or semi-conductive substrate with patterned insulating regions or (iii) an insulating substrate.
  • the initial multi-layer structure also includes a tracking resist layer 24 positioned on a top surface of metal gate 20.
  • Suitable materials for the multi-layer structure include the following: substrate 12 - glass or ceramic metal row electrode 14 - Ni resistive layer 16 - cermet, CrO x or SiC insulating layer 18 - SiO 2 metal gate layer 20 - Cr and/or Mo tracking resist layer 24 - polycarbonate filament 22 - Ni or Pt Multi-layer structure of Figure 1 can be irradiated with energetic charged particles, such as ions, to produce charged particle tracks in tracking resist layer 24.
  • the other methods include but are not limited to conventional lithography, such as photolithography, x-ray lithography and electron beam lithography.
  • tracking resist layer 24 When charged particles are used, they impinge on tracking resist layer 24 in a direction that is substantially pe ⁇ endicular to a flat lower surface of substrate 12, and therefore are generally pe ⁇ endicular to tracking resist layer 24. The charged particles pass through tracking resist layer 24 in a straight path creating a continuous damage zone along the path. Particle tracks are randomly distributed across the multi-layer structure with a well defined average spacing. The track density can be as much as 10" tracks/cm 2 . A typical value is 10 8 tracks/cm 2 , which yields an average track spacing of 1 micron.
  • a charged particle accelerator forms a well collimated beam of ions which are used to form tracks.
  • the ion beam is scanned uniformly across tracking resist layer 24.
  • a preferred charged particle species is ionized Xe with an energy typically in the range of about 4 MeV to 16 MeV.
  • charged particle tracks can be created from a collimated source of nuclear fission particles produced, for example, by the radioactive element Californium 252.
  • a chemical etch including but not limited to KOH or NaOH, etches and can over-etch the track formed in tracking resist layer 24 (Figure 3). Instead of forming a cylindrical pore etched along the track, it is widened to open up an aperture 26 in tracking resist layer 24 that is conical with a generally trapezoidal cross-section. Aperture 26 has a diameter of about 50 to 1000 nm, such as by way of example 200 nm, at gate layer 20. Tracking resist layer 24 is used as a mask to etch gate layer 20 to produce, in one embodiment a 200 nm diameter gate hole 28 ( Figure 4). The etching can be reactive ion etching such as Cl, for Cr and SF 6 for Mo.
  • the depth of reactive ion etching into insulating layer 18 is minimized.
  • a variety of mechanisms are available to ensure that the reactive ion etching stops at insulating layer 18 including but not limited to, monitoring the process and stopping it at the appropriate time, the use of feedback devices, such as sensors, and use of a selective etch. Excess tracking resist 24 material is stripped away, leaving a gate 30 on the top of insulating layer 18. Referring now to Figure 5(a), a conformal layer 32 is applied on top of gates
  • Suitable materials for conformal layer 32 include but are not limited to silicon nitride, amo ⁇ hous or small grained polycrystalline Si, and SiO : .
  • Methods for applying conformal layer include but are not limited to CVD.
  • spacer 36 leaves an aperture 38 at the top of insulating layer 18.
  • the size of spacers 36 is controlled to define the size of aperture 38, which can be, in one instance about 100 nm in width.
  • spacers 36 are used as a mask for etching, e.g., a highly anisotropic selective etch in order to etch substantially only insulating layer 18 and form an insulating pore 40.
  • Other structures are minimally etched.
  • polymer is formed on the walls of insulating pores due to the use of CH 4 in the plasma. This forms a polymer on side and bottom walls of insulating pores 40.
  • the polymer protects the walls from chemical attack but does not protect the walls from the energetic particles. Because the energetic particles come straight down and hit only the bottom of insulating pore 40, the polymer is removed only from the bottom of insulating pore 40 and not along the sidewalls.
  • the walls are protected from chemical attack, and etching is only in a direction towards resistive layer 16 because of the anisotropic nature of the reactive ion etching.
  • the control of limiting the etching of resistive layer 16 is accomplished with a variety of mechanisms, including but not limited to, (i) employing a selective etch that etches resistive layer 16 very slowly, (ii) determination of an end point when the etching will be completed by timing and the like, and (iii) monitoring to determine the point when resistive layer 16 begins to be etched.
  • a chemical treatment include but are not limited to, a plasma of CF 4 with O : , or commercially available polymer strippers used in the semiconductor industry well known to those skilled in the art. Thereafter, an electrochemical cell is used, such as shown in Figure 7.
  • insulating pore 40 is then filled with a filament material.
  • the plating extends into patterned gate 30.
  • Suitable plating materials include but are not limited to Ni, Pt and the like.
  • Plating can be achieved by pulse plating, with resistance layer 16 as the cathode, and an external anode. The voltage of resistive layer 16 and patterned gate 30 is controlled so that plating does not occur on metal gate layer 20.
  • Spacers 36 are subsequently removed with a removal process, including but not limited to selective plasma etching and wet etching. Thereafter, insulating layer 16 adjacent to filament 22 can be removed with an isotropic plasma or wet chemical (dilute HF) etch. The amount of insulating layer 18 removed is almost down to resistive layer 16.
  • insulating layer 18 is not removed ( Figure 9).
  • the use of spacers 36 along with reactive ion etching defines insulating pores 40 which are used to create filaments 22.
  • An alternative process is to use tracking of the insulating layer 18 and chemical etching along the particle tracks.
  • filament 22 is created and its tip preferably is between a top planar surface 41 of gate layer 20, and a bottom planar surface 43 of gate layer 20.
  • the filament tip is formed above planer surface 41. Less preferably, filament tip is formed below planar surface 43.
  • the tip of filament 22 can be polished/etched to form a desired tip geometry.
  • Filaments 22 can have a variety of geometries such as flat topped cylinders, rounded top cylinders, sha ⁇ cones and the like, which can be created by polishing/etching.
  • FIG. 10 If there are nonuniformities in the thickness of insulating layer 18, or nonuniformities in plating, another embodiment of the invention, illustrated in Figures 10 through 21, may be more suitable for producing filaments 22 with the same position relative to each respective gate 30, as more fully described hereafter.
  • filament 22 is formed above patterned gate 30 by the inclusion of a gate encapsulation layer 42.
  • patterned gate 30 is then used to define the point of filament 22, e.g., the tip geometry of filament 22, which allows for accommodation of non-uniformity in plating and non-uniformity in thickness of the dielectric. This defines the self-alignment of filament 22.
  • Suitable gate encapsulation layer 42 materials include but are not limited to Si, SiO 2 and Si 3 N 4 .
  • the initial multi-layer structure is illustrated in Figure 10 and includes a substrate 12. a metal row electrode 14 positioned on a top surface of substrate 12, a resistive layer 16 on a top surface of metal row electrode 14, an insulating layer 18 on a top surface of resistive layer 16, a metal gate layer 20 positioned on a top surface of insulating layer 18, a gate encapsulation layer 42 positioned on a top surface of metal gate layer 20 and optionally a tracking resist layer 24 positioned on a top surface of gate encapsulation layer 42. It will be appreciated that tracking resist layer 24 need not be included in this embodiment. The appropriate choice of material for gate encapsulation layer 42 may permit gate encapsulation layer 42 to be used also as the tracking resist layer.
  • Gate encapsulation layer 42 provides two functions, (i) it encapsulates patterned gate 30 and (ii) allows for the formation of taller spacers 36, permitting plating filament 22 above patterned gate 30. Particle tracking is utilized, as practiced in the first embodiment, and tracking resist layer 24 is etched ( Figure 1 1 ). A reactive ion etch through gate encapsulation layer 42 and gate layer 20 is performed ( Figure 12), creating gate hole 28 and patterned gate 30. Tracking resist layer 24 need not be included if gate encapsulation layer 42 can be tracked, etched and used as a resist for patterning gate 30. It will be appreciated that the same methods employed in the embodiment illustrated in Figures 1 through 9 are employed in this second embodiment, illustrated in Figures 10 through 21. The detailed descriptions of the multiplicity of steps utilized will not be repeated here.
  • gate layer 20 is completely insulated; therefore eliminating concerns regarding controlling voltage on patterned gate 30 to ensure that plating will not occur on patterned gate 30.
  • anisotropic etching of spacer conformal layer 32 the resulting spacers
  • Insulating pore 40 is formed ( Figure 15) and can have a width in the range of 50 to 1000 nm. A suitable width is about 100 nm. Insulating pore 40 is then filled ( Figure 16).
  • Patterned gate 30 can be used to electro-polish filament 22 with the circuitry illustrated in Figure 19. Thus, patterned gate 30 is used to define the point where a tip 44 of filament 22 will be ( Figure 20). Patterned gate 30 serves as the cathode for the electro-polishing. A suitable electrolyte is well known to those skilled in the art. This essentially pinches off filament 22 so that excess material becomes free and can be washed away. The remaining filament 22 has a tip 44 geometry that is sha ⁇ .
  • Tip 44 of filament 22 is now located at the position of patterned gate 30.
  • Filament 22 and filament tip 44 are positioned in gate aperture 28 to establish a relative position for filament tip 44 with its associated gate aperture 28.
  • the relative position of filament tip 44 to its associated gate aperture 28 is defined as the position of tip 44 relative to a top planar surface 41 of gate layer
  • gate layer 20 and a bottom planar surface 43 of gate layer 20.
  • Metal gate layer 20 has an average thickness "s" and a top metal gate planar surface 20(a) that is substantially parallel to a bottom metal gate planar surface 20(b).
  • Metal gate layer 20 includes a plurality of pores 40 extending through metal gate 30. Each pore 40 has an average width "r" along a bottom planar surface of the aperture.
  • Each pore defines a midpoint plane 46 positioned parallel to and equally distant from top metal gate planar surface 20(a) and bottom metal gate planar surface 20(b).
  • a plurality of filaments 22 each have a filament tip 44 which terminates at a point "A” and a filament axis 48 that extends along a length of the filament through filament tip 44. At the intersection of filament axis 48 and midpoint plane 46, a point "O" is defined.
  • a majority of all filament tips 44 of the display have a length "L” between each filament tip 44 at point A and point O along filament axis 48, where,
  • filament tips 44 Preferably, at least 75% of all filament tips 44 have this relationship between point A and point O, more particularly, it is at least 90%.
  • the majority of filament tips 44 of the display can have, (i) point A above top metal gate layer planar surface 20(a), (ii) point A between top metal gate layer planar surface 20(a) and bottom metal gate layer planar surface 20(b). or (iii) point A below bottom metal gate layer planar surface 20(b).
  • every insulating pore 40 is ove ⁇ lated and vertical self-alignment is utilized.
  • Patterned gate 30 is used to do the polishing/etching. With the inclusion of gate encapsulation layer 42 filament 22 is plated above patterned gate 30.
  • plating at the edges of the field emission display there may be more plating at the edges of the field emission display than in the middle. This can occur because of (i) current crowding effects and (ii) electrolytic depletion effects. As long as the plating is above patterned gate 30 in all places two advantages are achieved, (i) a tolerance on thickness uniformity of deposited insulating layer 18 is provided, and (ii) a high tolerance for the uniformity of plating is possible.
  • Polished filament tips 44 can be created. Further, cones can be formed, as well as filaments using electroless deposition and selective deposition processes well known to those skilled in the art.
  • the gate can be patterned and used as a mask to completely etch the insulating layer.
  • the conformal layer is then deposited into the created pore. This can lead to complete encapsulation of the gate, making plating easier. Excess material formed on a bottom of the pore is removed with a suitable method including but not limited to plasma or wet etch. The pore is then ove ⁇ lated.
  • Conformal layer is subsequently substantially removed chemically, and the desired filament tip is then electrochemically etched to created the desired geometry.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)

Abstract

Structure à filaments comportant des grilles pour dispositif d'affichage par émission de champ comprenant une pluralité de filaments. Ces structures comportent un substrat, une couche isolante adjacente au substrat et une couche de grilles métalliques adjacente à la couche isolante. La couche de grilles métalliques comporte une pluralité de grilles, ladite couche ayant une épaisseur moyenne 's' et une surface plane supérieure sensiblement parallèle à une surface plane inférieure. La couche de grilles métalliques comporte une pluralité d'ouvertures qui s'étendent à travers les grilles. Chaque ouverture a une largeur moyenne 'r' le long d'une surface plane inférieure de l'ouverture. Chaque ouverture définit un plan médian situé à égale distance de la surface plane supérieure de la couche de grilles métalliques et de la surface plane inférieure de ladite couche et parallèle à ces deux surfaces. Une pluralité de filaments sont placés individuellement dans une ouverture. Chaque filament comporte un axe. L'intersection de cet axe et du plan médian définit un point 'O'. Chaque filament comporte une pointe terminée par un point 'A'. La majeure partie des pointes de filaments de l'afficheur présentent une longueur 'L' comprise entre le point A de la pointe du filament et le point O situé le long de l'axe du filament, L étant inférieur ou égal à (s+r)/2.
EP96905347A 1995-01-31 1996-01-31 Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ Expired - Lifetime EP0807314B1 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US383408 1982-06-01
US383409 1982-06-01
US08/383,408 US5578185A (en) 1993-09-08 1995-01-31 Method for creating gated filament structures for field emision displays
US08/383,410 US5801477A (en) 1993-09-08 1995-01-31 Gated filament structures for a field emission display
US383410 1995-01-31
US08/383,409 US7025892B1 (en) 1993-09-08 1995-01-31 Method for creating gated filament structures for field emission displays
PCT/US1996/001461 WO1996024152A1 (fr) 1995-01-31 1996-01-31 Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ

Publications (2)

Publication Number Publication Date
EP0807314A1 true EP0807314A1 (fr) 1997-11-19
EP0807314B1 EP0807314B1 (fr) 2002-04-24

Family

ID=27409622

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96905347A Expired - Lifetime EP0807314B1 (fr) 1995-01-31 1996-01-31 Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ

Country Status (4)

Country Link
EP (1) EP0807314B1 (fr)
JP (1) JP3832840B2 (fr)
AU (1) AU4913496A (fr)
WO (1) WO1996024152A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6031250A (en) * 1995-12-20 2000-02-29 Advanced Technology Materials, Inc. Integrated circuit devices and methods employing amorphous silicon carbide resistor materials
JP3171121B2 (ja) * 1996-08-29 2001-05-28 双葉電子工業株式会社 電界放出型表示装置
FR2766011B1 (fr) * 1997-07-10 1999-09-24 Alsthom Cge Alcatel Cathode froide a micropointes
FR2770683B1 (fr) * 1997-11-03 1999-11-26 Commissariat Energie Atomique Procede de fabrication d'une source d'electrons a micropointes

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3340777A1 (de) * 1983-11-11 1985-05-23 M.A.N. Maschinenfabrik Augsburg-Nürnberg AG, 8000 München Verfahren zur herstellung von duennfilm-feldeffekt-kathoden
DE4209301C1 (en) * 1992-03-21 1993-08-19 Gesellschaft Fuer Schwerionenforschung Mbh, 6100 Darmstadt, De Manufacture of controlled field emitter for flat display screen, TV etc. - using successive etching and deposition stages to form cone shaped emitter peak set in insulating matrix together with electrodes
US5320570A (en) * 1993-01-22 1994-06-14 Motorola, Inc. Method for realizing high frequency/speed field emission devices and apparatus
FR2705830B1 (fr) * 1993-05-27 1995-06-30 Commissariat Energie Atomique Procédé de fabrication de dispositifs d'affichage à micropointes, utilisant la lithographie par ions lourds.

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9624152A1 *

Also Published As

Publication number Publication date
JP3832840B2 (ja) 2006-10-11
JPH10513304A (ja) 1998-12-15
AU4913496A (en) 1996-08-21
WO1996024152A1 (fr) 1996-08-08
EP0807314B1 (fr) 2002-04-24

Similar Documents

Publication Publication Date Title
US5801477A (en) Gated filament structures for a field emission display
US5562516A (en) Field-emitter fabrication using charged-particle tracks
US6204596B1 (en) Filamentary electron-emission device having self-aligned gate or/and lower conductive/resistive region
US6339281B2 (en) Method for fabricating triode-structure carbon nanotube field emitter array
KR100638668B1 (ko) 전계방출 에미터 어레이 및 그 제조 방법
KR20010011136A (ko) 나노구조를 에미터로 사용한 삼극형 전계 방출 에미터의 구조및 그 제조방법
US5665421A (en) Method for creating gated filament structures for field emission displays
EP0807314B1 (fr) Structures a filaments comportant des grilles pour dispositif d'affichage par emission de champ
US5556530A (en) Flat panel display having improved electrode array
US7025892B1 (en) Method for creating gated filament structures for field emission displays
US5607335A (en) Fabrication of electron-emitting structures using charged-particle tracks and removal of emitter material
KR100349457B1 (ko) 전계방출디스플레이용게이트필라멘트구조
US20070200478A1 (en) Field Emission Device
US7404980B2 (en) Method for producing an addressable field-emission cathode and an associated display structure
KR100266224B1 (ko) 전계방출 소자 및 그 제조방법과 그를 이용한전계방출 디스플레이 장치
KR100866832B1 (ko) 전계방출소자 제조방법
KR100286454B1 (ko) 전계방출 이미터 및 그 제조방법
KR20000021034A (ko) 전기 영동법에 의한 필드 에미터의 제조방법

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19970724

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): FR GB

17Q First examination report despatched

Effective date: 19980119

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20030127

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

REG Reference to a national code

Ref country code: FR

Ref legal event code: TP

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20130204

Year of fee payment: 18

Ref country code: GB

Payment date: 20130130

Year of fee payment: 18

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20140131

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20140930

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140131

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140131