EP0806719A2 - Circuit pour générer une tension de référence - Google Patents

Circuit pour générer une tension de référence Download PDF

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Publication number
EP0806719A2
EP0806719A2 EP97106833A EP97106833A EP0806719A2 EP 0806719 A2 EP0806719 A2 EP 0806719A2 EP 97106833 A EP97106833 A EP 97106833A EP 97106833 A EP97106833 A EP 97106833A EP 0806719 A2 EP0806719 A2 EP 0806719A2
Authority
EP
European Patent Office
Prior art keywords
transistor
collector
base
resistor
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97106833A
Other languages
German (de)
English (en)
Other versions
EP0806719A3 (fr
EP0806719B1 (fr
Inventor
Stephan Dr. Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0806719A2 publication Critical patent/EP0806719A2/fr
Publication of EP0806719A3 publication Critical patent/EP0806719A3/fr
Application granted granted Critical
Publication of EP0806719B1 publication Critical patent/EP0806719B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to a circuit arrangement for generating a reference potential with a first transistor, whose emitter is connected to a reference potential and whose base and collector are connected to one another, with a second transistor, the base of which is connected to the base of the first transistor, with a first resistor , which is connected between the collector of the first transistor and an output terminal for tapping the reference potential, with a second resistor, which is connected between the collector of the second transistor and the output terminal, with a third resistor, which is connected between the emitter of the second transistor and the Reference potential is connected to a third transistor, the base of which is connected to the collector of the second transistor and the emitter of which is connected to the reference potential, and a controlled current source which is connected between a supply potential and the output terminal and which e is coupled on the input side to the collector of the third transistor.
  • bandgap reference Such a circuit arrangement, also referred to as bandgap reference, is for example from Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, John Wiley and Sons, 1984, pp. 293-296 and EP 0 411 657 A1 and is often used as an internal reference voltage source in integrated circuits.
  • a frequency-compensated bandgap reference is also described in GB 2 256 949 A.
  • Switching off should take place as quickly as possible in order to effectively reduce the current consumption and thus the power loss.
  • the switch-on time should also be kept as short as possible in order to bring the circuit into working condition within a very short time.
  • Another important criterion of circuit arrangements for generating a reference potential is the noise behavior. This can be favorably influenced by band-limiting capacitors, which filter the noise at high frequencies. However, these measures increase the on and off times of the respective circuit.
  • the object of the invention is to provide a circuit arrangement of the type mentioned at the outset which, despite good noise behavior, has short switch-on and switch-off times.
  • a capacitance is connected in parallel with the second resistor.
  • the fourth transistor operated as an emitter follower can deliver more current and thereby shortens the switch-on time.
  • the second resistor lying parallel to the capacitance helps to shorten the switch-off time. Stability and noise behavior remain practically unchanged. Finally, the operating voltage suppression at high frequencies is improved.
  • the controlled current source has a fourth transistor, the collector of which is connected to the supply potential, the emitter of which is connected to the output terminal and the base of which is connected to the collector of the third transistor. Another current source is connected between the base and collector of the fourth transistor.
  • the further current source can have a fifth transistor, the base of which is connected to the output terminal and the emitter of which is connected to the reference potential with the interposition of a fourth resistor. Furthermore, there is a sixth transistor, the emitter of which is connected to the supply potential with the interposition of a fifth resistor, the collector of which is connected to the base of the fourth transistor and the base of which is coupled to the collector of the fifth transistor, and a seventh transistor whose base and Collector are coupled to each other and to the collector of the fifth transistor and the emitter is connected to the supply potential with the interposition of a sixth resistor.
  • an eighth resistor is connected in series to the further current source in the collector line of the sixth transistor.
  • the noise of the further current source has an influence on the noise behavior of the entire circuit arrangement, particularly at high frequencies. This is particularly troublesome when pnp transistors are used in the further current source, since these are far removed from an ideal transistor in terms of noise and the size of the parasitic capacitances.
  • the inserted eighth resistor insulates especially at high ones Frequencies is the non-ideal working other current source and thus improves the noise behavior and the output resistance.
  • the stability is improved, since the effective capacitance at the output of the further current source no longer influences the phase reserve of the entire circuit arrangement to such an extent.
  • the insertion of a series resistor is particularly recommended when implementing the sixth and seventh transistor as pnp transistors at a current output of the circuit arrangement.
  • an npn transistor T1 is provided, the emitter of which is connected to a reference potential M and whose base and collector are both connected to one another and are coupled via a common resistor R1 to an output terminal U carrying a reference potential.
  • the base of an npn transistor T2 is connected to the base and collector of the transistor T1, the emitter of which is coupled to the reference potential M via a resistor R3 and the collector of which is coupled to the output terminal U via a resistor R2.
  • the emitter of an npn transistor T4 is also connected to the output terminal U.
  • the base of the transistor T4 is connected to the collector of an npn transistor T3, the emitter of which is connected to the reference potential M and the base of which is connected to the collector of the transistor T2.
  • a capacitor C1 is connected in parallel with the resistor R2.
  • the base of transistor T4 is also connected to supply potential V via a resistor R8 and a current source circuit.
  • the current source circuit has a pnp transistor T6, the emitter of which is connected via a resistor R5 to the supply potential V and the collector of which is connected via resistor R8 to the base of the transistor T4 and the collector of the transistor T3.
  • the base of the transistor T6 is connected to the base and collector of a pnp transistor T7, the emitter of which is coupled to the supply potential V via a resistor R6.
  • the base and collector of the transistor T7 and the base of the transistor T6 are also connected to the collector of an npn transistor T5, the emitter of which is connected to the reference potential M via a resistor R4 and the base of which is connected to the output terminal U.
  • an output connection I can also be provided which carries a reference current.
  • the output terminal I is connected to the collector of a pnp transistor T8, the emitter of which is connected to the supply potential V via a resistor R7 and the base of which is connected to the bases of the transistors T6 and T7.
  • the dimensioning of the capacitor C1 depends on the respective application, whereby the noise behavior becomes higher with higher capacitances and the switch-on behavior with lower capacitances.
  • the resistor R8 is chosen as large as possible in order to ensure the highest possible insulation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
EP97106833A 1996-05-10 1997-04-24 Circuit pour générer une tension de référence Expired - Lifetime EP0806719B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19618914 1996-05-10
DE19618914A DE19618914C1 (de) 1996-05-10 1996-05-10 Schaltungsanordnung zur Erzeugung eines Referenzpotentials

Publications (3)

Publication Number Publication Date
EP0806719A2 true EP0806719A2 (fr) 1997-11-12
EP0806719A3 EP0806719A3 (fr) 1998-09-16
EP0806719B1 EP0806719B1 (fr) 2001-08-01

Family

ID=7793979

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97106833A Expired - Lifetime EP0806719B1 (fr) 1996-05-10 1997-04-24 Circuit pour générer une tension de référence

Country Status (3)

Country Link
US (1) US5883543A (fr)
EP (1) EP0806719B1 (fr)
DE (2) DE19618914C1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10357772A1 (de) * 2003-12-10 2005-07-14 Siemens Ag Steuereinheit und Steuervorrichtung mit der Steuereinheit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002008708A1 (fr) * 2000-07-26 2002-01-31 Stmicroelectronics Asia Pacifc Pte Ltd Circuit détecteur thermique

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3515006A1 (de) * 1984-04-26 1985-10-31 Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa Spannungsausgangskreis
EP0411657A1 (fr) * 1989-08-03 1991-02-06 Kabushiki Kaisha Toshiba Circuit à tension constante
GB2256949A (en) * 1991-06-19 1992-12-23 Samsung Electronics Co Ltd Integrated bandgap voltage reference having improved substrate noise immunity

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4553083A (en) * 1983-12-01 1985-11-12 Advanced Micro Devices, Inc. Bandgap reference voltage generator with VCC compensation
US5028527A (en) * 1988-02-22 1991-07-02 Applied Bio Technology Monoclonal antibodies against activated ras proteins with amino acid mutations at position 13 of the protein
US5029295A (en) * 1990-07-02 1991-07-02 Motorola, Inc. Bandgap voltage reference using a power supply independent current source
JP2953226B2 (ja) * 1992-12-11 1999-09-27 株式会社デンソー 基準電圧発生回路
US5757224A (en) * 1996-04-26 1998-05-26 Caterpillar Inc. Current mirror correction circuitry

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3515006A1 (de) * 1984-04-26 1985-10-31 Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa Spannungsausgangskreis
EP0411657A1 (fr) * 1989-08-03 1991-02-06 Kabushiki Kaisha Toshiba Circuit à tension constante
GB2256949A (en) * 1991-06-19 1992-12-23 Samsung Electronics Co Ltd Integrated bandgap voltage reference having improved substrate noise immunity

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BIRRITTELLA M S ET AL: "DESIGN TECHNIQUES FOR IC VOLTAGE REGULATORS WITHOUT P-N-P TRANSISTORS" IEEE JOURNAL OF SOLID-STATE CIRCUITS, NEW YORK, NY, US, Bd. 22, Nr. 1, Februar 1987, Seiten 71-76, XP000004174 *
BIRRITTELLA M S ET AL: "DESIGN TECHNIQUES FOR IC VOLTAGE REGULATORS WITHOUT P-N-P TRANSISTORS" IEEE JOURNAL OF SOLID-STATE CIRCUITS, NEW YORK, NY, US, Bd. 22, Nr. 1, Februar 1987. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10357772A1 (de) * 2003-12-10 2005-07-14 Siemens Ag Steuereinheit und Steuervorrichtung mit der Steuereinheit

Also Published As

Publication number Publication date
EP0806719A3 (fr) 1998-09-16
EP0806719B1 (fr) 2001-08-01
DE59704169D1 (de) 2001-09-06
US5883543A (en) 1999-03-16
DE19618914C1 (de) 1997-08-14

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