EP0717437A2 - Méthode pour former des couches enterrées d'oxide - Google Patents
Méthode pour former des couches enterrées d'oxide Download PDFInfo
- Publication number
- EP0717437A2 EP0717437A2 EP95308590A EP95308590A EP0717437A2 EP 0717437 A2 EP0717437 A2 EP 0717437A2 EP 95308590 A EP95308590 A EP 95308590A EP 95308590 A EP95308590 A EP 95308590A EP 0717437 A2 EP0717437 A2 EP 0717437A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- wafer
- oxygen
- oxide layer
- soi
- approximately
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000001301 oxygen Substances 0.000 claims abstract description 54
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 54
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 53
- 230000007547 defect Effects 0.000 claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 23
- 238000000137 annealing Methods 0.000 claims description 15
- 235000012431 wafers Nutrition 0.000 description 71
- 238000002513 implantation Methods 0.000 description 13
- 239000007943 implant Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- -1 boron Chemical class 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005305 interferometry Methods 0.000 description 1
- 150000001455 metallic ions Chemical class 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
Definitions
- the instant invention is directed to the manufacture of a silicon on insulator (SOI) wafer, and more particularly to a method of producing an SOI wafer having a buried oxide layer at a lower cost and which is also more reliable than conventionally known wafers. According to the method of the invention, such an SOI wafer can be produced using standard equipment in a normal production facility.
- SOI silicon on insulator
- SOI wafers having buried oxide layers are an attractive technology for deep-submicron CMOS and radiation-hardened devices because the buried oxide layer offers both device isolation and the ability to getter defects, such as oxygen and metallic ions, away from the operating region of the device.
- SIBOND With SIBOND wafers, as illustrated in Figure 1A, an oxide layer 12 is formed on the surface of a substrate 10. A second silicon wafer 14 is bonded to the top surface of the oxide layer 12. Using this method, the top wafer 14 must be formed relatively thin so that the oxide layer 12 is at the desired depth to achieve the device isolation. This results, in an increased potential for defects as the thin layer is worked.
- Another drawback to the SIBOND wafer is manufacturing cost.
- the SOI wafer cannot be incorporated into the "in-house" production of a semiconductor device. Instead, the SOI wafer must be purchased from an outside source.
- the second method employed to produce SOI wafers is SIMOX (i.e., S eparation by Im planted Ox ygen).
- SIMOX technology as illustrate in Figure 1B, oxygen 16 is implanted into the substrate 10 at relatively low energies to form the buried oxide layer 13.
- SIBOND one drawback for a semiconductor device manufacturer who wishes to use conventional SIMOX wafers is that the equipment need to produce such wafers is not of the type normally used in manufacturing semiconductor devices.
- typically SIMOX wafers must also be purchased from an outside source. Accordingly the costs of using SOI wafers is increased.
- SIMOX wafers are typically considered "dirty", in the sense that significant amounts of iron impurities are introduced into the wafer during oxygen implantation. Since Oxygen is not a standard species for ion implantation, the implanting device must be configured in a way which introduces these unwanted impurities.
- One of the downsides of using SIMOX wafers is that the iron rich nature of the wafer will significantly hinder the production and/or operation of most semiconductor devices.
- the oxygen implantation step is not practical for implementation in standard device production facilities as part of the manufacturing process.
- a method of manufacturing a wafer having a buried oxygen layer at a desired depth includes the step of implanting an ion into at least a portion of an oxygen-rich wafer to form a defect region at the desired depth in the oxygen rich wafer.
- the implantation is carried out at an energy level at or above 1 MeV.
- the method also includes the step of annealing the oxygen-rich wafer such that oxygen in the wafer is gettered to the defect region.
- phosphorous is used for the ion implantation at a dose between 4.5x10 14 /cm 2 and 1x10 15 /cm 2 .
- the method is used to produce an SOI wafer having a buried oxide layer at a desired depth.
- Figure 2 illustrates a device for which an SOI wafer manufactured according to the instant invention is to be used.
- a substrate 20 includes a buried oxide layer 22.
- a semiconductor device 26 is formed on the upper portion 24 of the wafer above the oxide layer 22, a semiconductor device 26 is formed.
- This type of structure is particularly advantageous in CMOS logic in that it prevents parasitic latch-up.
- This type of structure is also advantageous for use in radiation hardened devices, as it prevents problems associated with ⁇ -particles of radiation.
- FIGs 3A-3C illustrate a method for producing an SOI wafer according to an embodiment of the instant invention.
- a standard P-type (100) wafer which is grown in an oxygen-rich (e.g. approximately 1x10 18 cm 3 ) is provided as shown in Figure 3A.
- the oxygen-rich wafer is implanted with a standard species, in this case phosphorous (P), at an energy level of at least 1 MeV.
- P phosphorous
- the instant invention is not limited to phosphorous. Any standard species which generates the desired defect region could be used.
- having ions (relative to phosphorous) such as Arsenic can most easily be used to produce the desired effect.
- the implantation step could be carried out through an oxide layer (not shown) on the surface of wafer 35.
- the dosage of the phosphorous implant can be varied according to the desired effect. In the specific examples provided below, the doses were varied between approximately 5x10 14 cm 2 to 1x10 15 cm 2 .
- the high energy phosphorous implantation of Figure 3B creates a zone of defects 31 as a function of the phosphorous implant.
- the zone of defects 31 is approximately 1 micron beneath the surface of the wafer 35. Since the implantation energy is relatively high, the zone of defects 31 are formed as an amorphous layer roughly about 1 micron deep. The defect zone is not formed from the surface down to the region 31 (at 1 micron) as would be seen in conventional SIMOX oxygen implantation illustrated in Figure 1B. This is because a higher implantation energy is used as compared to the energy used for SIMOX oxygen implantation.
- the wafer 35 including the zone of defects 31, is subjected to a 30-minute 960° annealing process.
- the oxygen within the oxygen rich wafer 30 is drawn to the defects in the zone of defects 31.
- the background oxygen of the wafer 35 is drawn from both near the surface and from the bulk.
- a zone of oxygen is collected where the defects 31 were formed.
- an SOI wafer including a buried oxide layer 32 at a depth of approximately 1 micron is formed. In this manner, during the annealing step, the oxygen is gettered to the defects created by the phosphorous implant in order to produce a buried oxide layer.
- Figures 4A-4D illustrate SIMS profiles which illustrate features of the above described process for manufacturing an SOI wafer.
- Figure 4A shows a SIMS profile of the oxygen-rich wafer directly after a 1x10 15 cm 2 phosphorous implant at 1 MeV was carried out in the manner illustrated in Figure 3B.
- the SIMS profile of Figure 4A illustrates the properties of a wafer before the annealing step illustrated in Figure 3C is carried out.
- the background oxygen level 41 of the wafer is approximately 1x10 18 atoms/cm 2 .
- the location of the phosphorous implant 43 is also evident.
- Figure 4A also illustrates the absence of any buried oxygen layers within the wafer.
- Figures 4B and 4C illustrate wafers manufactured according to the instant invention after the annealing step of Figure 3C is carried out on implants of phosphorous at dosages of approximately 5x10 14 cm 2 and 1x10 15 cm 2 , respectively.
- a dosage of 5x10 14 a distinct oxide layer is formed at the oxygen peak 42 approximately 1 micron deep. This layer is approximately 0.5 microns wide and has a peak level of 5x10 18 cm 3 .
- the surrounding oxygen has been gettered in the production of the oxygen peak 42.
- Figure 4C illustrates a SIMS profile of a wafer after the annealing step which was implanted with phosphorous at a level of approximately 1x10 15 cm 2 .
- this process produced two oxygen peaks 43 and 44 at approximately 0.3 and 1.0 microns, respectively.
- the first oxygen peak 44 is similar to the oxygen peak 42 in Figure 4B.
- the second peak 43 is produced as a result of the phosphorous implant at the higher dosage which knocks oxygen from the surface into the substrate. In other words, some of the oxygen at the surface is knocked into the substrate by the phosphorous. This effect is even more pronounced when the phosphorous implant is carried out through an oxide layer on the surface of the substrate.
- the second oxygen peak 43 is not the result of defects created by the phosphorous implant, but rather is a result of oxygen actually moved from the surface to that region. This will be more fully understood from the description of the interferometry results described below.
- FIG 4D a wafer is shown wherein phosphorous was implanted at a dose of 5x10 14 cm 2 at approximately 1 MeV.
- the wafer prior to the annealing step illustrated in Figure 3C, the wafer is subjected to an H 2 15 minute 1,150° annealing treatment.
- H 2 treatment is carried out prior to the annealing step illustrated in Figure 3C, significant oxygen layers are not formed within the wafer.
- a slight oxygen peak 48 can be seen. However, this oxygen peak is not at a significant level.
- the H 2 anneal can be used to essentially prohibit the formation of the oxide layer (i.e., when it is desired that the oxygen not be gettered to the defect zone, an H 2 treatment can be carried out in order to push the oxygen towards the bottom of the substrate).
- an H 2 anneal can be used along with the phosphorous implant in a standard production line.
- an H 2 treatment could be carried out prior to the annealing step.
- the production of an SOI type substrate could be selectively carried out. That is, the same implant could be carried out when it is desired to create the same junction, but if the buried O 2 layer was not desired, the hydrogen annealing step would be inserted between the steps illustrated in Figure 3B and Figures 3C.
- the instant method for producing an SOI wafer could be carried out in a production process as desired, without committing the entire production line to an SOI type wafer.
- the interferometric results demonstrate that in each of the instances except for wafer 24, a defect region is detected at the depth of approximately 1 micron. The results did not produce a defect region above the 1 micron region. It is noted that for wafer 24 while the defect region exists no oxide layer is formed at the 1 micron level in order to reflect and examine the defect region. While in wafer 5 (illustrated in Figure 4D) only a small oxygen peak is formed, it is sufficient to examine the defect region.
- an oxide layer buried within the SOI wafer can be formed. The formation of the oxide layer can also be controlled by controlling the phosphorous implantation and/or the level of the background oxygen layer. Moreover, formation can be inhibited with an H 2 anneal.
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Glass Compositions (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US355298 | 1982-11-01 | ||
US35529894A | 1994-12-12 | 1994-12-12 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0717437A2 true EP0717437A2 (fr) | 1996-06-19 |
EP0717437A3 EP0717437A3 (fr) | 1997-04-02 |
EP0717437B1 EP0717437B1 (fr) | 2002-04-24 |
Family
ID=23396959
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP95308590A Expired - Lifetime EP0717437B1 (fr) | 1994-12-12 | 1995-11-29 | Méthode pour former des couches enterrées d'oxide |
Country Status (6)
Country | Link |
---|---|
US (1) | US5891743A (fr) |
EP (1) | EP0717437B1 (fr) |
JP (1) | JPH08255885A (fr) |
KR (1) | KR960026128A (fr) |
AT (1) | ATE216802T1 (fr) |
DE (1) | DE69526485T2 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261A1 (fr) * | 1997-12-30 | 1999-07-02 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
US6486043B1 (en) | 2000-08-31 | 2002-11-26 | International Business Machines Corporation | Method of forming dislocation filter in merged SOI and non-SOI chips |
FR2823596B1 (fr) | 2001-04-13 | 2004-08-20 | Commissariat Energie Atomique | Substrat ou structure demontable et procede de realisation |
US6602757B2 (en) * | 2001-05-21 | 2003-08-05 | International Business Machines Corporation | Self-adjusting thickness uniformity in SOI by high-temperature oxidation of SIMOX and bonded SOI |
FR2830983B1 (fr) | 2001-10-11 | 2004-05-14 | Commissariat Energie Atomique | Procede de fabrication de couches minces contenant des microcomposants |
US7176108B2 (en) | 2002-11-07 | 2007-02-13 | Soitec Silicon On Insulator | Method of detaching a thin film at moderate temperature after co-implantation |
FR2848336B1 (fr) | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
FR2856844B1 (fr) | 2003-06-24 | 2006-02-17 | Commissariat Energie Atomique | Circuit integre sur puce de hautes performances |
FR2857953B1 (fr) | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | Structure empilee, et procede pour la fabriquer |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
US7772087B2 (en) | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
FR2886051B1 (fr) | 2005-05-20 | 2007-08-10 | Commissariat Energie Atomique | Procede de detachement d'un film mince |
FR2889887B1 (fr) | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
FR2891281B1 (fr) | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
FR2899378B1 (fr) | 2006-03-29 | 2008-06-27 | Commissariat Energie Atomique | Procede de detachement d'un film mince par fusion de precipites |
FR2910179B1 (fr) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
FR2925221B1 (fr) | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | Procede de transfert d'une couche mince |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
CN116759325B (zh) * | 2023-08-23 | 2023-11-03 | 江苏卓胜微电子股份有限公司 | 用于监控离子注入剂量的阻值监控方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3622382A (en) * | 1969-05-05 | 1971-11-23 | Ibm | Semiconductor isolation structure and method of producing |
US4151007A (en) * | 1977-10-11 | 1979-04-24 | Bell Telephone Laboratories, Incorporated | Hydrogen annealing process for stabilizing metal-oxide-semiconductor structures |
US4371420A (en) * | 1981-03-09 | 1983-02-01 | The United States Of America As Represented By The Secretary Of The Navy | Method for controlling impurities in liquid phase epitaxial growth |
JPS6031231A (ja) * | 1983-07-29 | 1985-02-18 | Toshiba Corp | 半導体基体の製造方法 |
US4522657A (en) * | 1983-10-20 | 1985-06-11 | Westinghouse Electric Corp. | Low temperature process for annealing shallow implanted N+/P junctions |
JPS6151930A (ja) * | 1984-08-22 | 1986-03-14 | Nec Corp | 半導体装置の製造方法 |
JP3066968B2 (ja) * | 1988-07-25 | 2000-07-17 | ソニー株式会社 | 半導体ウエハのゲッタリング方法 |
US5229311A (en) * | 1989-03-22 | 1993-07-20 | Intel Corporation | Method of reducing hot-electron degradation in semiconductor devices |
JPH03201535A (ja) * | 1989-12-28 | 1991-09-03 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置とその製造方法 |
JPH0411736A (ja) * | 1990-04-28 | 1992-01-16 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5244819A (en) * | 1991-10-22 | 1993-09-14 | Honeywell Inc. | Method to getter contamination in semiconductor devices |
-
1995
- 1995-11-29 EP EP95308590A patent/EP0717437B1/fr not_active Expired - Lifetime
- 1995-11-29 DE DE69526485T patent/DE69526485T2/de not_active Expired - Fee Related
- 1995-11-29 KR KR19950044881A patent/KR960026128A/ko active IP Right Grant
- 1995-11-29 AT AT95308590T patent/ATE216802T1/de not_active IP Right Cessation
- 1995-12-12 JP JP7322879A patent/JPH08255885A/ja active Pending
-
1996
- 1996-12-24 US US08/773,769 patent/US5891743A/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
---|
None |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261A1 (fr) * | 1997-12-30 | 1999-07-02 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
WO1999035674A1 (fr) * | 1997-12-30 | 1999-07-15 | Commissariat A L'energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
US6756286B1 (en) | 1997-12-30 | 2004-06-29 | Commissariat A L'energie Atomique | Method for transferring a thin film comprising a step of generating inclusions |
US7229899B2 (en) | 1997-12-30 | 2007-06-12 | Commissariat A L'energie Atomique | Process for the transfer of a thin film |
Also Published As
Publication number | Publication date |
---|---|
DE69526485T2 (de) | 2002-12-19 |
US5891743A (en) | 1999-04-06 |
DE69526485D1 (de) | 2002-05-29 |
EP0717437A3 (fr) | 1997-04-02 |
EP0717437B1 (fr) | 2002-04-24 |
KR960026128A (fr) | 1996-07-22 |
ATE216802T1 (de) | 2002-05-15 |
JPH08255885A (ja) | 1996-10-01 |
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