EP0707758A1 - Circuit integre comprenant un etage de sortie pourvu d'un condensateur de miller - Google Patents

Circuit integre comprenant un etage de sortie pourvu d'un condensateur de miller

Info

Publication number
EP0707758A1
EP0707758A1 EP95915980A EP95915980A EP0707758A1 EP 0707758 A1 EP0707758 A1 EP 0707758A1 EP 95915980 A EP95915980 A EP 95915980A EP 95915980 A EP95915980 A EP 95915980A EP 0707758 A1 EP0707758 A1 EP 0707758A1
Authority
EP
European Patent Office
Prior art keywords
output
gate electrode
current channel
coupled
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP95915980A
Other languages
German (de)
English (en)
Other versions
EP0707758B1 (fr
Inventor
Eise Carel Dijkmans
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV, Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP95915980A priority Critical patent/EP0707758B1/fr
Publication of EP0707758A1 publication Critical patent/EP0707758A1/fr
Application granted granted Critical
Publication of EP0707758B1 publication Critical patent/EP0707758B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Definitions

  • Integrated circuit comprising an output stage with a Miller capacitor.
  • the invention relates to an integrated circuit, comprising an output stage with an input which is coupled to a first and a second gate electrode of a first and a second current channel, respectively, and an output which is connected to a first and a second supply terminal via the first and the second current channel, respectively, which output stage is arranged to switch over, under the control of a signal on the input, from a first state (L) in which the first and the second current channel are conductive and non-conductive, respectively, to a second state (H) in which the. first and the second current channel are non- conductive and conductive, respectively, the output being coupled to the first gate electrode via a series connection of a Miller capacitor and switching means.
  • An integrated circuit of this kind is known from US 5,051,625.
  • the first current channel in this circuit is formed by the channel of an NMOS transistor; the second current channel is the channel of a PMOS transistor.
  • the first state i.e. the "logic low” state
  • the channel of the NMOS transistor connects the output to the low supply voltage applied to the first supply terminal.
  • the ._cond state i.e. the "logic high” state
  • the channel of the PMOS transistor connects the output to the high supply voltage applied to the second supply terminal.
  • the voltage on the gate electrodes of the NMOS transistor and the PMOS transistor is logic low.
  • the voltage on the gate electrodes is raised from logic low to logic high.
  • the voltage on the output then decreases because the channel of the NMOS transistor starts to conduct whereas the channel of the PMOS transistor ceases to conduct. If switching over from the second to the first state is very fast, disturbances occur. The speed of switching over, and hence the occurrence of disturbances, is dependent on the degree of loading of the output.
  • the Miller capacitor provides retrocoupling of the voltage on the output to the gate electrode of the NMOS transistor. Such retrocoupling opposes the increase of the voltage on the gate electrode of the NMOS transistor. This opposition is greater as the rate of decrease of the voltage on the output is higher. Because the rate of decrease of the voltage on the output itself is dependent on the voltage on the gate electrode of the NMOS transistor, due to the characteristic of the NMOS transistor, the rate of decrease is thus limited.
  • the Miller capacitor thus controls the rate of decrease and limits the disturbances occurring upon . switching over from the second to the first state.
  • the channel of the PMOS transistor starts to conduct whereas the channel of the NMOS transistor ceases to conduct.
  • the rate at which the channel of the NMOS transistor ceases to conduct is then slowed down by the Miller capacitor, whereas the PMOS is already conductive.
  • a short-circuit current starts to flow from the first to the second supply terminal. This current causes interference pulses on the supply terminals and increases the power consumption of the circuit.
  • the channel of a further NMOS transistor is connected in series with the channel of the NMOS transistor. In response to the signal on the input, the channel of the further transistor is also rendered non-conductive when the channel of the NMOS transistor is rendered non-conductive.
  • an object of the invention to provide an integrated circuit which comprises an output stage with a Miller capacitor for limiting the switching speed and in which the short-circuit current remains limited without a substantial amount of additional surface area being required.
  • the integrated circuit in accordance with the invention is characterized in that it comprises a facility for rendering the switching means non-conductive ahead of the switching over from the first state (L) to the second state (H).
  • the first current channel can be rendered non-conductive more quickly, thus preventing the short-circuit current.
  • switching means arranged between the output and the first gate electrode are known per se from the cited US Patent (US 5,051,625).
  • the circuit according to the cited publication also has a high impedance state in which neither the NMOS transistor nor the PMOS transistor is conductive.
  • the circuit comprises a special enable input which is independent of the signal input and which serves to realise the high impedance state.
  • the switching means in the circuit according to the cited publication are provided to prevent coupling through of the signal from the input to the output via the Miller capacitor in the high impedance state.
  • the switching means are controlled via the enable input. Outside the high impedance state, notably upon switching over from the first state to the second state and vice versa, the switching means according to the cited publication remain conductive.
  • the first and the second gate electrode are directly interconnected, so that the first and second gate electrodes cannot be independently controlled either.
  • the switching means are rendered conductive again.
  • this switching over the Miller capacitor has the described effect of limiting the rate of decrease of the voltage on the output.
  • An embodiment of the integrated circuit in accordance with the invention is characterized in that it comprises a discharging circuit for discharging the Miller capacitor after the switching means have been rendered non-conductive.
  • the discharging circuit adjusts the voltage across the Miller capacitor to the value required for the next switching over from the second to the first state.
  • the rate at which the Miller capacitor is charged to the appropriate voltage defines the maximum frequency at which changes of state may succeed one another. If the change-overs were to succeed one another so quickly that after a change-over the voltage across the Miller capacitor has not yet reached the correct value for the next change ⁇ over, the first and the second current channel would be simultaneously conductive, thus causing a disturbing current pulse between the supply terminals.
  • the rate at which the Miller capacitor is charged to the appropriate voltage may not be too high as otherwise the current required to charge the Miller capacitor itself would cause a disturbing current pulse on the supply terminals.
  • a suitable compromise is to make the rate of charging of the Miller capacitor substantially equal to the rate of change of the output voltage.
  • An embodiment of the integrated circuit in accordance with the invention is characterized in that the discharging circuit comprises a third current channel which is of the same conductivity type as the first current channel, that the Miller capacitor is coupled to the first gate electrode via successively a junction and the switching means, that the junction is coupled to the first gate electrode via the third current channel, and that a third gate electrode of the third current channel is coupled to the output.
  • discharging takes place via the third current channel whose conductivity gradually increases at a rate which is dependent on the rate of change of the voltage on the output.
  • the discharging rate will thus be adapted to the rate of change of the output signal. Therefore, discharging will not be unnecessarily fast so that it does not cause an unnecessary current pulse on the supply terminal.
  • An embodiment of the integrated circuit in accordance with the invention is characterized in that the output is coupled to the second gate electrode via a further series connection of a further Miller capacitor and further switching means, and that it comprises a further facility for rendering the further switching means non-conductive ahead of the switching over from the second state (H) to the first state (L).
  • the rate of change of the voltage on the output is thus controlled also for the switching over from the first to the second state, without the switching over from the second to the first state giving rise to an unnecessary short-circuit current.
  • An embodiment of the integrated circuit in accordance with the invention is characterized in that the Miller capacitor is coupled to the first gate electrode via the switching means and to the second gate electrode via further switching means, and that the integrated circuit comprises a further facility for rendering the further switching means non- conductive ahead of the switching over from the second to the first state.
  • One Miller capacitor thus serves for the switching over from the first to the second state as well as for the switching over from the second to the first state, without giving rise to unnecessary short- circuit currents.
  • the surface area for a second Miller capacitor is thus saved.
  • a condition to be satisfied in this respect is, of course, that such switching over operations should not succeed one another so quickly that the Miller capacitor has not yet been fully charged or discharged upon switching over.
  • An embodiment of the integrated circuit in accordance with the invention is characterized in that the input is coupled to a third and a fourth gate electrode of a third and a fourth current channel, respectively, and that the first electrode is coupled, via the third current channel and via a series connection of a resistor and the fourth current channel, to the first and the second supply terminal, respectively.
  • the Miller capacitor Upon switching over from the second to the first state, the Miller capacitor is charged via the resistor and the fourth current channel and the voltage on the first gate electrode, therefore, will change gradually.
  • the voltage on the first gate electrode will change due to a current through the third current channel.
  • the switching means are not conductive for the latter switching over, so that the third current channel need not discharge the Miller capacitor.
  • the invention can be used notably in output stages intended to control output pins of the integrated circuit whereto a load which is not exactly known in advance is to be connected.
  • Fig. 1 shows an embodiment of a part of an integrated circuit in accordance with the invention
  • Fig. 2 shows a further embodiment of a part of an integrated circuit in accordance with the invention.
  • Fig. 1 shows an embodiment of a part of an integrated circuit 10 in accordance with the invention. It shows a logic circuit block 19, having an output coupled to an input I of an output stage with an output O. Between the input I and the output O there is arranged a parallel connection of an N-part 11 and a P-part 12, together constituting an output stage. The output O is coupled to a pin 13 of the integrated circuit 10. An external load capacitance C L is coupled to the pin 13 of the integrated circuit 10. The first and the second supply terminal (Vss, Vdd) of the integrated circuit are coupled to further pins of the integrated circuit via wires. These wires are symbolized by inductances L_, L N .
  • the input I of the N-part 11 is coupled to the input of a first input inverter 14.
  • the output of the first input inverter 14 is coupled to a first gate electrode.
  • This gate electrode serves to control the conductivity in a current channel which, in conjunction with the gate electrode, is conventionally indicated as a transistor.
  • the transistor comprising the first electrode is referred to as the first output transistor Nl.
  • the current channel of the first output transistor Nl is connected between the output O and the first supply terminal Vss.
  • the output O is coupled to a terminal of a Miller capacitor C ⁇ , the other terminal of which is coupled, via the current channel of an NMOS feedback transistor N2, to the first gate electrode.
  • the input I is coupled to the gate electrode of the NMOS feedback transistor N2 via an inverter 16.
  • the junction 17 of the Miller capacitor C MN and the current channel of the NMOS feedback transistor N2 is coupled to the first gate electrode via the current channel of an NMOS discharge transistor N3.
  • the P-section 12 is identical to the N-section, except that the NMOS transistors Nl, N2, N3 and the first input inverter 14 are replaced by PMOS transistors PI, P2, P3 and a second input inverter 15, respectively; the first supply terminal Vss and the second supply terminal Vdd are interchanged.
  • the Miller capacitor in the P-section 12 is referred to as C MP and the output transistor PI is referred to as the second output transistor.
  • the first and the second supply terminal (Vss, Vdd) are connected via successively the current channel of an NMOS transistor N4, a resistor R N and the current channel of a PMOS transistor P5.
  • the input of the first input inverter 15 is coupled to the gate electrodes of the transistors N4, P5.
  • a junction of the resistor R N and the current channel of the NMOS transistor N4 is coupled to the output of the first input inverter 14.
  • the P-section comprises a second input inverter 15 (P4, R ⁇ , N5) which is complementary to the first input inverter 14.
  • the first input inverter 14 acts as a conventional inverter, but the current that it can output from the second supply terminal Vdd is limited due to the resistor R ⁇ .
  • the output O of the circuit can assume one of two logic states, as shown in Fig. 1, under the control of the logic circuit block 19 which generates signals on the input I.
  • the first state output logic low
  • the voltage on the input I is logic low and the current channel of the output transistor Nl in the N-section 11 is conductive, whereas the current channel of the output transistor PI in the P-section 12 is not conductive.
  • the Miller capacitor C MN in the N-section 11 is conductively connected, via the current channel of the feedback transistor N2, to the gate electrode of the NMOS output transistor Nl.
  • the Miller capacitor C 1 in the N-section 11 Across the Miller capacitor C 1 in the N-section 11 a voltage arises which corresponds to the voltage difference between logic high and low as present on the gate electrode of the NMOS output transistor N2 and the output 0, respectively.
  • the Miller capacitor C P in the P-section 12 is isolated from the gate electrode of the second output transistor P2.
  • the current channel of the discharge transistor N3 in the N-section 11 is not conductive; that of the discharge transistor P3 in the P-section 12 is conductive.
  • Across the Miller capacitor C MP in the P-section 12 a voltage arises which corresponds to the voltage difference between logic high and low as present on the gate electrode of the PMOS output transistor P2 and the output O, respectively.
  • the circuit When the voltage on the input is made logic high, the circuit will switch over from the first to the second state (logic high). Under the control of the input, first the feedback transistor N2 is rendered non-conductive, via the inverter 16, so that the Miller capacitor C MN in the N-section 11 is isolated from the gate electrode of the NMOS output transistor Nl.
  • the first gate electrode of the output transistor Nl is pulled to the voltage on the first supply terminal Vss, so that the first output transistor Nl is rendered non-conductive. Because the current channel of the feedback transistor N2 isolates, it is not necessary to discharge the Miller capacitor, so that the first gate electrode of the first output transistor Nl can be pulled down quickly and without causing an unnecessary current pulse due to discharging of the Miller capacitor C MN . Because the voltage on the output O initially is still logic low, the current channel of the discharge transistor N2 isolates so that the charge across the Miller capacitor C MN in the N- section 11 is initially retained.
  • the current channel of the feedback transistor P2 in the P-section 12 is rendered conductive under the influence of the input.
  • the current channel of the discharge transistor P3 remains conductive under the influence of the output O.
  • the second gate electrode is also connected to the output O via the current channel of the transistors P2 and P3 and the Miller capacitor C MP .
  • the second input inverter 15 Upon said switching over to logic high, the second input inverter 15 starts to pull down the voltage on its output.
  • the second input inverter 15, however, is capable of delivering a limited current only.
  • This current charges the Miller capacitor C MP and the gate capacitance of the second output transistor P2.
  • the current channel of the second output transistor PI starts to conduct. Consequently, the load capacitance C L is charged and the voltage on the output O increases.
  • the rate of increase is codependent on the magnitude of the load capacitance. As the voltage on the output O increases faster, however, the Miller capacitor C MP will tend to push up the voltage on the second gate electrode again, thus slowing down the rising of the voltage on the output O.
  • the current channel of the discharge capacitor N3 in the N-section 11 will gradually start to conduct. Consequently, the voltage across the Miller capacitor C MN in the N-section 11 will ultimately correspond to the difference between the logic high and the logic low voltage as present on the output O and the gate electrode of the NMOS output transistor Nl, respectively.
  • Switching over from the second to the first state takes place in approximately the same way as the switching over from the first to the second state, be it that the roles of the N-section 11 and the P-section 12 are interchanged.
  • the currents required for switching over are derived via the supply terminals Vdd, Vss. These terminals are connected to the pins of the integrated circuit via connection wires.
  • the connection wires behave as inductances and, therefore, are represented by coils L n and L P in Fig. 1. Variations in the current through these wires, as occurring upon switching over, cause interference pulses.
  • the invention mitigates these interference pulses because the rate of change of the signal on the output is limited and because unnecessarily fast discharging of the Miller capacitors C MN , C MP is prevented by rendering the feedback transistors P2, N2 non-conductive before the output transistor Nl, PI, to the gate electrode of which they are coupled, is rendered non-conductive.
  • the feedback transistor N2 in the N-section 11 Upon switching over from the second to the first state, the feedback transistor N2 in the N-section 11 is rendered conductive. If the full voltage difference between the output O and the gate electrode of the NMOS input transistor Nl were not yet present across the Miller capacitor C MN in the N-section 11 at that instant, there would be a risk of the output transistor Nl becoming directly conductive at the beginning of switching over, when the NMOS transistor N4 closes, so that the current drawn by the output stage would quickly increase and hence a high induction voltage could arise across the inductance L. Therefore, the switching frequency of the signal on the output I is preferably kept so low that the Miller capacitor is allowed to reach its full voltage. The optimum discharging speed for the Miller capacitors C MN and C MP is, therefore, determined by a compromise. Excessively fast discharging causes unnecessary current pulses. Excessively slow discharging reduces the maximum usable frequency of the signal on the input I.
  • resistors or components acting as resistors, instead of the current channel of the discharge transistors N3, P3.
  • the resistances are then chosen so that the discharge rate of the Miller capacitors C MN , C MP is limited thereby to such an extent that discharging does not cause disturbing interference pulses (instead of to the gate electrode of the output transistors Nl, PI, these resistances can also be connected directly to the supply terminals V D r_, V ss , in the P-section 12 and the N-section 11).
  • Fig. 2 shows a further embodiment of a part of an integrated circuit 29 in accordance with the invention.
  • a logic circuit block 28 is coupled to an input I which is coupled, via a first input inverter 25, to a first gate electrode of a first output transistor 20 of the NMOS type.
  • the current channel of the first transistor 20 is connected between the first supply terminal Vss and the output O.
  • the first input inverter 25 has the same structure as the first input inverter 14 described with reference to Fig. 1.
  • the input I is also coupled, via a second input inverter 26, to a second gate electrode of a second output transistor 21 of the PMOS type.
  • the current channel of the second output transistor 21 is connected between the second supply terminal Vss and the output O.
  • the second input inverter 26 has the same structure as the second input inverter 15 described with reference to Fig. 1.
  • the output O is fed back to the first gate electrode via a Miller capacitor 22 and the current channel of an NMOS feedback transistor 23. Furthermore, the output O is fed back to the second gate electrode via this capacitor and the current channel of a PMOS feedback transistor 24. Via an inverter 27, the input I is coupled to the gate electrodes of the PMOS feedback transistor 24 and the NMOS feedback transistor 24.
  • the logic circuit block 28 can set the output O to each of two logic states.
  • the first state output logic low
  • the voltage on the input I is logic low and the current channel of the first output transistor 20 is conductive, whereas the current channel of the second output transistor 21 is not conductive.
  • the Miller capacitor 22 is conductively connected to the first gate electrode of the first output transistor 20 via the current channel of the feedback transistor 23.
  • the Miller capacitor 22 is isolated from the gate electrode of the second output transistor 21.
  • the Miller capacitor 22 is isolated from the gate electrode of the first output transistor 20 by rendering the feedback transistor 23 non-conductive.
  • the first gate electrode of the first output transistor 20 is pulled to the voltage on the first supply terminal Vss, so that the first output transistor 20 becomes non-conductive. Because the current channel of the feedback transistor 23 isolates, it is then unnecessary to discharge also the Miller capacitor, so that the first gate electrode of the first output transistor 20 can be pulled down quickly and without giving rise to an unnecessary current pulse for the discharging of the Miller capacitor 22.
  • the current channel of the feedback transistor 24 is rendered conductive, under the influence of the input, via the inverter 27.
  • the second gate electrode is connected to the output O via the current channel of the feedback transistor 24 and the Miller capacitor 22.
  • the second input inverter 26 pulls down the voltage on its output.
  • the second input inverter 26 is capable of delivering a limited current only. This current charges the Miller capacitor 22 and the gate capacitance of the second output transistor 21. Consequently, the current channel of the second output transistor 21 becomes conductive.
  • the voltage on the output O increases. The rate of increase is also dependent on the magnitude of the load capacitance. As the voltage rise on the output O is faster, however, the Miller capacitor 22 will push up the voltage on the second gate electrode, so that the rising of the voltage on the output O is slowed down.
  • Switching over from the second to the first state is quite similar to the switching over from the first to the second state, be it that the roles of the first supply terminal Vss, the inverter 25, the first output transistor 20 and the feedback transistor 23 are exchanged with those of the second supply terminal Vdd, the inverter 26, the second output transistor 21 and the feedback transistor 24, respectively.
  • the Miller capacitor 22 alternately performs the same slow-down task for the first and the second output transistor 20, 21 upon switching over from the first to the second state and over from the second to the first state, respectively.
  • the embodiment of Fig. 2 reduces the current pulses on the connection wires of the integrated circuit because unnecessary discharging of the Miller capacitor 22 is prevented.
  • this is at the expense of an inevitable reduction of the maximum usable frequency of transitions in the output signal. This is because these transitions should succeed one another with a spacing such that upon a transition the Miller capacitor has been charged or discharged to such an extent that the output transistor whereto it is coupled in first instance remains non- conductive. Interference pulses due to simultaneous conduction of the output transistors are thus prevented.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

Un circuit intégré comprend un étage de sortie pourvu d'une entrée (I) qui est couplée respectivement à une première et une seconde porte d'un transistor MOS à canal N (N1) et d'un transistor MOS à canal P (P1), et d'une sortie qui est connectée à une première (Vdd) et une seconde borne d'alimentation (Vss) par l'intermédiaire respectivement du transistor MOS à canal P et du transistor MOS à canal N. La sortie est couplée à la première porte par l'intermédiaire d'une connexion en série d'un condensateur de Miller (CMN) et d'un dispositif de commutation (N2, N3). Le condensateur de Miller limite le taux d'élévation des tensions à la sortie, ce qui évite les interférences. Le dispositif de commutation est rendu non conducteur avant la commutation d'un niveau bas de logique à un niveau élevé de logique. Ceci empêche une décharge soudaine du condensateur de Miller qui, sinon, se créerait lui-même des interférences.
EP95915980A 1994-05-09 1995-05-05 Circuit integre comprenant un etage de sortie pourvu d'un condensateur de miller Expired - Lifetime EP0707758B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP95915980A EP0707758B1 (fr) 1994-05-09 1995-05-05 Circuit integre comprenant un etage de sortie pourvu d'un condensateur de miller

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP94201298 1994-05-09
EP94201298 1994-05-09
PCT/IB1995/000329 WO1995031041A1 (fr) 1994-05-09 1995-05-05 Circuit integre comprenant un etage de sortie pourvu d'un condensateur de miller
EP95915980A EP0707758B1 (fr) 1994-05-09 1995-05-05 Circuit integre comprenant un etage de sortie pourvu d'un condensateur de miller

Publications (2)

Publication Number Publication Date
EP0707758A1 true EP0707758A1 (fr) 1996-04-24
EP0707758B1 EP0707758B1 (fr) 1999-08-04

Family

ID=8216864

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95915980A Expired - Lifetime EP0707758B1 (fr) 1994-05-09 1995-05-05 Circuit integre comprenant un etage de sortie pourvu d'un condensateur de miller

Country Status (5)

Country Link
US (1) US5587678A (fr)
EP (1) EP0707758B1 (fr)
JP (1) JPH09500515A (fr)
DE (1) DE69511206T2 (fr)
WO (1) WO1995031041A1 (fr)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08203270A (ja) * 1995-01-27 1996-08-09 Matsushita Electron Corp 半導体集積回路
JP2692637B2 (ja) * 1995-02-28 1997-12-17 日本電気株式会社 バスドライバ
US5760620A (en) * 1996-04-22 1998-06-02 Quantum Effect Design, Inc. CMOS limited-voltage-swing clock driver for reduced power driving high-frequency clocks
US5684420A (en) * 1996-05-29 1997-11-04 Vlsi Technology, Inc. Small signal amplifier for independent p-channel and n-channel drives
US5894241A (en) * 1996-09-30 1999-04-13 Cypress Semiconductor Corp. Bootstrap augmentation circuit and method
US5883531A (en) * 1997-08-18 1999-03-16 National Semiconductor Corporation Universal serial bus driver having MOS transistor gate capacitor
US5949259A (en) * 1997-11-19 1999-09-07 Atmel Corporation Zero-delay slew-rate controlled output buffer
US6225819B1 (en) 1998-03-17 2001-05-01 Cypress Semiconductor Corp. Transmission line impedance matching output buffer
JP2000049585A (ja) 1998-07-31 2000-02-18 Fujitsu Ltd 出力バッファ回路
US6060938A (en) * 1998-08-19 2000-05-09 Fairchild Semiconductor Corp. Output buffer for reducing switching noise
US6281730B1 (en) 1999-05-13 2001-08-28 National Semiconductor Corporation Controlled slew rate driver
JP3736227B2 (ja) * 1999-09-20 2006-01-18 富士電機デバイステクノロジー株式会社 ドライブ回路
US6384621B1 (en) 2001-02-22 2002-05-07 Cypress Semiconductor Corp. Programmable transmission line impedance matching circuit
US6753708B2 (en) * 2002-06-13 2004-06-22 Hewlett-Packard Development Company, L.P. Driver circuit connected to pulse shaping circuitry and method of operating same
US7888962B1 (en) 2004-07-07 2011-02-15 Cypress Semiconductor Corporation Impedance matching circuit
KR100706576B1 (ko) * 2005-08-01 2007-04-13 삼성전자주식회사 슬루율이 제어된 출력 구동회로
KR100832894B1 (ko) * 2005-10-06 2008-05-28 삼성전기주식회사 출력 버퍼회로
US8036846B1 (en) 2005-10-20 2011-10-11 Cypress Semiconductor Corporation Variable impedance sense architecture and method
JP2009531934A (ja) * 2006-03-31 2009-09-03 エヌエックスピー ビー ヴィ 容量帰還を用いる信号ドライバのための方法およびシステム
FR2907619B1 (fr) * 2006-10-20 2009-02-13 Atmel Nantes Sa Sa Dispositif d'interfacage de sortie compense en charge et circuit electronique correspondant.
US7652511B2 (en) * 2008-01-16 2010-01-26 Amazing Microelectronic Corp. Slew-rate control circuitry with output buffer and feedback
US9106378B2 (en) 2009-06-10 2015-08-11 Qualcomm Incorporated Systems, apparatus and methods for communicating downlink information
US9144037B2 (en) 2009-08-11 2015-09-22 Qualcomm Incorporated Interference mitigation by puncturing transmission of interfering cells
US8724563B2 (en) * 2009-08-24 2014-05-13 Qualcomm Incorporated Method and apparatus that facilitates detecting system information blocks in a heterogeneous network
US9277566B2 (en) 2009-09-14 2016-03-01 Qualcomm Incorporated Cross-subframe control channel design
US8942192B2 (en) 2009-09-15 2015-01-27 Qualcomm Incorporated Methods and apparatus for subframe interlacing in heterogeneous networks
US9271167B2 (en) 2010-04-13 2016-02-23 Qualcomm Incorporated Determination of radio link failure with enhanced interference coordination and cancellation
US9226288B2 (en) 2010-04-13 2015-12-29 Qualcomm Incorporated Method and apparatus for supporting communications in a heterogeneous network
US9125072B2 (en) 2010-04-13 2015-09-01 Qualcomm Incorporated Heterogeneous network (HetNet) user equipment (UE) radio resource management (RRM) measurements
US9392608B2 (en) 2010-04-13 2016-07-12 Qualcomm Incorporated Resource partitioning information for enhanced interference coordination
US8886190B2 (en) 2010-10-08 2014-11-11 Qualcomm Incorporated Method and apparatus for measuring cells in the presence of interference
US8638131B2 (en) * 2011-02-23 2014-01-28 Qualcomm Incorporated Dynamic feedback-controlled output driver with minimum slew rate variation from process, temperature and supply
KR20140146482A (ko) * 2013-06-17 2014-12-26 에스케이하이닉스 주식회사 반도체시스템
DE102014209694A1 (de) * 2014-05-21 2015-11-26 Robert Bosch Gmbh Teilnehmerstation für ein Bussystem und Verfahren zur Erhöhung der Störfestigkeit im Bereich der elektromagnetischen Verträglichkeit für eine Teilnehmerstation
US9548726B1 (en) * 2015-02-13 2017-01-17 Inphi Corporation Slew-rate control and waveshape adjusted drivers for improving signal integrity on multi-loads transmission line interconnects
US10826466B1 (en) * 2019-09-26 2020-11-03 Stmicroelectronics S.R.L. Digital output buffer circuits with reduced input/output delay

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857863A (en) * 1988-08-25 1989-08-15 Motorola, Inc. Low power output driver circuit with slew rate limiting
US5051625B1 (en) * 1988-10-28 1993-11-16 Nissan Motor Co.,Ltd. Output buffer circuits for reducing noise
KR920702576A (ko) * 1990-06-20 1992-09-04 고스기 노부미쓰 출력 버퍼 회로
US5218239A (en) * 1991-10-03 1993-06-08 National Semiconductor Corporation Selectable edge rate cmos output buffer circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9531041A1 *

Also Published As

Publication number Publication date
WO1995031041A1 (fr) 1995-11-16
DE69511206T2 (de) 2000-02-17
US5587678A (en) 1996-12-24
EP0707758B1 (fr) 1999-08-04
DE69511206D1 (de) 1999-09-09
JPH09500515A (ja) 1997-01-14

Similar Documents

Publication Publication Date Title
US5587678A (en) Integrated circuit having an output stage with a Miller capacitor
JP2996301B2 (ja) 負荷及び時間適応電流供給ドライブ回路
US5036222A (en) Output buffer circuit with output voltage sensing for reducing switching induced noise
EP0212584B1 (fr) Circuit de sortie avec stabilisation du niveau
US4827159A (en) High power buffer circuit with low noise
US5206544A (en) CMOS off-chip driver with reduced signal swing and reduced power supply disturbance
US4820942A (en) High-speed, high-drive output buffer circuits with reduced ground bounce
US4789796A (en) Output buffer having sequentially-switched output
US4825099A (en) Feedback-controlled current output driver having reduced current surge
US6680637B2 (en) Phase splitter circuit with clock duty/skew correction function
US5367210A (en) Output buffer with reduced noise
GB1589414A (en) Fet driver circuits
US4973861A (en) Integrated circuit comprising logic circuits and at least one push-pull stage
EP0439149B1 (fr) Circuits digitaux semi-conducteurs
JPH06244706A (ja) 補償形低域フィルタ網を備えた入力バッファ
US5059823A (en) Supply bounce controlled output buffer circuit
JPH0738401A (ja) ノイズ低減出力段を備えた集積回路
US6958626B2 (en) Off chip driver
JPH02119427A (ja) 出力バッファ回路
EP0962050A1 (fr) Etage de sortie a autoregulation de la vitesse de variation
EP1451932B1 (fr) Attaqueur de sortie comprenant un circuit de commande perfectionne
US6359489B1 (en) Clock signal generation and buffer circuit having high noise immunity and low power consumption
US6650156B1 (en) Integrated circuit charge pumps having control circuits therein that inhibit parasitic charge injection from control signals
WO1997008831A1 (fr) Circuit tampon cmos accelere
US5406215A (en) Open drain driver circuit which eliminates overshoot caused by parasitic capacitances

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19960517

17Q First examination report despatched

Effective date: 19961217

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

RAP3 Party data changed (applicant data changed or rights of an application transferred)

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V.

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 19990804

REF Corresponds to:

Ref document number: 69511206

Country of ref document: DE

Date of ref document: 19990909

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20010523

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20010531

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20010717

Year of fee payment: 7

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020505

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20021203

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20020505

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030131

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST