EP0706100B1 - Zeitintervalmessvorrichtung - Google Patents

Zeitintervalmessvorrichtung Download PDF

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Publication number
EP0706100B1
EP0706100B1 EP95402202A EP95402202A EP0706100B1 EP 0706100 B1 EP0706100 B1 EP 0706100B1 EP 95402202 A EP95402202 A EP 95402202A EP 95402202 A EP95402202 A EP 95402202A EP 0706100 B1 EP0706100 B1 EP 0706100B1
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EP
European Patent Office
Prior art keywords
clock
signal
circuit
flip
flop
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP95402202A
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English (en)
French (fr)
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EP0706100A1 (de
Inventor
Pascal Besesty
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time

Definitions

  • the present invention relates to a device for measure of the duration of a time interval.
  • the field of the invention is that of chronometry, of the precise time measurement of a period of time, short or infinitely long, included between a start signal and an end signal measured.
  • the present invention aims to resolve these problems.
  • the digital circuit is provided with a second clock, the pulses of which are offset from those of the first clock, the digital circuit also counts the number of pulses of the second clock which are followed by a period whole and which are included between the start (D) and end (F) signal, the analog circuit determines on the one hand the time separating the signal (D) and the start of the first pulse of the second clock which starts after (D) and, on the other hand, the time separating the end signal (F) from the end of the last period of the second clock which ends before (F), and this analog circuit is able to convert the data analog obtained in digital data.
  • the device also comprises means capable of determining which of the counts made on one of the two clocks (H 1 , H 2 ) is to be taken into account, so as to resolve any ambiguity situation which could lead to an error in counting a clock period.
  • start (D) and end (F) signals can be completely asynchronous from the clock. This is interesting for applications in the field of "time of flight" type telemetry, in which (D) and (F) are given by the start of a light pulse and by receiving the reflected pulse on a object, these two signals (D) and (F) can be asynchronous to the clock.
  • the part is measured coarse the time interval so digital, and the thin part analogically.
  • the parameters thus acquired are then recombined to get the result.
  • the measurement of time is thus obtained by associating a numerical quantity under the form of a number of clock periods counted, and analog quantities obtained by conversion of time in voltage amplitudes.
  • a triangular signal R of period 2T, of amplitude A, and synchronous with the base clock of period T is used.
  • a is the amplitude measured on the ramp
  • the t elapsed since the start of the ramp is equal to T / A • a .
  • t 1 and t 2 are then digitized, which gives two corresponding values T 1 and T 2 .
  • a device for the implementation of the invention is shown in Figure 2.
  • a clock H delivers pulses of period T on one of the inputs of an AND gate, designated by reference 2.
  • This clock H can be produced from a quartz oscillator, operating for example at a 200 MHz frequency.
  • the other door entrance AND receives a signal from the Q output of a flip-flop RS designated by reference 4, on input S of which we send the start signal D, while input R is controlled by the end signal F.
  • the assembly constituted by the AND gate, the flip-flop 4 and clock H constitutes a digital measurement circuit to obtain a rough value of the time interval to be measured. This value is equal at nT where n is the number of clock periods T elapsed between the start signal D and the end signal F. It is counted in a counter 3.
  • a division of the frequency of the signals of the clock H is carried out by a divider 6, constituted for example by a rocker, the output of this divider supplying a ramp generator 8.
  • This generator can be produced by the load and the constant current discharge of a capacitor. The period and the slope of these ramps are very well defined.
  • the output of the ramp generator 8 is sent to a fast analog-digital converter 10 (for example of the flash or fast sampler + converter type), another input of which receives a signal coming for example from a flip-flop 12, controlled by the signals D and F at the start and end of the period to be measured.
  • the converter 10 takes the information on the amplitude of the ramp at the instants of start D and of end F of the time interval to be measured, as well as the information relating to the parity of the ramp at these instants, that is to say, its ascending or descending character.
  • This converter makes it possible to obtain the information relating to the values T 1 and T 2 .
  • This information is stored in a memory 13.
  • the rough information relating to nT and the "fine" information relating to the intervals T 1 and T 2 are sent to a processing circuit 14 which calculates the duration t v of the time interval to be measured.
  • This device provides good precision, since it eliminates all synchronization of the start D and end F signals of measurement in relation to the clock H of the chronometer; he also eliminates limited capacity of the chronometer to determine a weak and a very significant time difference, which may vary by a few picoseconds to infinity, because of its frequency which is fixed.
  • This device also makes it possible to determine large time intervals with precision constant, regardless of the length of this interval of time. This is not true in the case of devices for measuring the duration of an interval of time according to the prior art, in particular in the case of device described in the French patent application n ° 93 08145 of July 2, 1993. Indeed, the latter device involves, at the start of measurement the time interval, the discharge of a capacitor, and at the end of the time interval measurement the charge of the same capacitor; however, the load measured immediately after the arrival of signal D may vary before we reach the final part of the time interval to be measured, just before the signal of end F, and this all the more since the interval of time to measure is important. In the device according to the present invention, this problem is avoided by having use of recurrent ramps.
  • this type of device can be easily integrated to create a compact circuit.
  • the invention allows problems related to be taken into account ambiguity on the starting signal D and on the arrival signal F. These problems arise when either of these signals occur simultaneously with a rising or falling edge of clock signals.
  • the game counter device numeric, part that determines the measurement coarse time interval, can then count an additional clock pulse, which would not have not to be counted.
  • a clock H 1 delivers signals of period T.
  • a divider allows generate signals S 1 , of period 2T, synchronized with the signals of the clock H 1 . It is thus possible to generate rising and falling ramps R 1 , of amplitude A.
  • a delay device makes it possible to generate a second clock signal H 2 , from the signal H 1 , the signals H 2 being shifted by T / 2 with respect to the signals of H 1 .
  • a falling edge of a slot of H 2 corresponds to a rising edge of a slot of H 1 , as can be seen in FIG. 3.
  • This clock signal H 2 makes it possible to generate, in the same way that it has been explained above for the clock H 1 , a signal S 2 of period 2T, which will itself control a ramp R 2 of the same amplitude A as the ramp R 1 .
  • the two ramps R 1 and R 2 are sampled simultaneously. If there is for example ambiguity between D and H 1 , that is to say if the signal D is superimposed on a rising edge of a slot of H 1 , there cannot be simultaneously ambiguity between the signal D and the signals generated by H 2 , due to the shift of a half-period between the two channels.
  • the valid clock to determine the measurement of t 1 is the clock H 2 and the value to be taken into account is that measured on the ramp R 2 .
  • a first counter 25 receives on its CE authorization input a counting order coming from a flip-flop 23 and on its input C the clock signals H 1 .
  • the data at the output of the first counter 25 are transmitted to a processing circuit 22 by means of a routing circuit 36 controlled by an OR circuit 32.
  • the D flip-flops 26 and 30 receive the D and F signals via an OR 40, 41 function on their D input.
  • the flip-flop 23, which delivers the CE authorization signal, is also controlled by the D and F signals both delayed by an amount close to 3 propagation times in gates by devices 19, 42 which consist for example of delays in logic gates.
  • the first AND circuit 27 performs the AND function of the output of the flip-flop 26 and of the clock H 2 ; the signals of the latter are obtained from H 1 and a delay circuit 18, constituted for example by propagation times in gates.
  • a second counter 29 receives on its CE authorization input a counting order coming from the flip-flop 23.
  • the data from this counter 29 is transmitted to the processing circuit 22 via the circuit 36.
  • the second flip-flop type D 30 works as described above.
  • the second AND circuit 31 performs the AND function between the output of circuit 30 and the clock H 1 .
  • the output of circuit 32 controls the operation of the switching circuit 36 to obtain reading of counter 25 or 29 including the type flip-flop D (26 or 30) partner did not switch first. he detects the first of flip-flops 26 or 30 that has toppled and it authorizes the reading of the counter whose rocker has not changed state.
  • circuits 44, 45 and 46, 47 respectively for the first and second counters. Circuits 44 and 46 are AND circuits, circuits 45 and 47 are time formatting.
  • a flip-flop 33 receives on its SET input the output of an OR 34 circuit whose inputs correspond to signals D and F delayed by circuits 42 and 19.
  • the flip-flop 33 receives on its other input the outputs of the two doors AND 27, 31.
  • This flip-flop 33 controls an input of an analog-digital converter 50 and an input of an analog-digital converter 52. Another input of each of these converters 50, 52 is connected to the clock H 1 (respectively H 2 ) via a flip-flop 51 (respectively 53) which makes it possible to generate a signal S 1 respectively S 2 of period 2T, and a ramp generator 55 (respectively 57) to generate a ramp R1 (respectively R2). Downstream of the analog-digital converters, there are two memories 60, 62 and a switching circuit 56 controlled by the circuit 32.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Claims (8)

  1. Vorrichtung zum Messen eines Zeitintervalls, enthalten zwischen einem Anfangs-Signal (D) und einem Ende-Signal (F),
    dadurch gekennzeichnet, daß sie umfaßt:
    einen ersten Takt (H, H1), der Impulse mit einer Periode T liefert, sowie einen zweiten Takt (H2), dessen Impulse in bezug auf den ersten Takt (H1) verschoben sind,
    eine Digitalschaltung (2, 3, 4; 20), um die Anzahl der Impulse des ersten Takts zu zählen, denen eine ganze Periode T folgt und die enthalten sind zwischen dem Anfangs-Signal (D) und dem Ende-Signal (F), wobei die Digitalschaltung (20) ebenfalls die Anzahl der Impulse des zweiten Takts zählt, denen eine ganze Periode T folgt und die enthalten sind zwischen dem Anfangs-Signal (D) und dem Ende-Signal (F),
    eine Analogschaltung (6, 8, 12, 10, 13; 21), um einerseits die Zeit t1 zu bestimmen, die das Signal (D) und den Anfang des ersten Impulses des ersten Taktes, der nach (D) beginnt, trennt, und andererseits die Zeit t2, die das Ende-Signal (F) von dem Ende der letzten Periode des ersten Takts trennt, die vor (F) endet, sowie einerseits die Zeit, die das Signal (D) und den Anfang des ersten Impulses des zweiten Taktes, der nach (D) beginnt, trennt, und andererseits die Zeit, die das Ende-Signal (F) von dem Ende der letzten Periode des zweiten Takts, der vor (F) endet, trennt, wobei die Analogschaltung zudem fähig ist, die erhaltenen Analogdaten in Digitaldaten umzuwandeln,
    eine Verarbeitungsschaltung (14, 22), um die Dauer des Zeitintervalls zu bestimmen aufgrund der durch die Digitalschaltung gelieferten Daten sowie der durch die Analogschaltung gelieferten und im voraus in Digitaldaten umgewandelten Daten,
    Einrichtungen, um zu bestimmen, welche der an einem der beiden Takte (H1, H2) vorgenommenen Zählungen zu berücksichtigen ist, um jede Zweideutigkeits-Situation, die zu einem Zählfehler einer Taktperiode führen könnte, aufzulösen.
  2. Vorrichtung nach Anspruch 1, daß die Analogschaltung außerdem umfaßt:
    eine Frequenzteilerschaltung, verbunden mit dem ersten Takt,
    einen ersten Sägezahngenerator (8; 57), gesteuert durch das Ausgangssignal der Frequenzteilerschaltung (6; 53),
    und einen ersten Analog-Digital-Wandler (10; 52), der einerseits das durch den ersten Sägezahngenerator (8; 57) erzeugte Signal erhält und andererseits das Anfangs-Signal (D) und das Ende-Signal (F) des zu messenden Zeitintervalls.
  3. Vorrichtung nach Anspruch 2, wobei das Anfangs-Signal (D) und das Ende-Signal (F) des zu messenden Zeitintervalls über eine Kippschaltung (12; 33) zum ersten Analog-Digital-Wandler (10; 52) übertragen werden.
  4. Vorrichtung nach einem der Ansprüche 1 bis 3, wobei die Digitalschaltung (20) ebenfalls umfaßt:
    eine Kippschaltung des Typs RS (23), an ihrem SET-Eingang durch das Anfangs-Signal (D) gesteuert, verzögert nach Durchlaufen einer ersten Verzögerungsschaltung (42), und an ihrem RESET-Eingang durch das Ende-Signal (F), verzögert nach Durchlaufen einer Verzögerungsschaltung (19),
    einen ersten Block (24) mit einem ersten Zähler (25), einer ersten Kippschaltung des Typs D (26), einer ersten UND-Schaltung (27), einer ersten ODER-Schaltung (40), einer zweiten UND-Schaltung (44), einer Einrichtung zur zeitlichen Signalformung (45),
    einen zweiten Block (28) mit einem zweiten Zähler (29), einer zweiten Kippschaltung des Typs D (30), einer dritten UND-Schaltung (31), einer zweiten ODER-Schaltung (41), einer vierten UND-Schaltung (46), einer Einrichtung zur zeitlichen Signalformung (47),
    eine Schaltung (32) zum Ausführen einer ODER-Funktion, um festzustellen, welcher von den Ausgängen der Kippschaltungen (26, 30) als erster gekippt ist.
  5. Vorrichtung nach Anspruch 4, bei der in dem ersten Block (24) der erste Zähler (25) auf seinem Freigabeeingang CE einen von der Kippschaltung (23) des Typs RS kommenden Zählbefehl erhält, die Ausgangsdaten des ersten Zählers (25) mittels einer Weichenschaltung (36), gesteuert durch die ODER-Schaltung (32), zur Verarbeitungsschaltung (22) übertragen werden, die erste Kippschaltung des Typs D (26), gesteuert durch die erste ODER-Schaltung (40), einerseits das Anfangs-Signal (D) und das Intervallende-Signal (F) und andererseits die Impulse des ersten Takts (H1) erhält, und die erste UND-Schaltung (27) die UND-Funktion zwischen einerseits dem Ausgang der ersten Kippschaltung des Typs D (26) und andererseits den Impulsen des zweiten Takts (H2) erfüllt.
  6. Vorrichtung nach einem der Ansprüche 4 oder 5, bei der in dem zweiten Block (28) der zweite Zähler (29) auf seinem Freigabeeingang (CE) einen von der Kippschaltung (23) des Typs RS kommenden Zählbefehl erhält, die Ausgangsdaten dieses Zählers (29) mittels einer Weichenschaltung (36) zur Verarbeitungsschaltung (22) übertragen werden, die zweite Kippschaltung des Typs D (26), gesteuert durch die zweite ODER-Schaltung (41), einerseits das Anfangs-Signal (D) und das Intervallende-Signal. (F) und andererseits die Impulse des zweiten Takts (H2) erhält, und die zweite UND-Schaltung (31) die UND-Funktion zwischen einerseits dem Ausgang dieser Kippschaltung D (30) und den Impulsen des ersten Takts (H1) erfüllt.
  7. Vorrichtung nach den Ansprüchen 3 und 4, bei der die Kippschaltung (33) einerseits den Ausgang einer ODER-Schaltung (34) erhält, deren Eingänge den verzögerten Signalen (D) und (F) entsprechen, und andererseits die Ausgänge der ersten und der dritten UND-Schaltung (27, 31).
  8. Vorrichtung nach Anspruch 7, einen zweiten Analog-Digital-Wandler (50) umfassend, gesteuert durch den Ausgang der Kippschaltung (33) und durch den Ausgang eines zweiten Sägezahngenerators (55), seinerseits selbst durch Ausgang eines zweiten Impulsteilers (51) des zweiten Takts (H2) gesteuert.
EP95402202A 1994-10-04 1995-10-02 Zeitintervalmessvorrichtung Expired - Lifetime EP0706100B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9411848A FR2725326B1 (fr) 1994-10-04 1994-10-04 Dispositif de mesure de la duree d'un intervalle de temps
FR9411848 1994-10-04

Publications (2)

Publication Number Publication Date
EP0706100A1 EP0706100A1 (de) 1996-04-10
EP0706100B1 true EP0706100B1 (de) 1998-08-12

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EP95402202A Expired - Lifetime EP0706100B1 (de) 1994-10-04 1995-10-02 Zeitintervalmessvorrichtung

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US (1) US5717659A (de)
EP (1) EP0706100B1 (de)
DE (1) DE69504000T2 (de)
FR (1) FR2725326B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3451576B2 (ja) 1996-09-20 2003-09-29 株式会社日立製作所 情報処理システム
US7843771B2 (en) * 2007-12-14 2010-11-30 Guide Technology, Inc. High resolution time interpolator
CN110737189B (zh) * 2019-11-05 2021-02-09 中国电子科技集团公司第四十四研究所 脉冲激光间隔测量电路
CN112506031B (zh) * 2020-11-30 2021-09-21 中国计量科学研究院 一种激光干涉条纹信号的高精度时间间隔测量系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503376A (de) * 1973-05-11 1975-01-14
US4912734A (en) * 1989-02-14 1990-03-27 Ail Systems, Inc. High resolution event occurrance time counter
US5200933A (en) * 1992-05-28 1993-04-06 The United States Of America As Represented By The United States Department Of Energy High resolution data acquisition
JP2568145Y2 (ja) * 1992-08-14 1998-04-08 株式会社アドバンテスト 信号時間差測定装置
FR2707814B1 (fr) * 1993-07-02 1995-09-01 Commissariat Energie Atomique Dispositif de mesure de la durée d'un intervalle de temps.
US5325340A (en) * 1993-07-29 1994-06-28 Ramsey Alexander W Pacing device

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Publication number Publication date
FR2725326A1 (fr) 1996-04-05
FR2725326B1 (fr) 1996-10-25
US5717659A (en) 1998-02-10
DE69504000T2 (de) 1999-02-25
EP0706100A1 (de) 1996-04-10
DE69504000D1 (de) 1998-09-17

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