EP0729082B1 - Sehr genaue Chronometrierung eines Vorfalls - Google Patents

Sehr genaue Chronometrierung eines Vorfalls Download PDF

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Publication number
EP0729082B1
EP0729082B1 EP96400306A EP96400306A EP0729082B1 EP 0729082 B1 EP0729082 B1 EP 0729082B1 EP 96400306 A EP96400306 A EP 96400306A EP 96400306 A EP96400306 A EP 96400306A EP 0729082 B1 EP0729082 B1 EP 0729082B1
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EP
European Patent Office
Prior art keywords
event
time
time interval
clock
duration
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP96400306A
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English (en)
French (fr)
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EP0729082A1 (de
Inventor
Thierry Potier
Michel Geesen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
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Dassault Electronique SA
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Publication of EP0729082A1 publication Critical patent/EP0729082A1/de
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time

Definitions

  • chronometry is the dating of a event relative to a time reference.
  • This timing is known electronically, but becomes particularly difficult when a very large precision is necessary, as is the case for example for the timing of the arrival of laser beams, for distance measurement, or other operations based on the time, such as synchronizing remote clocks.
  • the present invention aims to do better, in particular by going down under the hundred, or better yet the ten picoseconds.
  • the time slot begins with the event, and ends with the impulse next clock.
  • the time constant circuit is a double integrator, using the fast charge of a capacitor during the time slot, followed by a discharge slow.
  • the discharge time defines a second time slot temporal.
  • the circuit can be arranged so that the duration of the second time slot is increased according to a known law, noticeably monotonous, compared to the duration of the first time slot (hence the time stretch).
  • a counter secondary measures the duration of the second time slot, which provides the fine secondary timing of the event, preferably compared to the same clock.
  • the present invention proposes a better solution.
  • the logical means are arranged to produce a time slot that begins at a time linked to the event and ends in a clock pulse which is at minus the second encountered after its start. Consequently, the duration of the time slot becomes greater than or equal to the clock period T0. It is between T0 and (k + 1) .T0, with k at least equal to 1.
  • the time constant circuit is a filter of selected characteristics, having a time constant greater, in principle significantly greater, than the duration nominal time slot.
  • the measurement means operate on a selected part of the filter's response to the time slot.
  • the filter is a low-pass filter
  • the part chosen of its answer is in the vicinity of the maximum of this response, and it was observed that the amplitude of this part is then representative of the duration of the time slot.
  • the circuit includes a clock 1 operating at a frequency F 0 which is for example 200 MHz.
  • This clock is of a suitable stability for the desired precision, which is considered here as accessible to a person skilled in the art.
  • the signal delivered by this clock 1 serves as the first input signal to a unit 2 grouping together logic circuits.
  • This unit 2 receives on a second EV input, a second electrical signal, in steps.
  • This step EV signal represents the event to be dated.
  • This step represents by example the rise time of a photodetector receiving a laser beam.
  • the present invention aims to achieve temporal precision from 2 to 3 picoseconds in quadratic mean value (RMS), for an electrical step signal whose rise time is 200 picoseconds.
  • RMS quadratic mean value
  • the logic circuits grouped in unit 2 are ECL technology.
  • the departure of the counting begins at an instant TRF, also defined by a step signal or a pulse validating the counter 210.
  • the counting stops when a signal representative of the step EV is applied to the second input PRE of the counter 210, after passing through the components FF1, CL3, FF3 and FF2.
  • the state of the counter is stored, for example in a register 212, which is then capable of providing a digital signal CHR1, representing the primary chronometry, in principle unambiguous but whose precision is limited by the period d 'clock T 0 .
  • the mode of transfer of the state of the counter 210 in the register 212 can depend on whether the counter 210 is synchronous or asynchronous. Information to this effect can be found in FR-2 492 563, already cited.
  • the EV step to date (third line from top) occurs during the Nth state of counter 210 at from the reference time TRF.
  • the logic unit 2 also includes a stage 22, the function is to generate a time slot IMP (t) (more precisely an electrical signal forming a time slot), linked to the time difference between the EV event and an impulse clock position known relative to this event.
  • IMP (t) results from a logical operation, carried out by the logical component CL1, between the EV step from FF1 and the signal from the third flip-flop component FF3, representative position clock pulses delivered by the clock 1.
  • IMP (t) is represented on the last line of Figure 3.
  • the clock pulse of known position corresponds to the N + 2 (th) pulse of clock 1, that is to say the second clock pulse following the EV step.
  • the time slot, noted IMP (t) the time slot, noted IMP (t).
  • FF3 also delivers on a second output, a signal CDE0 whose rising edge coincides with the end of the time slot IMP (t).
  • This pulse CDE0 is applied to the first ARM input of a digital timing circuit 228 capable of providing a time delay T E , and whose time base is the clock signal 1 applied to its second input CLK, which provides at the output of the timing circuit 228 a signal CDE which will serve to control the sampling of the event, which will be described later.
  • the unit 2 also comprises a sub-assembly 23, to generate two calibration slots denoted IMP1 (t) and IMP2 (t), of duration T 0 and 2T 0 respectively .
  • This sub-assembly 23 more particularly comprises the two flip-flop components FF4 and FF5, the respective outputs of which are coupled by a second logic component CL2 which delivers the result of its logic operations to FF3.
  • control signals C_IMP, 1/2 and RESET are derived from a microprocessor 5 which will be described later.
  • the slots IMP1 (t) and IMP2 (t) provide a framework for the duration of the IMP slot (t).
  • the slot signal IMP1 (t) ( Figure 4B) corresponds to the minimum duration of IMP (t), which is the period T 0 of the clock 1.
  • the slot signal IMP2 (t) ( Figure 4C) corresponds to the maximum duration of IMP (t), which is the period 2T 0 .
  • the slot issued at the output of the ECL 2 logic unit is applied to an APO amplifier, followed by a low-pass filter FPB, then a storage circuit SB, which is preferably a sampler-blocker or a follower-blocker.
  • the slots are first applied to a betting circuit in form 30, consisting of a clipping amplifier having a current output.
  • a betting circuit in form 30 consisting of a clipping amplifier having a current output.
  • stage 30 The output of stage 30 is applied to a first stage of filtering 31. It includes a resistor 310 of value R1, a capacitor 311 of value C1, and an amplifier 315.
  • the amplifier chosen in this example is an amplifier fast, low noise operation like AD811 of the ANALOG DEVICES Company.
  • the time constant ⁇ 1 of the circuit consisting of components 310 and 311, formed by the product R 1 .C 1 is chosen to be equal to approximately 100 nanoseconds.
  • amplifier 315 is applied to a second filter stage 32 starting with a resistor 320 of value R2, followed by a quick-switching switch 321, and a capacitor 322 of value C2, then an amplifier 323.
  • This amplifier is preferably made at using a fast and low operational amplifier noise, with JFET type inputs.
  • the time constant ⁇ 2 of the circuit consisting of components 320 and 322, formed by the product R 2 .C 2 is in an advantageous embodiment chosen equal to approximately 500 nanoseconds.
  • the lowest time constant ⁇ 1 is placed before the strongest time constant ⁇ 2 , in order to reduce the influence of the noise of the amplifier 315 on the time measurement T.
  • the assembly consisting of the switch 321 and capacitor 322 (C2) defines the circuit for memorization which is, in the example illustrated, a follower-blocker which will be used to fix the amplitude of the signal at a moment defined by the CDE command, after which the amplitude can be measured by an analog-digital converter 4, the digital output of which is applied to the microprocessor 5.
  • Stage 30 not shown in FIG. 1, translates the ECL logic levels and provides improved quality of the slots IMP (t), IMP1 (t) and IMP2 (t).
  • the floors 31 and 32 form the APO amplifier, the low-pass filter FPB and the follower-blocker SB of FIG. 1.
  • the low-pass filter comprises the two stages 31 and 32, and therefore it includes the follower-blocker circuit.
  • the role of the assembly illustrated in FIG. 5 is to store the signals at the output of the filter ⁇ 2 at a chosen time, in order to send it to the analog-digital converter 4.
  • the microprocessor 5 manages the entire device. It therefore generates the RESET, C_IMP and 1 / control signals. 2 , which allows it to be permanently informed of the fact that the measurement in progress, and therefore the signal it receives from the analog-digital converter 4, concerns either a slot IMP (t) corresponding to a true EV step, or either of the calibration slots IMP1 (t) and IMP2 (t).
  • logic unit 2 It is also possible to provide logic unit 2 with a PEV output intended to prevent microprocessor 5 from the arrival of a EV step.
  • the Applicant has observed that, if one places oneself at the neighborhood of the maximum of this response V (T) (or one of the maximum of this response), the amplitude of the output signal of the filter, existing at this time, is a representation of the duration of the IMP slot (t), and this in a relatively independent of the exact waveform of this niche. Indeed, it turns out that, by a suitable choice of the moment filtering parameters, we can obtain a signal at the output of the filter whose amplitude is a practically linear function.
  • the linearity can be further improved by using a filter with two cascaded time constants ⁇ 1 and ⁇ 2 , as described with reference to FIG. 3.
  • T represents the duration of the slot IMP (t)
  • T E is equal to the delay introduced by the timing circuit 228 described with reference to FIG. 2, which circuit 228 ensures by the control signal CDE the piloting of the switch I of the follower-blocker SB, which allows the sampling.
  • the time interval T E can be chosen close to 200 nanoseconds.
  • microprocessor 5 which can for example be type of model INTEL 87C51.
  • the large linearity which is obtained by a suitable choice of device time constants calculates the duration associated with this signal IMP (t) by interpolation between those which correspond to the minimum value IMP1 (t) and to the value maximum IMP2 (t).
  • the Applicant has also observed that there is an effect of noise of the duration measurement T.
  • This calibration operation can be carried out in different ways depending on the applications. We can first perform the calibration from time to time, or even only at the commissioning of the device. It is however preferable perform the calibration at a time closest to the real time, i.e. as close as possible to the measurement T itself. This can be done before the actual measurement said, if the timing is predictable, or after, especially in the opposite case.
  • the invention is here described with use of the response of a low-pass filter, which has the particular advantage to be particularly suitable for incorporating a follower-blocker, the invention could be implemented in using the impulse response of other types of filters, provided their characteristics are suitably chosen.

Claims (12)

  1. Elektronische Vorrichtung zur sehr genauen Zeitmessung eines Ereignisses, die enthält:
    einen Taktgeber (1),
    Mittel (21), die vom Taktgeber getaktet werden, um eine Primär-Zeitmessung (CHR1) des Ereignisses in der Größenordnung einer Periode des Taktgebers durchzuführen,
    logische Mittel (22) zum Erzeugen eines Impulsfensters, das zwischen dem Ereignis und einem Impuls des Taktgebers liegt, dessen Position im Verhältnis zum Ereignis bekannt ist,
    ein Schaltkeis (3) mit einer Zeitkonstanten, der dieses Impulsfenster empfängt, um als Antwort ein elektrisches Signal mit beträchtlich größerer Dauer als der des Impulsfensters zu erzeugen, und
    Mittel (4,5) zur Messung einer physikalischen Größe, die auf dieses elektrische Signal bezogen ist und charakteristisch für die Dauer des Impulsfensters, wodurch die genaue Zeitbestimmung des Ereignisses erreicht wird,
    dadurch gekennzeichnet, daß die logischen Mittel (22) so ausgebildet sind, daß sie ein Impulsfenster erzeugen, dessen Anfang mit dem Ereignis und dessen Ende mit dem k-ten Impuls des Taktgebers nach diesem Anfang zusammenfällt, wobei k eine ganze positive Zahl ist, daß der Shaltkreis (3) mit der Zeitkonstanten einen Filter (FPB) mit ausgewählten Eigenschaften umfaßt und daß die Mittel zur Messung (4, 5) einen ausgewählten Abschnitt der Signal-Antwort des Filters auswerten.
  2. Vorrichtung nach Anspruch 1, dadurch gekennzeichnet, daß der Filter (FPB) eine Zeitkonstante besitzt, die größer als die maximale Dauer des Impulsfensters ist.
  3. Vorrichtung nach Anspruch 2, dadurch gekennzeichnet, daß die Zeitkonstante mindestens fünfmal so lang wie die maximale Dauer des Impulsfensters ist.
  4. Vorrichtung nach Anspruch 3, dadurch gekennzeichnet, daß die Zeitkonstante mindestens zwanzigmal so lang wie die maximale Dauer des Impulsfensters ist.
  5. Vorrichtung nach einem der Ansprüche 1-4, dadurch gekennzeichnet, daß der Filter (FPB) ein Tiefpaßfilter ist, daß der ausgewählte Abschnitt seiner Signal-Antwort im Bereich des Maximums dieser Antwort liegt, und daß die Mittel zur Messung (4, 5) die Amplitude dieses ausgewählten Abschnitts auswerten, die ein Maß für die Länge des Impulsfensters ist.
  6. Vorrichtung nach Anspruch 5, dadurch gekennzeichnet, daß der Tiefpaßfilter (FPB) zwei Zeitkonstanten hat.
  7. Vorrichtung nach einem der Ansprüche 1-6, dadurch gekennzeichnet, daß sie ein Speicherelement (SB) beinhaltet, das am Ende einer gewählten Zeit betätigt wird, die relativ zum Taktimpuls des Taktgebers das Ende des Impulsfensters bestimmt.
  8. Vorrichtung nach den Ansprüchen 6 und 7, dadurch gekennzeichnet, daß der Tiefpaßfilter (FPB) zwei aufeinanderfolgende Stufen (31, 32) aufweist, die jeweils die eine der beiden Zeitkonstanten aufweisen, und daß die zweite Stufe (32) das Speicherelement (SB) beinhaltet.
  9. Vorrichtung nach einem der Ansprüche 7 und 8, dadurch gekennzeichnet, daß das Speicherelement (SB) eine Folge- und Halteschaltung (follow and hold) (321,322) ist.
  10. Vorrichtung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß sie Mittel (23) umfaßt, die zur wiederholten Erzeugung von Scheinereignissen zur Kalibrierung dienen.
  11. Vorrichtung nach Anspruch 10, dadurch gekennzeichnet, daß wenigstens einige der Schein-Ereignisse der maximalen und minimalen Länge des primären Impulsfensters entsprechen.
  12. Vorrichtung nach einem der Ansprüche 10 oder 11, dadurch gekennzeichnet, daß jedes Scheinereignis M-mal wiederholt wird, und daß ein Durchschnitt dieser M-mal wiederholten Scheinereignisse gebildet wird, um jede Ereignismessung zu kalibrieren.
EP96400306A 1995-02-22 1996-02-14 Sehr genaue Chronometrierung eines Vorfalls Expired - Lifetime EP0729082B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9502058 1995-02-22
FR9502058A FR2730830B1 (fr) 1995-02-22 1995-02-22 Chronometrie electronique tres precise d'un evenement

Publications (2)

Publication Number Publication Date
EP0729082A1 EP0729082A1 (de) 1996-08-28
EP0729082B1 true EP0729082B1 (de) 1999-01-13

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EP96400306A Expired - Lifetime EP0729082B1 (de) 1995-02-22 1996-02-14 Sehr genaue Chronometrierung eines Vorfalls

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US (1) US5812625A (de)
EP (1) EP0729082B1 (de)
AT (1) ATE175785T1 (de)
CA (1) CA2169792C (de)
DE (1) DE69601315T2 (de)
FR (1) FR2730830B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2241167T3 (es) * 1997-10-16 2005-10-16 The University Of Manchester Circuito temporizador.
US5958020A (en) * 1997-10-29 1999-09-28 Vlsi Technology, Inc. Real time event determination in a universal serial bus system
CN109643142B (zh) * 2017-08-04 2022-08-02 深圳市汇顶科技股份有限公司 定时方法、时钟设备和终端设备
CN111708059B (zh) * 2020-06-24 2023-08-08 中国科学院国家天文台长春人造卫星观测站 一种激光时间传递处理方法、系统、存储介质、装置及应用

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1520487A (fr) * 1967-01-24 1968-04-12 Onera (Off Nat Aerospatiale) Procédé et appareil de chronométrie
DE1591850A1 (de) * 1967-08-24 1970-10-01 Bosch Gmbh Robert Geraet zum Messen der Impulsdauer
DE2855819C3 (de) * 1977-12-26 1981-05-21 Takeda Riken Kogyo K.K., Tokyo Zeitintervall-Meßeinrichtung
FR2492563B1 (fr) * 1980-10-20 1986-08-14 Dassault Electronique Dispositif pour le comptage d'impulsions de frequence elevee
FR2493553A1 (fr) * 1980-10-31 1982-05-07 Dassault Electronique Appareillage pour la datation precise d'un evenement par rapport a une reference de temps
US5214680A (en) * 1991-11-01 1993-05-25 Hewlett-Packard Company CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration
US5228066A (en) * 1992-04-22 1993-07-13 Digital Equipment Corporation System and method for measuring computer system time intervals
DE4313780C1 (de) * 1993-04-27 1994-07-28 Daimler Benz Ag Verfahren und Vorrichtung für die Zählung von Zeittaktimpulsen zur Periodendauermessung
JP3125562B2 (ja) * 1994-03-10 2001-01-22 富士電機株式会社 クロック発生回路

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Publication number Publication date
EP0729082A1 (de) 1996-08-28
FR2730830A1 (fr) 1996-08-23
FR2730830B1 (fr) 1997-06-06
DE69601315D1 (de) 1999-02-25
CA2169792C (en) 2005-10-04
US5812625A (en) 1998-09-22
DE69601315T2 (de) 1999-06-02
CA2169792A1 (en) 1996-08-23
ATE175785T1 (de) 1999-01-15

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