EP0729082A1 - Sehr genaue Chronometrierung eines Vorfalls - Google Patents

Sehr genaue Chronometrierung eines Vorfalls Download PDF

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Publication number
EP0729082A1
EP0729082A1 EP96400306A EP96400306A EP0729082A1 EP 0729082 A1 EP0729082 A1 EP 0729082A1 EP 96400306 A EP96400306 A EP 96400306A EP 96400306 A EP96400306 A EP 96400306A EP 0729082 A1 EP0729082 A1 EP 0729082A1
Authority
EP
European Patent Office
Prior art keywords
event
time
time slot
clock
duration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96400306A
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English (en)
French (fr)
Other versions
EP0729082B1 (de
Inventor
Thierry Potier
Michel Geesen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Dassault Electronique SA
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Publication date
Application filed by Dassault Electronique SA filed Critical Dassault Electronique SA
Publication of EP0729082A1 publication Critical patent/EP0729082A1/de
Application granted granted Critical
Publication of EP0729082B1 publication Critical patent/EP0729082B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time

Definitions

  • chronometry is the dating of an event in relation to a time reference.
  • This timing is known electronically, but becomes particularly difficult when very high precision is required, as is the case, for example, with the timing of the arrival of laser beams, for the purpose of measuring distance, or other time-based operations, such as synchronizing remote clocks.
  • an event is a transition of an electrical signal detecting the arrival of the laser beam, from a low level to a high level.
  • the starting point for chronometry is assumed to be known.
  • the present invention aims to do better, in particular by going below one hundred, or better still the ten picoseconds.
  • the time slot begins with the event, and ends with the next clock pulse.
  • the time constant circuit is a double integrator, using the fast charge of a capacitor during the time slot, followed by a slow discharge.
  • the discharge time defines a second time slot.
  • the circuit can be arranged so that the duration of the second time slot is increased according to a known law, substantially monotonous, compared to the duration of the first time slot (hence the time stretching).
  • a secondary counter measures the duration of the second time slot, which provides the fine secondary timing of the event, preferably with respect to the same clock.
  • the present invention proposes a better solution.
  • the logic means are arranged to produce a time slot which begins at a time linked to the event and ends in a clock pulse which is at least the second encountered after its start. Consequently, the duration of the time slot becomes greater than or equal to the period T0 of the clock. It is between T0 and (k + 1) .T0, with k at least equal to 1.
  • the time constant circuit is a filter of selected characteristics, having a time constant greater, in principle much greater, than the nominal duration of the time slot.
  • the measurement means operate on a selected part of the response of the filter to the time slot.
  • the filter is a low-pass filter
  • the chosen part of its response is in the vicinity of the maximum of this response, and it has been observed that the amplitude of this part is then representative of the duration of the time slot.
  • the circuit includes a clock 1 operating at a frequency F 0 which is for example 200 MHz.
  • This clock is of a suitable stability for the desired precision, which is considered here as accessible to a person skilled in the art.
  • the signal delivered by this clock 1 serves as the first input signal to a unit 2 grouping together logic circuits.
  • This unit 2 receives on a second input EV, a second electrical signal, in step.
  • This step EV signal represents the event to be dated.
  • This step represents for example the rise time of a photodetector receiving a laser beam.
  • the present invention aims to achieve a temporal precision of 2 to 3 picoseconds in quadratic mean value (RMS), for an electrical step signal whose rise time is 200 picoseconds.
  • RMS quadratic mean value
  • the logic circuits grouped in unit 2 are of ECL technology.
  • FIG. 2 In which the logic components shown diagrammatically by squares are of the "flip-flop" type.
  • the counting starts at an instant TRF, also defined by a step signal or a pulse validating the counter 210.
  • the counting stops at the moment when a signal representative of the step EV is applied to the second PRE input of counter 210, after having passed through the components FF1, CL3, FF3 and FF2.
  • the state of the counter is stored, for example in a register 212, which is then capable of providing a digital signal CHR1, representing the primary chronometry, in principle unambiguous but whose precision is limited by the period d 'clock T 0 .
  • the mode of transfer of the state of the counter 210 in the register 212 can depend on whether the counter 210 is synchronous or asynchronous. Information to this effect can be found in FR-2 492 563, already cited.
  • the step EV to date (third line from the top) occurs during the Nth state of the counter 210 from the reference time TRF.
  • the logic unit 2 also includes a stage 22, the function of which is to generate a time slot IMP (t) (more precisely an electrical signal forming a time slot), linked to the time difference between the event EV and a pulse clock position known relative to this event.
  • IMP (t) results from a logic operation, performed by the logic component CL1, between the step EV from FF1 and the signal from the third flip-flop component FF3, representative of the position clock pulses delivered by the clock 1.
  • IMP (t) is shown on the last line of Figure 3.
  • the clock pulse of known position corresponds to the N + 2 (th) pulse of clock 1, that is to say the second clock pulse following the EV step.
  • the time slot, noted IMP (t) the time slot, noted IMP (t).
  • FF3 also delivers on a second output, a signal CDE0 whose rising edge coincides with the end of the time slot IMP (t).
  • This pulse CDE0 is applied to the first ARM input of a digital timing circuit 228 capable of providing a time delay T E , and whose time base is the clock signal 1 applied to its second input CLK, which provides at the output of the timing circuit 228 a signal CDE which will serve to control the sampling of the event, which will be described later.
  • the unit 2 also comprises a sub-assembly 23, to generate two calibration slots denoted IMP1 (t) and IMP2 (t), of duration T 0 and 2T 0 respectively .
  • This sub-assembly 23 more particularly comprises the two flip-flop components FF4 and FF5, the respective outputs of which are coupled by a second logic component CL2 which delivers the result of its logic operations to FF3.
  • control signals C_IMP, 1/2 and RESET are derived from a microprocessor 5 which will be described later.
  • the slots IMP1 (t) and IMP2 (t) make it possible to provide a framework for the duration of the slot IMP (t).
  • the slot signal IMP1 (t) ( Figure 4B) corresponds to the minimum duration of IMP (t), which is the period T 0 of the clock 1.
  • the slot signal IMP2 (t) ( Figure 4C) corresponds to the maximum duration of IMP (t), which is the period 2T 0 .
  • the three signals IMP (t), IMP1 (t) or IMP2 (t) are available on the same channel, the sequencing being managed by the microprocessor 5 which will be discussed later.
  • the slot delivered at the output of the logic unit ECL 2 is applied to an amplifier APO, followed by a low-pass filter FPB, then by a storage circuit SB, which is preferably a sampler-blocker or a follower - blocker.
  • the slots are first applied to a shaping circuit 30, consisting of a clipping amplifier having a current output.
  • a shaping circuit 30 consisting of a clipping amplifier having a current output.
  • a differential amplifier with transistors is used.
  • stage 30 The output of stage 30 is applied to a first filtering stage 31. It comprises a resistor 310 of value R1, a capacitor 311 of value C1, and an amplifier 315.
  • the amplifier chosen in this example is a fast operational amplifier and low noise, like the AD811 model from ANALOG DEVICES.
  • the time constant ⁇ 1 of the circuit consisting of components 310 and 311, formed by the product R 1 .C 1 is chosen to be equal to approximately 100 nanoseconds.
  • the output of the amplifier 315 is applied to a second filtering stage 32 starting with a resistor 320 of value R2, followed by a fast switching switch 321, and of a capacitor 322 of value C2, then of an amplifier 323.
  • This amplifier is preferably produced using a fast, low-noise operational amplifier provided with JFET type inputs.
  • the time constant ⁇ 2 of the circuit consisting of components 320 and 322, formed by the product R 2 .C 2 is in an advantageous embodiment chosen equal to approximately 500 nanoseconds.
  • the lowest time constant ⁇ 1 is placed before the strongest time constant ⁇ 2 , in order to reduce the influence of the noise of the amplifier 315 on the time measurement T.
  • the assembly consisting of the switch 321 and the capacitor 322 (C2) defines the storage circuit which is, in the example illustrated, a follower-blocker which will serve to fix the amplitude of the signal to a moment defined by the CDE command, after which the amplitude can be measured by an analog-digital converter 4, the digital output of which is applied to the microprocessor 5.
  • Stage 30, not shown in FIG. 1, translates the logic levels ECL and provides an improvement in the quality of the slots IMP (t), IMP1 (t) and IMP2 (t).
  • the stages 31 and 32 form the amplifier APO, the low-pass filter FPB and the follower-blocker SB of FIG. 1.
  • the low-pass filter comprises the two stages 31 and 32, and therefore it includes the follower-blocker circuit.
  • the role of the assembly illustrated in FIG. 5 is to store the signals at the output of the filter ⁇ 2 at a chosen time, in order to send it to the analog-digital converter 4.
  • the microprocessor 5 manages the entire device. It therefore generates the RESET, C_IMP and 1 / control signals. 2 ⁇ , which allows it to be permanently informed of the fact that the measurement in progress, and therefore the signal it receives from the analog-digital converter 4, concerns either a slot IMP (t) corresponding to a true EV step, or either of the calibration slots IMP1 (t) and IMP2 (t).
  • the Applicant has observed that, if one places oneself near the maximum of this response V (T) (or one of the maxima of this response), the amplitude of the output signal of the filter, existing at this moment, constitutes a representation of the duration of the slot IMP (t), and this in a manner relatively independent of the exact waveform of this slot. Indeed, it turns out that, by a suitable choice of the sampling instant and the filtering parameters, it is possible to obtain a signal at the output of the filter whose amplitude is a practically linear function.
  • the linearity can be further improved by using a filter with two cascaded time constants ⁇ 1 and ⁇ 2 , as described with reference to FIG. 3.
  • T represents the duration of the slot IMP (t)
  • T E is equal to the delay introduced by the timing circuit 228 described with reference to FIG. 2, which circuit 228 ensures by the control signal CDE the piloting of the switch I of the follower-blocker SB, which allows the sampling.
  • the time interval T E can be chosen close to 200 nanoseconds.
  • the output of the converter 4 is applied to the microprocessor 5, which can for example be of the type of the 87C51 model from the company INTEL.
  • the Applicant has also observed that there is an effect of the noise of the measurement of the duration T.
  • This calibration operation can be carried out in different ways depending on the applications. You can first perform the calibration from time to time, or even only when the device is put into service. It is however preferable to carry out the calibration at a time closest to real time, that is to say as close as possible to the measurement. T itself. This can be done before the actual measurement, if the time is foreseeable, or after, especially in the opposite case.
  • the invention is described here with the use of the response of a low-pass filter, which has the particular advantage of being particularly suitable for incorporating a follower-blocker, the invention could be implemented implemented using the impulse response of other types of filters, provided that their characteristics are suitably chosen.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Steroid Compounds (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Emulsifying, Dispersing, Foam-Producing Or Wetting Agents (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)
EP96400306A 1995-02-22 1996-02-14 Sehr genaue Chronometrierung eines Vorfalls Expired - Lifetime EP0729082B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9502058A FR2730830B1 (fr) 1995-02-22 1995-02-22 Chronometrie electronique tres precise d'un evenement
FR9502058 1995-02-22

Publications (2)

Publication Number Publication Date
EP0729082A1 true EP0729082A1 (de) 1996-08-28
EP0729082B1 EP0729082B1 (de) 1999-01-13

Family

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EP96400306A Expired - Lifetime EP0729082B1 (de) 1995-02-22 1996-02-14 Sehr genaue Chronometrierung eines Vorfalls

Country Status (6)

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US (1) US5812625A (de)
EP (1) EP0729082B1 (de)
AT (1) ATE175785T1 (de)
CA (1) CA2169792C (de)
DE (1) DE69601315T2 (de)
FR (1) FR2730830B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1023644B1 (de) * 1997-10-16 2005-04-13 The University of Manchester Zeitmessschaltung
US5958020A (en) * 1997-10-29 1999-09-28 Vlsi Technology, Inc. Real time event determination in a universal serial bus system
WO2019024064A1 (zh) * 2017-08-04 2019-02-07 深圳市汇顶科技股份有限公司 定时方法、时钟设备和终端设备
CN111708059B (zh) * 2020-06-24 2023-08-08 中国科学院国家天文台长春人造卫星观测站 一种激光时间传递处理方法、系统、存储介质、装置及应用

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1520487A (fr) * 1967-01-24 1968-04-12 Onera (Off Nat Aerospatiale) Procédé et appareil de chronométrie
FR1578540A (de) * 1967-08-24 1969-08-14
DE2855819A1 (de) * 1977-12-26 1979-06-28 Takeda Riken Ind Co Ltd Zeitintervall-messeinrichtung

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2492563B1 (fr) * 1980-10-20 1986-08-14 Dassault Electronique Dispositif pour le comptage d'impulsions de frequence elevee
FR2493553A1 (fr) * 1980-10-31 1982-05-07 Dassault Electronique Appareillage pour la datation precise d'un evenement par rapport a une reference de temps
US5214680A (en) * 1991-11-01 1993-05-25 Hewlett-Packard Company CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration
US5228066A (en) * 1992-04-22 1993-07-13 Digital Equipment Corporation System and method for measuring computer system time intervals
DE4313780C1 (de) * 1993-04-27 1994-07-28 Daimler Benz Ag Verfahren und Vorrichtung für die Zählung von Zeittaktimpulsen zur Periodendauermessung
JP3125562B2 (ja) * 1994-03-10 2001-01-22 富士電機株式会社 クロック発生回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1520487A (fr) * 1967-01-24 1968-04-12 Onera (Off Nat Aerospatiale) Procédé et appareil de chronométrie
FR1578540A (de) * 1967-08-24 1969-08-14
DE2855819A1 (de) * 1977-12-26 1979-06-28 Takeda Riken Ind Co Ltd Zeitintervall-messeinrichtung

Also Published As

Publication number Publication date
ATE175785T1 (de) 1999-01-15
FR2730830B1 (fr) 1997-06-06
DE69601315D1 (de) 1999-02-25
FR2730830A1 (fr) 1996-08-23
CA2169792A1 (en) 1996-08-23
DE69601315T2 (de) 1999-06-02
EP0729082B1 (de) 1999-01-13
US5812625A (en) 1998-09-22
CA2169792C (en) 2005-10-04

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