EP0729082A1 - Very precise chrono-measurement of an event - Google Patents

Abstract

The chronometer comprises a clock (1), providing (21) pulses, as a primary event chronometer (CHR1) of close time periods. Logic circuits (22) produce a timing waveform, connecting the time between an event and a known clock impulse. A constant timing circuit (3) receives this timing waveform and produces an electrical signal much longer than the timing wave. This signal is measured (4,5), representing the timed waveform duration, providing a fine measurement of the event time. The logic circuits produce the timing waveform, its start coinciding with the event and ending at "k" clock impulses after the start, with "k" being a positive integer. The constant timing circuit comprises a filter (FAB), the measurement resulting from its response.

Description

One of the aspects of chronometry is the dating of an event in relation to a time reference.

This timing is known electronically, but becomes particularly difficult when very high precision is required, as is the case, for example, with the timing of the arrival of laser beams, for the purpose of measuring distance, or other time-based operations, such as synchronizing remote clocks.

We consider here that an event is a transition of an electrical signal detecting the arrival of the laser beam, from a low level to a high level. The starting point for chronometry is assumed to be known.

The patent specifications FR-B-2 492 563 and more particularly FR-B-2 493 553 have described solutions with which the conceivable precision drops below the nanosecond, as well as various applications where this precision is desired.

The present invention aims to do better, in particular by going below one hundred, or better still the ten picoseconds.

• une horloge formant référence de temps,
• des moyens pulsés par l'horloge, pour effectuer une chronométrie primaire de l'événement, à une période d'horloge près,
• des moyens logiques pour engendrer un créneau temporel, lié à l'écart temporel entre l'événement et une impulsion d'horloge de position connue par rapport à l'événement,
• un circuit à constante de temps, recevant ce créneau temporel, pour engendrer en réponse un signal électrique de durée fortement supérieure à celle du créneau temporel, et
• des moyens de mesure d'une grandeur physique relative à ce signal électrique, et représentative de la durée du créneau temporel, permettant par là une chronométrie secondaire de l'événement.

In known manner, the proposed device comprises:

• a clock forming a time reference,
• means pulsed by the clock, to perform a primary chronometry of the event, to within a clock period,
• logic means for generating a time slot, linked to the time difference between the event and a clock pulse of known position with respect to the event,
• a time constant circuit, receiving this time slot, in order to generate in response an electrical signal of duration considerably greater than that of the time slot, and
• means for measuring a physical quantity relating to this electrical signal, and representative of the duration of the time slot, thereby enabling secondary timing of the event.

According to document FR-B-2 493 553, the time slot begins with the event, and ends with the next clock pulse. The time constant circuit is a double integrator, using the fast charge of a capacitor during the time slot, followed by a slow discharge. The discharge time defines a second time slot. The circuit can be arranged so that the duration of the second time slot is increased according to a known law, substantially monotonous, compared to the duration of the first time slot (hence the time stretching). A secondary counter then measures the duration of the second time slot, which provides the fine secondary timing of the event, preferably with respect to the same clock.

The present invention proposes a better solution.

First of all, the logic means are arranged to produce a time slot which begins at a time linked to the event and ends in a clock pulse which is at least the second encountered after its start. Consequently, the duration of the time slot becomes greater than or equal to the period T0 of the clock. It is between T0 and (k + 1) .T0, with k at least equal to 1.

Then, the time constant circuit is a filter of selected characteristics, having a time constant greater, in principle much greater, than the nominal duration of the time slot.

Finally, the measurement means operate on a selected part of the response of the filter to the time slot.

Preferably, the filter is a low-pass filter, the chosen part of its response is in the vicinity of the maximum of this response, and it has been observed that the amplitude of this part is then representative of the duration of the time slot.

• la figure 1 est le schéma électrique simplifié d'un mode de réalisation de la présente invention;
• la figure 2 est un schéma détaillé de l'unité logique 2 de la figure 1;
• la figure 3 illustre quatre diagrammes temporels qui se correspondent et sont utiles à la compréhension de la figure 1;
• les figures 4A à 4C sont trois groupes de diagrammes temporels permettant de mieux comprendre la calibration du dispositif selon l'invention;
• la figure 5 est un schéma de principe détaillé du groupe d'éléments FPB, APO, et SB correspondant au mode de réalisation de la figure 1; et
• la figure 6 est un diagramme temporel permettant de mieux comprendre le fonctionnement du dispositif selon l'invention, à propos du schéma de la figure 5.

Other characteristics and advantages of the invention will appear on examining the detailed description below, as well as the appended drawings, in which:

• Figure 1 is the simplified electrical diagram of an embodiment of the present invention;
• Figure 2 is a detailed diagram of the logic unit 2 of Figure 1;
• FIG. 3 illustrates four time diagrams which correspond and are useful for the understanding of FIG. 1;
• FIGS. 4A to 4C are three groups of time diagrams making it possible to better understand the calibration of the device according to the invention;
• Figure 5 is a detailed block diagram of the group of elements FPB, APO, and SB corresponding to the embodiment of Figure 1; and
• FIG. 6 is a time diagram making it possible to better understand the operation of the device according to the invention, with reference to the diagram of FIG. 5.

The attached drawings contain many elements of a certain character, which it is difficult to define completely by the text. Consequently, they are therefore an integral part of the description, and may contribute to the definition of the invention.

It has already been indicated that the invention relates to very fine chronometry. At the desired scale, under the nanosecond, we will only be able to date an event from a determined reference instant, better perceptible to humans than the order of magnitude of the nanosecond.

In FIG. 1, the circuit includes a clock 1 operating at a frequency F ₀ which is for example 200 MHz. This clock is of a suitable stability for the desired precision, which is considered here as accessible to a person skilled in the art. The signal delivered by this clock 1 serves as the first input signal to a unit 2 grouping together logic circuits.

This unit 2 receives on a second input EV, a second electrical signal, in step. This step EV signal represents the event to be dated. This step represents for example the rise time of a photodetector receiving a laser beam.

In a particularly efficient embodiment, the present invention aims to achieve a temporal precision of 2 to 3 picoseconds in quadratic mean value (RMS), for an electrical step signal whose rise time is 200 picoseconds.

In view of the precision sought, it is necessary to use logic electronic circuits which switch very quickly. To this end, the logic circuits grouped in unit 2 are of ECL technology.

To describe unit 2 in more detail, reference is made to FIG. 2, in which the logic components shown diagrammatically by squares are of the "flip-flop" type.

For the reason already indicated, a primary count is first carried out. To this end, the part 21 of the unit 2 comprises a counter 210, receiving on a first input CLK the pulses of frequency F ₀ and of period T ₀ = 1 / F ₀ , from clock 1. The counting starts at an instant TRF, also defined by a step signal or a pulse validating the counter 210. The counting stops at the moment when a signal representative of the step EV is applied to the second PRE input of counter 210, after having passed through the components FF1, CL3, FF3 and FF2.

At a suitable time, the state of the counter is stored, for example in a register 212, which is then capable of providing a digital signal CHR1, representing the primary chronometry, in principle unambiguous but whose precision is limited by the period d 'clock T ₀ . The mode of transfer of the state of the counter 210 in the register 212 can depend on whether the counter 210 is synchronous or asynchronous. Information to this effect can be found in FR-2 492 563, already cited.

What has just been described corresponds to the first four lines of the timing diagram of FIG. 3. In the illustrated example, the step EV to date (third line from the top) occurs during the Nth state of the counter 210 from the reference time TRF. The numerical value CHR1 taken by the synchronous command PRE and N or N + 1 according to the implementation of part 21.

The logic unit 2 also includes a stage 22, the function of which is to generate a time slot IMP (t) (more precisely an electrical signal forming a time slot), linked to the time difference between the event EV and a pulse clock position known relative to this event. IMP (t) results from a logic operation, performed by the logic component CL1, between the step EV from FF1 and the signal from the third flip-flop component FF3, representative of the position clock pulses delivered by the clock 1. IMP (t) is shown on the last line of Figure 3.

In this example, the clock pulse of known position corresponds to the N + 2 (th) pulse of clock 1, that is to say the second clock pulse following the EV step. We thus obtain the time slot, noted IMP (t).

But, FF3 also delivers on a second output, a signal CDE0 whose rising edge coincides with the end of the time slot IMP (t). This pulse CDE0 is applied to the first ARM input of a digital timing circuit 228 capable of providing a time delay T _E , and whose time base is the clock signal 1 applied to its second input CLK, which provides at the output of the timing circuit 228 a signal CDE which will serve to control the sampling of the event, which will be described later.

As of the generation of the slot IMP (t) by an EV step, the Q output of FF1 is maintained at 0 thanks to the memory of FF2, this having the effect of ignoring all the subsequent EV steps as long as a command RESET = 1 has not been sent.

Preferably, the unit 2 also comprises a sub-assembly 23, to generate two calibration slots denoted IMP1 (t) and IMP2 (t), of duration T ₀ and 2T _{0 respectively} . This sub-assembly 23 more particularly comprises the two flip-flop components FF4 and FF5, the respective outputs of which are coupled by a second logic component CL2 which delivers the result of its logic operations to FF3.

:

• si 1/ $\overline{\text{2}}$
  
  = 1 : la sortie Q de FF5 est maintenue à 0 et IMP1(t) est généré par FF3, FF4, CL2 et CL3 via CL1.
• Si 1/ $\overline{\text{2}}$
  
  = 0 : FF5 est active et le créneau double IMP2(t) est généré par FF3, FF4, FF5, CL2 et CL3 via CL1.

The synthesis of the calibration slots takes place when the EV input is deactivated, i.e. after an IMP slot (t) and before the RESET command = 1 (the Q outputs of FF1 and FF2 are then 0) . This synthesis is controlled by a rising edge of the signal C_IMP and the choice of IMP1 (t) or IMP2 (t) depends on the state of the signal 1 / $\overline{\text{2}}$

:

• if 1 / $\overline{\text{2}}$
  
  = 1: the Q output of FF5 is maintained at 0 and IMP1 (t) is generated by FF3, FF4, CL2 and CL3 via CL1.
• If 1 / $\overline{\text{2}}$
  
  = 0: FF5 is active and the double IMP2 (t) slot is generated by FF3, FF4, FF5, CL2 and CL3 via CL1.

The control signals C_IMP, 1/2 and RESET are derived from a microprocessor 5 which will be described later.

As indicated in FIG. 4, the slots IMP1 (t) and IMP2 (t) make it possible to provide a framework for the duration of the slot IMP (t).

Thus, the slot signal IMP1 (t) (Figure 4B) corresponds to the minimum duration of IMP (t), which is the period T ₀ of the clock 1. Furthermore, the slot signal IMP2 (t) (Figure 4C) corresponds to the maximum duration of IMP (t), which is the period 2T ₀ .

Returning now to FIG. 1, the three signals IMP (t), IMP1 (t) or IMP2 (t) are available on the same channel, the sequencing being managed by the microprocessor 5 which will be discussed later.

The slot delivered at the output of the logic unit ECL 2 is applied to an amplifier APO, followed by a low-pass filter FPB, then by a storage circuit SB, which is preferably a sampler-blocker or a follower - blocker.

This filter, this amplifier and this storage circuit are described in more detail in FIG. 5.

The slots are first applied to a shaping circuit 30, consisting of a clipping amplifier having a current output. For example, a differential amplifier with transistors is used.

The output of stage 30 is applied to a first filtering stage 31. It comprises a resistor 310 of value R1, a capacitor 311 of value C1, and an amplifier 315. The amplifier chosen in this example is a fast operational amplifier and low noise, like the AD811 model from ANALOG DEVICES.

In an advantageous embodiment, the time constant τ ₁ of the circuit consisting of components 310 and 311, formed by the product R ₁ .C ₁ , is chosen to be equal to approximately 100 nanoseconds.

The output of the amplifier 315 is applied to a second filtering stage 32 starting with a resistor 320 of value R2, followed by a fast switching switch 321, and of a capacitor 322 of value C2, then of an amplifier 323. This amplifier is preferably produced using a fast, low-noise operational amplifier provided with JFET type inputs.

The time constant τ ₂ of the circuit consisting of components 320 and 322, formed by the product R ₂ .C ₂ , is in an advantageous embodiment chosen equal to approximately 500 nanoseconds.

In this arrangement, the lowest time constant τ _{1 is placed} before the strongest time constant τ ₂ , in order to reduce the influence of the noise of the amplifier 315 on the time measurement T.

We also observe that the assembly consisting of the switch 321 and the capacitor 322 (C2) defines the storage circuit which is, in the example illustrated, a follower-blocker which will serve to fix the amplitude of the signal to a moment defined by the CDE command, after which the amplitude can be measured by an analog-digital converter 4, the digital output of which is applied to the microprocessor 5.

Stage 30, not shown in FIG. 1, translates the logic levels ECL and provides an improvement in the quality of the slots IMP (t), IMP1 (t) and IMP2 (t). The stages 31 and 32 form the amplifier APO, the low-pass filter FPB and the follower-blocker SB of FIG. 1. In fact in the assembly described, the low-pass filter comprises the two stages 31 and 32, and therefore it includes the follower-blocker circuit.

Of course, one could use a sampler-blocker instead of the follower-blocker, but that would complicate the assembly.

The role of the assembly illustrated in FIG. 5 is to store the signals at the output of the filter τ ₂ at a chosen time, in order to send it to the analog-digital converter 4. One could also use an analog-digital converter of the type FLASH which does not require such memorization but whose resolution remains limited.

In addition, some analog-to-digital converters already have an internal sampler-blocker, which could simplify assembly. However, given the precision required, these hardly support the impulse nature of the signals to be processed.

, ce qui lui permet d'être informé en permanence du fait que la mesure en cours, et donc le signal qu'il reçoit du convertisseur analogique-numérique 4, concerne soit un créneau IMP(t) correspondant à un véritable échelon EV, soit l'un ou l'autre des créneaux de calibration IMP1(t) et IMP2(t).The microprocessor 5 manages the entire device. It therefore generates the RESET, C_IMP and 1 / control signals. $\overline{\text{2}}$

, which allows it to be permanently informed of the fact that the measurement in progress, and therefore the signal it receives from the analog-digital converter 4, concerns either a slot IMP (t) corresponding to a true EV step, or either of the calibration slots IMP1 (t) and IMP2 (t).

It is also possible to provide the logic unit 2 with a PEV output intended to prevent the microprocessor 5 from the arrival of an EV step.

Figures 1 and 6 will better understand the operating mechanism of the device according to the invention.

The IMP (t) pulse is very brief. Its maximum duration is at most equal to twice the period T ₀ of clock 1, ie T _max = 10 nanoseconds (F ₀ = 200 Mhz).

The Applicant has observed that, when a slot is thus applied to a low-pass filter whose time constant result is much longer than the duration of the slot, the filter output signal approaches its so-called "impulse" response, which is considerably stretched over time, as shown by the dashed curve V (t) in Figure 6. In specialist jargon, an impulse response is obtained when the filter receives an input signal whose mathematical representation can be assimilated to a "Dirac".

In addition, the Applicant has observed that, if one places oneself near the maximum of this response V (T) (or one of the maxima of this response), the amplitude of the output signal of the filter, existing at this moment, constitutes a representation of the duration of the slot IMP (t), and this in a manner relatively independent of the exact waveform of this slot. Indeed, it turns out that, by a suitable choice of the sampling instant and the filtering parameters, it is possible to obtain a signal at the output of the filter whose amplitude is a practically linear function.

The greater the time constant resulting from the filtering compared to the maximum duration of the slot applicable to the input of the filter, the better the linearity.

The linearity can be further improved by using a filter with two cascaded time constants τ ₁ and τ ₂ , as described with reference to FIG. 3.

In FIG. 6, T represents the duration of the slot IMP (t), while T _E is equal to the delay introduced by the timing circuit 228 described with reference to FIG. 2, which circuit 228 ensures by the control signal CDE the piloting of the switch I of the follower-blocker SB, which allows the sampling.

In the embodiment described, the time interval T _E , can be chosen close to 200 nanoseconds.

After obtaining the stored signal VH (t), its analog-digital conversion is carried out using the converter 4 which is for example of the type of the AD779 model from the company ANALOG DEVICES.

The same processing is carried out on the calibration pulses IMP1 (t) and IMP2 (t), which makes it possible to obtain the measured values VH1 (t) and VH2 (t) of the response of the filter for the time slots respectively minimum and maximum (T ₀ and 2T ₀ ).

As previously indicated, the output of the converter 4 is applied to the microprocessor 5, which can for example be of the type of the 87C51 model from the company INTEL.

When a time slot IMP (t) to be measured comes into play, the great linearity obtained by a suitable choice of the time constants of the device makes it possible to calculate the duration associated with this signal IMP (t) by interpolation between those which correspond to the minimum value IMP1 (t) and the maximum value IMP2 (t).

The Applicant has also observed that there is an effect of the noise of the measurement of the duration T.

To reduce this noise, the application of the calibration slots IMP1 (t) and IMP2 (t) is repeated M times, and the average values for each of them are determined. It has been observed that these mean values give satisfactory results when M is equal to 4 or more. Values greater than 8 do not seem to provide any significant additional improvements.

This calibration operation can be carried out in different ways depending on the applications. You can first perform the calibration from time to time, or even only when the device is put into service. It is however preferable to carry out the calibration at a time closest to real time, that is to say as close as possible to the measurement. T itself. This can be done before the actual measurement, if the time is foreseeable, or after, especially in the opposite case.

Of course, the present invention is not limited to the embodiment described.

First of all, we can always extend the duration of the time slot IMP (t), that is to say that instead of being in the interval of durations which goes from T ₀ to 2T ₀ , we can go from 2T ₀ to 3T ₀ or from 3T ₀ to 4T ₀ .

Then, although the invention is described here with the use of the response of a low-pass filter, which has the particular advantage of being particularly suitable for incorporating a follower-blocker, the invention could be implemented implemented using the impulse response of other types of filters, provided that their characteristics are suitably chosen.

Finally, it is also possible to generate a third calibration window of duration 3T _{0 in} order to perform a parabolic interpolation making it possible to minimize the effect of second order residual non-linearities.

Claims (12)

Electronic device for very precise timing of an event, of the type comprising: - a clock (1), means (21), pulsed by the clock, for performing primary chronometry (CHR1) of the event, to within a clock period, - logic means (22) for generating a time slot, linked to the time difference between the event and a clock pulse of known position with respect to the event, - a time constant circuit (3), receiving this time slot, in order to generate in response an electrical signal of duration considerably greater than that of the time slot, and means (4,5) for measuring a physical quantity relating to this electrical signal, and representative of the duration of the time slot, thereby allowing fine timing of the event, characterized in that the logic means (22) are arranged to produce a time slot whose start coincides with the event and whose end occurs at the k-th clock pulse after this start, with k positive integer, that the time constant circuit (3) comprises a filter (FPB) of selected characteristics, and in that the measuring means (4,5) operate on a selected part of the response of the filter. Device according to claim 1, characterized in that the filter (FPB) has a time constant greater than the maximum duration of the time slot. Device according to claim 2, characterized in that the time constant is at least equal to 5 times the maximum duration of the time slot. Device according to claim 3, characterized in that the time constant is at least equal to 20 times the maximum duration of the time slot. Device according to one of Claims 1 to 4, characterized in that the filter (FPB) is a low-pass filter, in that the chosen part of its response is in the vicinity of the maximum of this response, and in that the measuring means (4,5) operate on the amplitude of this selected part, which is representative of the duration of the time slot. Device according to claim 5, characterized in that the low-pass filter (FPB) has a double time constant. Device according to one of claims 1 to 6, characterized in that it comprises a storage member (SB) controlled after a selected time, with respect to the clock pulse which marks the end of the time slot . Device according to Claims 6 and 7, taken in combination, characterized in that the low-pass filter (FPB) comprises two successive stages (31,32) having the two time constants respectively, and in that the second stage (32 ) contains the storage device (SB). Device according to one of claims 7 and 8, characterized in that the memory member (SB) is a follower-blocker (321,322). Device according to one of the preceding claims, characterized in that the device comprises means (23) capable of repeatedly generating dummy calibration events, for said measurement. Device according to claim 10, characterized in that at least some of the dummy events correspond to the maximum and minimum durations of the first time slot. Device according to either of Claims 10 and 11, characterized in that each dummy event is repeated M times, and in that an average of these dummy events M times repeated is carried out to calibrate each event measurement.

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