EP0706100B1 - Time interval measuring device - Google Patents

Time interval measuring device Download PDF

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Publication number
EP0706100B1
EP0706100B1 EP95402202A EP95402202A EP0706100B1 EP 0706100 B1 EP0706100 B1 EP 0706100B1 EP 95402202 A EP95402202 A EP 95402202A EP 95402202 A EP95402202 A EP 95402202A EP 0706100 B1 EP0706100 B1 EP 0706100B1
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Prior art keywords
clock
signal
circuit
flip
flop
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German (de)
French (fr)
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EP0706100A1 (en
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Pascal Besesty
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time

Definitions

  • the present invention relates to a device for measure of the duration of a time interval.
  • the field of the invention is that of chronometry, of the precise time measurement of a period of time, short or infinitely long, included between a start signal and an end signal measured.
  • the present invention aims to resolve these problems.
  • the digital circuit is provided with a second clock, the pulses of which are offset from those of the first clock, the digital circuit also counts the number of pulses of the second clock which are followed by a period whole and which are included between the start (D) and end (F) signal, the analog circuit determines on the one hand the time separating the signal (D) and the start of the first pulse of the second clock which starts after (D) and, on the other hand, the time separating the end signal (F) from the end of the last period of the second clock which ends before (F), and this analog circuit is able to convert the data analog obtained in digital data.
  • the device also comprises means capable of determining which of the counts made on one of the two clocks (H 1 , H 2 ) is to be taken into account, so as to resolve any ambiguity situation which could lead to an error in counting a clock period.
  • start (D) and end (F) signals can be completely asynchronous from the clock. This is interesting for applications in the field of "time of flight" type telemetry, in which (D) and (F) are given by the start of a light pulse and by receiving the reflected pulse on a object, these two signals (D) and (F) can be asynchronous to the clock.
  • the part is measured coarse the time interval so digital, and the thin part analogically.
  • the parameters thus acquired are then recombined to get the result.
  • the measurement of time is thus obtained by associating a numerical quantity under the form of a number of clock periods counted, and analog quantities obtained by conversion of time in voltage amplitudes.
  • a triangular signal R of period 2T, of amplitude A, and synchronous with the base clock of period T is used.
  • a is the amplitude measured on the ramp
  • the t elapsed since the start of the ramp is equal to T / A • a .
  • t 1 and t 2 are then digitized, which gives two corresponding values T 1 and T 2 .
  • a device for the implementation of the invention is shown in Figure 2.
  • a clock H delivers pulses of period T on one of the inputs of an AND gate, designated by reference 2.
  • This clock H can be produced from a quartz oscillator, operating for example at a 200 MHz frequency.
  • the other door entrance AND receives a signal from the Q output of a flip-flop RS designated by reference 4, on input S of which we send the start signal D, while input R is controlled by the end signal F.
  • the assembly constituted by the AND gate, the flip-flop 4 and clock H constitutes a digital measurement circuit to obtain a rough value of the time interval to be measured. This value is equal at nT where n is the number of clock periods T elapsed between the start signal D and the end signal F. It is counted in a counter 3.
  • a division of the frequency of the signals of the clock H is carried out by a divider 6, constituted for example by a rocker, the output of this divider supplying a ramp generator 8.
  • This generator can be produced by the load and the constant current discharge of a capacitor. The period and the slope of these ramps are very well defined.
  • the output of the ramp generator 8 is sent to a fast analog-digital converter 10 (for example of the flash or fast sampler + converter type), another input of which receives a signal coming for example from a flip-flop 12, controlled by the signals D and F at the start and end of the period to be measured.
  • the converter 10 takes the information on the amplitude of the ramp at the instants of start D and of end F of the time interval to be measured, as well as the information relating to the parity of the ramp at these instants, that is to say, its ascending or descending character.
  • This converter makes it possible to obtain the information relating to the values T 1 and T 2 .
  • This information is stored in a memory 13.
  • the rough information relating to nT and the "fine" information relating to the intervals T 1 and T 2 are sent to a processing circuit 14 which calculates the duration t v of the time interval to be measured.
  • This device provides good precision, since it eliminates all synchronization of the start D and end F signals of measurement in relation to the clock H of the chronometer; he also eliminates limited capacity of the chronometer to determine a weak and a very significant time difference, which may vary by a few picoseconds to infinity, because of its frequency which is fixed.
  • This device also makes it possible to determine large time intervals with precision constant, regardless of the length of this interval of time. This is not true in the case of devices for measuring the duration of an interval of time according to the prior art, in particular in the case of device described in the French patent application n ° 93 08145 of July 2, 1993. Indeed, the latter device involves, at the start of measurement the time interval, the discharge of a capacitor, and at the end of the time interval measurement the charge of the same capacitor; however, the load measured immediately after the arrival of signal D may vary before we reach the final part of the time interval to be measured, just before the signal of end F, and this all the more since the interval of time to measure is important. In the device according to the present invention, this problem is avoided by having use of recurrent ramps.
  • this type of device can be easily integrated to create a compact circuit.
  • the invention allows problems related to be taken into account ambiguity on the starting signal D and on the arrival signal F. These problems arise when either of these signals occur simultaneously with a rising or falling edge of clock signals.
  • the game counter device numeric, part that determines the measurement coarse time interval, can then count an additional clock pulse, which would not have not to be counted.
  • a clock H 1 delivers signals of period T.
  • a divider allows generate signals S 1 , of period 2T, synchronized with the signals of the clock H 1 . It is thus possible to generate rising and falling ramps R 1 , of amplitude A.
  • a delay device makes it possible to generate a second clock signal H 2 , from the signal H 1 , the signals H 2 being shifted by T / 2 with respect to the signals of H 1 .
  • a falling edge of a slot of H 2 corresponds to a rising edge of a slot of H 1 , as can be seen in FIG. 3.
  • This clock signal H 2 makes it possible to generate, in the same way that it has been explained above for the clock H 1 , a signal S 2 of period 2T, which will itself control a ramp R 2 of the same amplitude A as the ramp R 1 .
  • the two ramps R 1 and R 2 are sampled simultaneously. If there is for example ambiguity between D and H 1 , that is to say if the signal D is superimposed on a rising edge of a slot of H 1 , there cannot be simultaneously ambiguity between the signal D and the signals generated by H 2 , due to the shift of a half-period between the two channels.
  • the valid clock to determine the measurement of t 1 is the clock H 2 and the value to be taken into account is that measured on the ramp R 2 .
  • a first counter 25 receives on its CE authorization input a counting order coming from a flip-flop 23 and on its input C the clock signals H 1 .
  • the data at the output of the first counter 25 are transmitted to a processing circuit 22 by means of a routing circuit 36 controlled by an OR circuit 32.
  • the D flip-flops 26 and 30 receive the D and F signals via an OR 40, 41 function on their D input.
  • the flip-flop 23, which delivers the CE authorization signal, is also controlled by the D and F signals both delayed by an amount close to 3 propagation times in gates by devices 19, 42 which consist for example of delays in logic gates.
  • the first AND circuit 27 performs the AND function of the output of the flip-flop 26 and of the clock H 2 ; the signals of the latter are obtained from H 1 and a delay circuit 18, constituted for example by propagation times in gates.
  • a second counter 29 receives on its CE authorization input a counting order coming from the flip-flop 23.
  • the data from this counter 29 is transmitted to the processing circuit 22 via the circuit 36.
  • the second flip-flop type D 30 works as described above.
  • the second AND circuit 31 performs the AND function between the output of circuit 30 and the clock H 1 .
  • the output of circuit 32 controls the operation of the switching circuit 36 to obtain reading of counter 25 or 29 including the type flip-flop D (26 or 30) partner did not switch first. he detects the first of flip-flops 26 or 30 that has toppled and it authorizes the reading of the counter whose rocker has not changed state.
  • circuits 44, 45 and 46, 47 respectively for the first and second counters. Circuits 44 and 46 are AND circuits, circuits 45 and 47 are time formatting.
  • a flip-flop 33 receives on its SET input the output of an OR 34 circuit whose inputs correspond to signals D and F delayed by circuits 42 and 19.
  • the flip-flop 33 receives on its other input the outputs of the two doors AND 27, 31.
  • This flip-flop 33 controls an input of an analog-digital converter 50 and an input of an analog-digital converter 52. Another input of each of these converters 50, 52 is connected to the clock H 1 (respectively H 2 ) via a flip-flop 51 (respectively 53) which makes it possible to generate a signal S 1 respectively S 2 of period 2T, and a ramp generator 55 (respectively 57) to generate a ramp R1 (respectively R2). Downstream of the analog-digital converters, there are two memories 60, 62 and a switching circuit 56 controlled by the circuit 32.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Description

Domaine techniqueTechnical area

La présente invention concerne un dispositif de mesure de la durée d'un intervalle de temps.The present invention relates to a device for measure of the duration of a time interval.

Le domaine de l'invention est celui de la chronométrie, de la mesure temporelle précise d'une période de temps, courte ou infiniment longue, comprise entre un signal de départ et un signal de fin de mesure.The field of the invention is that of chronometry, of the precise time measurement of a period of time, short or infinitely long, included between a start signal and an end signal measured.

Ce type de problème se pose dans tous les dispositifs où une mesure temporelle précise est nécessaire sur des durées très longues, en particulier dans les dispositifs utilisés dans le domaine de la télémétrie laser.This type of problem occurs in all devices where an accurate time measurement is necessary over very long periods, in particular in the devices used in the field of laser telemetry.

Etat de la technique antérieureState of the art

Dans le domaine de la mesure de temps de grande précision, on fait appel :

  • soit à des technique de moyennage qui augmentent considérablement le temps d'acquisition par rapport au temps mesuré. Ce type de technique ne peut pas être employé dans le cas où le temps d'acquisition doit être limité, et, par ailleurs, le moyennage n'est possible que si le phénomène mesuré présente une stationnarité convenable relativement au temps de moyennage.
  • à des techniques de type "vernier", ces techniques reposant sur le comptage des périodes d'une horloge, pour une mesure grossière, et sur la détermination d'un complément temporel par une méthode analogique qui donne la précision à la mesure. Une telle technique est décrite dans l'article intitulé "The vernier time-measuring technique" de Robert G. Baron (proceedings of the IRE, janvier 1957), mais cette technique rallonge d'une quantité non négligeable le temps de mesure (5µs de temps de mesure pour une résolution de 20 µs avec des horloges de 100 mégahertz). Cette technique limite donc le nombre de mesures possibles bien en-deçà de la cadence de réalisation de certains événements.
In the area of high-precision time measurement, use is made of:
  • or to averaging techniques which considerably increase the acquisition time compared to the measured time. This type of technique cannot be used in the case where the acquisition time must be limited, and, moreover, averaging is only possible if the phenomenon measured has suitable stationarity relative to the averaging time.
  • to "vernier" type techniques, these techniques based on counting the periods of a clock, for a rough measurement, and on the determination of a time complement by an analog method which gives the precision to the measurement. Such a technique is described in the article entitled "The vernier time-measuring technique" by Robert G. Baron (proceedings of the IRE, January 1957), but this technique extends the measurement time by a significant amount (5µs of measurement time for a resolution of 20 µs with clocks of 100 megahertz). This technique therefore limits the number of possible measurements well below the rate at which certain events take place.

La demande de brevet français déposée sous le n°93 08145 (2 juillet 1993) intitulée "Dispositif de mesure de la durée d'un intervalle de temps" décrit un procédé de mesure de temps qui permet d'enlever l'ambiguïté de comptage d'un coup d'horloge et tient compte des problèmes de non-synchronisme. Ce procédé n'est pas adapté à la mesure de durées temporelles importantes, supérieures à 10 µs, du fait de la décharge d'un condensateur du circuit qui peut entraíner une erreur importante sur de grands intervalles de mesure, notamment pour des applications de télémétrie à moyenne distance (supérieure à 1 km).The French patent application filed under n ° 93 08145 (July 2, 1993) entitled "Device for measure of the duration of a time interval "describes a time measurement process which removes the ambiguity of counting a clock and holds account for problems of non-synchronism. This process is not suitable for measuring time durations important, greater than 10 µs, due to the discharge of a circuit capacitor which can cause a major error on large measurement intervals, especially for applications medium distance telemetry (greater than 1 km).

Exposé de l'inventionStatement of the invention

La présente invention vise à résoudre ces problèmes.The present invention aims to resolve these problems.

Plus précisément, elle a pour objet un dispositif de mesure de la durée d'un intervalle de temps compris entre un signal de début (D) et un signal de fin (F), caractérisé en ce qu'il comporte :

  • une première horloge qui délivre des impulsions avec une période T,
  • un circuit numérique pour compter le nombre d'impulsions de la première horloge qui sont suivies par une période entière T et qui sont comprises entre le signal de début (D) et le signal de fin (F),
  • un circuit analogique pour déterminer d'une part le temps t1 séparant le signal (D) et le début de la première impulsion de la première horloge qui commence après (D) et d'autre part le temps t2 séparant le signal de fin (F) de la fin de la dernière période de la première horloge qui s'achève avant (F), et apte à convertir les données analogiques obtenues en données numériques,
  • un circuit de traitement, pour déterminer la durée de l'intervalle de temps à partir des données fournies par le circuit numérique et celles fournies par le circuit analogique préalablement converties en données numériques,
  • des moyens déterminant lequel des comptages réalisés sur l'une des deux horloges (H1, H2) est à prendre en compte, de manière à résoudre toute situation d'ambiguïté.
More specifically, it relates to a device for measuring the duration of a time interval between a start signal (D) and an end signal (F), characterized in that it comprises:
  • a first clock which delivers pulses with a period T,
  • a digital circuit for counting the number of pulses of the first clock which are followed by an entire period T and which are included between the start signal (D) and the end signal (F),
  • an analog circuit for determining on the one hand the time t 1 separating the signal (D) and the start of the first pulse of the first clock which begins after (D) and on the other hand the time t 2 separating the end signal (F) of the end of the last period of the first clock which ends before (F), and capable of converting the analog data obtained into digital data,
  • a processing circuit, to determine the duration of the time interval from the data supplied by the digital circuit and that supplied by the analog circuit previously converted into digital data,
  • means determining which of the counts made on one of the two clocks (H 1 , H 2 ) is to be taken into account, so as to resolve any ambiguity situation.

Selon l'invention, le circuit numérique est muni d'une seconde horloge, dont les impulsions sont décalées par rapport à celles de la première horloge, le circuit numérique compte également le nombre d'impulsions de la seconde horloge qui sont suivies par une période entière et qui sont comprises entre le signal de début (D) et de fin (F), le circuit analogique détermine d'une part le temps séparant le signal (D) et le début de la première impulsion de la deuxième horloge qui commence après (D) et, d'autre part, le temps séparant le signal de fin (F) de la fin de la dernière période de la deuxième horloge qui s'achève avant (F), et ce circuit analogique est apte à convertir les données analogiques obtenues en données numériques. Le dispositif comporte en outre des moyens aptes à déterminer lequel des comptages réalisés sur l'une des deux horloges (H1, H2) est à prendre en compte, de manière à résoudre toute situation d'ambiguïté qui pourrait conduire à une erreur de comptage d'une période d'horloge.According to the invention, the digital circuit is provided with a second clock, the pulses of which are offset from those of the first clock, the digital circuit also counts the number of pulses of the second clock which are followed by a period whole and which are included between the start (D) and end (F) signal, the analog circuit determines on the one hand the time separating the signal (D) and the start of the first pulse of the second clock which starts after (D) and, on the other hand, the time separating the end signal (F) from the end of the last period of the second clock which ends before (F), and this analog circuit is able to convert the data analog obtained in digital data. The device also comprises means capable of determining which of the counts made on one of the two clocks (H 1 , H 2 ) is to be taken into account, so as to resolve any ambiguity situation which could lead to an error in counting a clock period.

Ainsi, il est possible de lever toute situation d'ambiguïté dans le cas où l'un des signaux (D) et (F) est confondu avec une impulsion d'horloge.So it is possible to lift any situation of ambiguity in the case where one of the signals (D) and (F) is confused with a clock pulse.

Ce dispositif permet de mesurer des intervalles de temps très longs avec une très grande précision. En outre, les signaux de départ (D) et de fin (F) peuvent être complètement asynchrones de l'horloge. Ceci est intéressant pour des applications au domaine de la télémétrie du type "temps de vol", dans lequel (D) et (F) sont donnés par le départ d'une impulsion lumineuse et par la réception de l'impulsion réfléchie sur un objet, ces deux signaux (D) et (F) pouvant être asynchrones par rapport à l'horloge.This device makes it possible to measure intervals very long times with very high precision. In in addition, the start (D) and end (F) signals can be completely asynchronous from the clock. this is interesting for applications in the field of "time of flight" type telemetry, in which (D) and (F) are given by the start of a light pulse and by receiving the reflected pulse on a object, these two signals (D) and (F) can be asynchronous to the clock.

Selon un mode particulier de réalisation de l'invention, le circuit analogique peut en outre comprendre :

  • un circuit diviseur de fréquence, relié à la première horloge,
  • un premier générateur de rampes commandé par le signal de sortie du circuit diviseur de fréquence,
  • et un premier convertisseur analogique-numérique, recevant d'une part le signal engendré par le premier générateur de rampes et, d'autre part, les signaux de début (D) et de fin (F) de l'intervalle de temps à mesurer.
According to a particular embodiment of the invention, the analog circuit can also comprise:
  • a frequency divider circuit, connected to the first clock,
  • a first ramp generator controlled by the output signal of the frequency divider circuit,
  • and a first analog-to-digital converter, receiving on the one hand the signal generated by the first ramp generator and, on the other hand, the start (D) and end (F) signals of the time interval to be measured .

D'autres aspects et modes particuliers de réalisation apparaissent dans les revendications dépendantesOther specific aspects and modes of achievement appear in claims dependent

Brève description des figuresBrief description of the figures

De toute façon, les caractéristiques et avantages de l'invention apparaítront mieux à la lumière de la description qui va suivre. Cette description porte sur les exemples de réalisation, donnés à titre explicatif et non limitatif, en se référant à des dessins annexés sur lesquels :

  • la figure 1 illustre le principe de la mesure d'un intervalle de temps, selon la présente invention,
  • la figure 2 est un schéma d'un dispositif pour la mise en oeuvre de l'invention,
  • la figure 3 illustre le principe de la méthode selon un mode particulier de réalisation de l'invention, dans le cas où des situations d'ambiguïté doivent être levées,
  • la figure 4 est un schéma d'un autre dispositif pour la mise en oeuvre de l'invention selon un second mode particulier de réalisation.
In any case, the characteristics and advantages of the invention will appear better in the light of the description which follows. This description relates to the exemplary embodiments, given by way of explanation and without limitation, with reference to the appended drawings in which:
  • FIG. 1 illustrates the principle of the measurement of a time interval, according to the present invention,
  • FIG. 2 is a diagram of a device for implementing the invention,
  • FIG. 3 illustrates the principle of the method according to a particular embodiment of the invention, in the case where ambiguity situations have to be resolved,
  • FIG. 4 is a diagram of another device for implementing the invention according to a second particular embodiment.

Exposé détaillé de modes de réalisationDetailed description of embodiments

Pour mesurer la durée d'un intervalle de temps déterminé, selon l'invention, on mesure la partie grossière de l'intervalle de temps de manière numérique, et la partie fine de manière analogique. Les paramètres ainsi acquis sont ensuite recombinés pour obtenir le résultat. La mesure de temps est ainsi obtenue en associant une grandeur numérique sous la forme d'un nombre de périodes d'horloge comptées, et des grandeurs analogiques obtenues par conversion de temps en amplitudes de tension.To measure the duration of a time interval determined, according to the invention, the part is measured coarse the time interval so digital, and the thin part analogically. The parameters thus acquired are then recombined to get the result. The measurement of time is thus obtained by associating a numerical quantity under the form of a number of clock periods counted, and analog quantities obtained by conversion of time in voltage amplitudes.

Ce principe est illustré plus précisément à l'aide du chronogramme de la figure 1. On cherche à mesurer l'intervalle de temps tv entre une impulsion de départ D et une impulsion de fin d'intervalle à mesurer F.This principle is illustrated more precisely using the timing diagram of FIG. 1. We seek to measure the time interval t v between a start pulse D and an end pulse to measure F.

Pour cela, on utilise une horloge de base H, de période T. On compte le nombre n d'impulsions d'horloge qui sont suivies par une période entière T, et ceci pendant la durée tv. Le temps total correspondant à l'écoulement de cette période est égal à nT. Comme l'horloge n'est pas synchrone avec le signal de départ D et de fin F, il faut en outre déterminer d'une part le temps t1, qui s'écoule entre le signal de départ D et le début de la première impulsion d'horloge qui commence après D, et, d'autre part, le temps t2, qui s'écoule entre le signal de fin F et la fin de la dernière période d'horloge qui s'achève avant le signal F. Pour obtenir la durée de l'intervalle de temps tv, il suffit ensuite d'additionner les trois temps mesurés : t1+nT+t2.For this, we use a basic clock H, of period T. We count the number n of clock pulses which are followed by an entire period T, and this for the duration t v . The total time corresponding to the passage of this period is equal to nT. As the clock is not synchronous with the start signal D and end signal F, it is also necessary to determine on the one hand the time t 1 , which elapses between the start signal D and the start of the first clock pulse which begins after D, and, on the other hand, the time t 2 , which elapses between the end signal F and the end of the last clock period which ends before the signal F. To obtain the duration of the time interval t v , it then suffices to add the three measured times: t 1 + nT + t 2 .

Pour déterminer t1 et t2, on utilise un signal triangulaire R, de période 2T, d'amplitude A, et synchrone avec l'horloge de base de période T. A tout instant, si a est l'amplitude mesurée sur la rampe, le t écoulé depuis le début de la rampe est égal à T / A•a. En échantillonnant les rampes à l'apparition du signal de départ D et du signal de fin F, on obtient des amplitudes a1 et a2 représentatives respectivement de t1 et t2.To determine t 1 and t 2 , a triangular signal R, of period 2T, of amplitude A, and synchronous with the base clock of period T is used. At any time, if a is the amplitude measured on the ramp , the t elapsed since the start of the ramp is equal to T / A • a . By sampling the ramps on the appearance of the start signal D and the end signal F, we obtain amplitudes a 1 and a 2 representative of t 1 and t 2 respectively .

Si l'impulsion de départ se produit au cours d'une rampe montante, on a alors : t1= T / A•a1 .If the starting pulse occurs during an increasing ramp, we then have: t 1 = T / A • a 1 .

Si l'impulsion de départ se produit au cours d'une rampe descendante, on a : t1=T- T / A•a1 .If the starting pulse occurs during a falling ramp, we have: t 1 = T- T / A • a 1 .

Si l'impulsion de fin F se produit sur une rampe montante, on a : t2= T / A•a2 .If the end pulse F occurs on a rising ramp, we have: t 2 = T / A • a 2 .

Si l'impulsion de fin F se produit sur une rampe descendante, on a : t2=T- T / A•a2 .If the end pulse F occurs on a descending ramp, we have: t 2 = T- T / A • a 2 .

t1 et t2 sont ensuite numérisés, ce qui donne deux valeurs T1 et T2 correspondantes. On obtient ensuite la durée de l'intervalle de temps tv=nT+T1+T2.t 1 and t 2 are then digitized, which gives two corresponding values T 1 and T 2 . We then obtain the duration of the time interval t v = nT + T 1 + T 2 .

Un dispositif pour la mise en oeuvre de l'invention est représenté sur la figure 2. Une horloge H délivre des impulsions de période T sur une des entrées d'une porte ET, désignée par la référence 2. Cette horloge H peut être réalisée à partir d'un oscillateur à quartz, fonctionnant par exemple à une fréquence de 200 MHz. L'autre entrée de la porte ET reçoit un signal à partir de la sortie Q d'une bascule RS désignée par la référence 4, sur l'entrée S de laquelle on envoie le signal de départ D, tandis que l'entrée R est pilotée par le signal de fin F. L'ensemble constitué par la porte ET, la bascule 4 et l'horloge H constitue un circuit de mesure numérique permettant d'obtenir une valeur grossière de l'intervalle de temps à mesurer. Cette valeur est égale à nT où n est le nombre de périodes d'horloge T écoulé entre le signal de début D et le signal de de fin F. Elle est comptabilisée dans un compteur 3.A device for the implementation of the invention is shown in Figure 2. A clock H delivers pulses of period T on one of the inputs of an AND gate, designated by reference 2. This clock H can be produced from a quartz oscillator, operating for example at a 200 MHz frequency. The other door entrance AND receives a signal from the Q output of a flip-flop RS designated by reference 4, on input S of which we send the start signal D, while input R is controlled by the end signal F. The assembly constituted by the AND gate, the flip-flop 4 and clock H constitutes a digital measurement circuit to obtain a rough value of the time interval to be measured. This value is equal at nT where n is the number of clock periods T elapsed between the start signal D and the end signal F. It is counted in a counter 3.

En parallèle, une division de la fréquence des signaux de l'horloge H est effectuée par un diviseur 6, constitué par exemple par une bascule, la sortie de ce diviseur alimentant un générateur de rampes 8. Ce générateur peut être réalisé par la charge et la décharge à courant constant d'un condensateur. La période et la pente de ces rampes sont très bien définies. La sortie du générateur de rampes 8 est envoyée sur un convertisseur analogique-numérique rapide 10 (par exemple du type flash ou échantillonneur rapide + convertisseur), dont une autre entrée reçoit un signal provenant par exemple d'une bascule 12, pilotée par les signaux D et F de début et de fin de la période à mesurer. Ainsi, le convertisseur 10 prélève l'information sur l'amplitude de la rampe aux instants de début D et de fin F de l'intervalle de temps à mesurer, ainsi que l'information relative à la parité de la rampe à ces instants, c'est-à-dire à son caractère montant ou descendant. Ce convertisseur permet d'obtenir les informations portant sur les valeurs T1 et T2. Ces informations sont mémorisées dans une mémoire 13.In parallel, a division of the frequency of the signals of the clock H is carried out by a divider 6, constituted for example by a rocker, the output of this divider supplying a ramp generator 8. This generator can be produced by the load and the constant current discharge of a capacitor. The period and the slope of these ramps are very well defined. The output of the ramp generator 8 is sent to a fast analog-digital converter 10 (for example of the flash or fast sampler + converter type), another input of which receives a signal coming for example from a flip-flop 12, controlled by the signals D and F at the start and end of the period to be measured. Thus, the converter 10 takes the information on the amplitude of the ramp at the instants of start D and of end F of the time interval to be measured, as well as the information relating to the parity of the ramp at these instants, that is to say, its ascending or descending character. This converter makes it possible to obtain the information relating to the values T 1 and T 2 . This information is stored in a memory 13.

L'information grossière portant sur nT et les informations "fines" portant sur les intervalles T1 et T2 sont envoyées à un circuit de traitement 14 qui calcule la durée tv de l'intervalle de temps à mesurer.The rough information relating to nT and the "fine" information relating to the intervals T 1 and T 2 are sent to a processing circuit 14 which calculates the duration t v of the time interval to be measured.

Ce dispositif permet d'obtenir une bonne précision, puisqu'il permet de s'affranchir de toute synchronisation des signaux de départ D et de fin F de mesure par rapport à l'horloge H du chronomètre ; il permet également de s'affranchir de la capacité limitée du chronomètre à déterminer un faible et un très important écart temporel, pouvant varier de quelques picosecondes à l'infini, du fait de sa fréquence qui est fixe.This device provides good precision, since it eliminates all synchronization of the start D and end F signals of measurement in relation to the clock H of the chronometer; he also eliminates limited capacity of the chronometer to determine a weak and a very significant time difference, which may vary by a few picoseconds to infinity, because of its frequency which is fixed.

Ce dispositif permet également de déterminer des intervalles de temps importants avec une précision constante, quelle que soit la durée de cet intervalle de temps. Ceci n'est pas vrai dans le cas des dispositifs de mesure de la durée d'un intervalle de temps selon l'art antérieur, notamment dans le cas du dispositif décrit dans la demande de brevet français n° 93 08145 du 2 juillet 1993. En effet, ce dernier dispositif fait intervenir, en début de mesure de l'intervalle de temps, la décharge d'un condensateur, et en fin de mesure de l'intervalle de temps la charge du même condensateur ; or, la charge mesurée immédiatement après l'arrivée du signal D peut varier avant que l'on ait atteint la partie finale de l'intervalle de temps à mesurer, juste avant le signal de fin F, et ceci d'autant plus que l'intervalle de temps à mesurer est important. Dans le dispositif selon la présente invention, on évite ce problème en ayant recours à des rampes récurrentes. This device also makes it possible to determine large time intervals with precision constant, regardless of the length of this interval of time. This is not true in the case of devices for measuring the duration of an interval of time according to the prior art, in particular in the case of device described in the French patent application n ° 93 08145 of July 2, 1993. Indeed, the latter device involves, at the start of measurement the time interval, the discharge of a capacitor, and at the end of the time interval measurement the charge of the same capacitor; however, the load measured immediately after the arrival of signal D may vary before we reach the final part of the time interval to be measured, just before the signal of end F, and this all the more since the interval of time to measure is important. In the device according to the present invention, this problem is avoided by having use of recurrent ramps.

Enfin, ce type de dispositif peut être facilement intégrable pour réaliser un circuit compact.Finally, this type of device can be easily integrated to create a compact circuit.

L'invention permet de tenir compte des problèmes liés aux situations d'ambiguïté sur le signal de départ D et sur le signal d'arrivée F. Ces problèmes surgissent lorsque l'un ou l'autre de ces signaux, se produisent simultanément à un front de montée ou de descente des signaux de l'horloge. Le compteur de la partie numérique du dispositif, partie qui détermine la mesure grossière de l'intervalle de temps, peut alors compter une impulsion d'horloge supplémentaire, qui n'aurait pas du être comptée.The invention allows problems related to be taken into account ambiguity on the starting signal D and on the arrival signal F. These problems arise when either of these signals occur simultaneously with a rising or falling edge of clock signals. The game counter device numeric, part that determines the measurement coarse time interval, can then count an additional clock pulse, which would not have not to be counted.

De façon à résoudre ce problème, l'invention propose un dispositif qui fonctionne sur le principe illustré sur la figure 3. Conformément à ce qui a déjà été expliqué ci-dessus, une horloge H1 délivre des signaux de période T. Un diviseur permet de générer des signaux S1, de période 2T, synchronisés avec les signaux de l'horloge H1. On peut ainsi générer des rampes montantes et descendantes R1, d'amplitude A. Un dispositif de retard permet de générer un deuxième signal d'horloge H2, à partir du signal H1, les signaux H2 étant décalés de T/2 par rapport aux signaux de H1. Ainsi, un front descendant d'un créneau de H2 correspond à un front montant d'un créneau de H1, comme on peut le voir sur la figure 3. Ce signal d'horloge H2 permet de générer, de la même manière qu'il a été expliqué ci-dessus pour l'horloge H1, un signal S2 de période 2T, qui va commander lui-même une rampe R2 de même amplitude A que la rampe R1. Lorsque le signal D de départ de la mesure se présente, on échantillonne simultanément les deux rampes R1 et R2. S'il y a par exemple ambiguïté entre D et H1, c'est-à-dire si le signal D se superpose à un front de montée d'un créneau de H1, il ne peut y avoir simultanément ambiguïté entre le signal D et les signaux générés par H2, du fait du décalage d'une demi-période entre les deux voies. Par conséquent, il suffit d'identifier l'horloge qui n'est pas en situation d'ambiguïté avec le signal de départ D, et de ne retenir alors que la valeur échantillonnée de la rampe R correspondante pour déterminer t1. Par exemple, si la situation d'ambiguïté se présente entre le signal de départ D et l'horloge H1, l'horloge valide pour déterminer la mesure de t1 est l'horloge H2 et la valeur à prendre en compte est celle mesurée sur la rampe R2.In order to solve this problem, the invention proposes a device which operates on the principle illustrated in FIG. 3. In accordance with what has already been explained above, a clock H 1 delivers signals of period T. A divider allows generate signals S 1 , of period 2T, synchronized with the signals of the clock H 1 . It is thus possible to generate rising and falling ramps R 1 , of amplitude A. A delay device makes it possible to generate a second clock signal H 2 , from the signal H 1 , the signals H 2 being shifted by T / 2 with respect to the signals of H 1 . Thus, a falling edge of a slot of H 2 corresponds to a rising edge of a slot of H 1 , as can be seen in FIG. 3. This clock signal H 2 makes it possible to generate, in the same way that it has been explained above for the clock H 1 , a signal S 2 of period 2T, which will itself control a ramp R 2 of the same amplitude A as the ramp R 1 . When the measurement start signal D occurs, the two ramps R 1 and R 2 are sampled simultaneously. If there is for example ambiguity between D and H 1 , that is to say if the signal D is superimposed on a rising edge of a slot of H 1 , there cannot be simultaneously ambiguity between the signal D and the signals generated by H 2 , due to the shift of a half-period between the two channels. Consequently, it suffices to identify the clock which is not in an ambiguous situation with the starting signal D, and to then only retain the sampled value of the corresponding ramp R to determine t 1 . For example, if the ambiguity situation arises between the starting signal D and the clock H 1 , the valid clock to determine the measurement of t 1 is the clock H 2 and the value to be taken into account is that measured on the ramp R 2 .

Il en va de même pour toute situation d'ambiguïté sur le signal F. Lorsque le signal de fin F se présente, on échantillonne simultanément les deux rampes R1 et R2. On prend pour t2 la valeur de la rampe R1 ou R2 issue de l'horloge H1 ou H2 qui ne présente pas d'ambiguïté avec le signal F.The same goes for any ambiguity situation on the signal F. When the end signal F occurs, the two ramps R 1 and R 2 are sampled simultaneously. We take for t 2 the value of the ramp R 1 or R 2 from the clock H 1 or H 2 which does not have any ambiguity with the signal F.

Dans le cas où une situation d'ambiguité existe simultanément sur D et F, il est possible de rajouter un troisième circuit avec une horloge H3 décalée par rapport à H2 et H1.In the case where an ambiguity situation exists simultaneously on D and F, it is possible to add a third circuit with a clock H 3 offset from H 2 and H 1 .

Dans le cas où il n'y a aucune ambiguïté, ni avec l'horloge H1 ni avec l'horloge H2, les valeurs de temps obtenues (t1 ou t2) seront prises indifféremment sur l'un des deux circuits correspondant aux deux horloges.In the case where there is no ambiguity, neither with the clock H 1 nor with the clock H 2 , the time values obtained (t 1 or t 2 ) will be taken indifferently on one of the two corresponding circuits to the two clocks.

Le dispositif correspondant à ce mode particulier de mise en oeuvre de l'invention est illustré sur la figure 4. Sur cette figure, dans un premier bloc 24, un premier compteur 25 reçoit sur son entrée autorisation CE un ordre de comptage venant d'une bascule 23 et sur son entrée C les signaux d'horloge H1. Les données en sortie du premier compteur 25 sont transmises à un circuit de traitement 22 par l'intermédiaire d'un circuit d'aiguillage 36 commandé par un circuit OU 32.The device corresponding to this particular embodiment of the invention is illustrated in FIG. 4. In this figure, in a first block 24, a first counter 25 receives on its CE authorization input a counting order coming from a flip-flop 23 and on its input C the clock signals H 1 . The data at the output of the first counter 25 are transmitted to a processing circuit 22 by means of a routing circuit 36 controlled by an OR circuit 32.

Les bascules D 26 et 30 reçoivent les signaux D et F par l'intermédiaire d'une fonction OU 40, 41 sur leur entrée D. La bascule 23, qui délivre le signal d'autorisation CE est également commandée par les signaux D et F tous deux retardés d'une quantité voisine de 3 temps de propagation dans des portes par les dispositifs 19, 42 qui sont constitués par exemple de retards dans des portes logiques. Le premier circuit ET 27 réalise la fonction ET de la sortie de la bascule 26 et de l'horloge H2 ; les signaux de cette dernière sont obtenus à partir de H1 et d'un circuit de retard 18, constitué par exemple par des temps de propagation dans des portes.The D flip-flops 26 and 30 receive the D and F signals via an OR 40, 41 function on their D input. The flip-flop 23, which delivers the CE authorization signal, is also controlled by the D and F signals both delayed by an amount close to 3 propagation times in gates by devices 19, 42 which consist for example of delays in logic gates. The first AND circuit 27 performs the AND function of the output of the flip-flop 26 and of the clock H 2 ; the signals of the latter are obtained from H 1 and a delay circuit 18, constituted for example by propagation times in gates.

Dans le second bloc 28, un second compteur 29 reçoit sur son entrée autorisation CE un ordre de comptage venant de la bascule 23. Les données de ce compteur 29 sont transmises au circuit de traitement 22 par l'intermédiaire du circuit 36. La seconde bascule de type D 30 fonctionne comme décrit ci-dessus. Le second circuit ET 31 réalise la fonction ET entre la sortie du circuit 30 et l'horloge H1.In the second block 28, a second counter 29 receives on its CE authorization input a counting order coming from the flip-flop 23. The data from this counter 29 is transmitted to the processing circuit 22 via the circuit 36. The second flip-flop type D 30 works as described above. The second AND circuit 31 performs the AND function between the output of circuit 30 and the clock H 1 .

La sortie du circuit 32 commande le fonctionnement du circuit d'aiguillage 36 pour obtenir la lecture du compteur 25 ou 29 dont la bascule de type D (26 ou 30) associée n'a pas basculé la première. Il détecte la première des bascules 26 ou 30 qui a basculé et il autorise la lecture du compteur dont la bascule n'a pas changé d'état.The output of circuit 32 controls the operation of the switching circuit 36 to obtain reading of counter 25 or 29 including the type flip-flop D (26 or 30) partner did not switch first. he detects the first of flip-flops 26 or 30 that has toppled and it authorizes the reading of the counter whose rocker has not changed state.

S'il y a une situation d'incertitude, par exemple au début du comptage, pour l'un ou l'autre des compteurs, le premier des circuits d'identification de présence 26, 30 qui bascule valide le choix entre les horloges H1 ou H2. Le compteur validé est laissé inchangé, par contre l'autre compteur est remis à zéro avant l'arrivée de la deuxième impulsion d'horloge suivant le signal D. Ceci est réalisé par les circuits 44, 45 et 46, 47 respectivement pour les premier et deuxième compteurs. Les circuits 44 et 46 sont des circuits ET, les circuits 45 et 47 sont des mises en forme temporelle.If there is a situation of uncertainty, for example at the start of the counting, for one or other of the counters, the first of the presence identification circuits 26, 30 which switches validates the choice between the clocks H 1 or H 2 . The validated counter is left unchanged, on the other hand the other counter is reset to zero before the arrival of the second clock pulse according to the signal D. This is achieved by circuits 44, 45 and 46, 47 respectively for the first and second counters. Circuits 44 and 46 are AND circuits, circuits 45 and 47 are time formatting.

Une bascule 33 (bascule de type RS) reçoit sur son entrée SET la sortie d'un circuit OU 34 dont les entrées correspondent aux signaux D et F retardés par les circuits 42 et 19. La bascule 33 reçoit sur son autre entrée les sorties des deux portes ET 27, 31.A flip-flop 33 (RS-type flip-flop) receives on its SET input the output of an OR 34 circuit whose inputs correspond to signals D and F delayed by circuits 42 and 19. The flip-flop 33 receives on its other input the outputs of the two doors AND 27, 31.

Cette bascule 33 commande une entrée d'un convertisseur analogique-numérique 50 et une entrée d'un convertisseur analogique-numérique 52. Une autre entrée de chacun de ces convertisseurs 50, 52 est reliée à l'horloge H1 (respectivement H2) par l'intermédiaire d'une bascule 51 (respectivement 53) qui permet de générer un signal S1 respectivement S2 de période 2T, et d'un générateur de rampe 55 (respectivement 57) pour générer une rampe R1 (respectivement R2) . En aval des convertisseurs analogiques-numériques, on trouve deux mémoires 60, 62 et un circuit d'aiguillage 56 commandé par le circuit 32.This flip-flop 33 controls an input of an analog-digital converter 50 and an input of an analog-digital converter 52. Another input of each of these converters 50, 52 is connected to the clock H 1 (respectively H 2 ) via a flip-flop 51 (respectively 53) which makes it possible to generate a signal S 1 respectively S 2 of period 2T, and a ramp generator 55 (respectively 57) to generate a ramp R1 (respectively R2). Downstream of the analog-digital converters, there are two memories 60, 62 and a switching circuit 56 controlled by the circuit 32.

Claims (8)

  1. Device for measuring the duration of a time slot between a start signal (D) and a stop signal (F), characterized in that it comprises:
    a first clock (H, H1) supplying pulses with a period T, as well as a second clock (H2), whose pulses are shifted with respect to those of the first clock (H1),
    a digital circuit (2, 3, 4; 20) for counting the number of pulses of the first clock and which are followed by a complete period T and occur between the start signal (D) and the stop signal (F), the digital circuit (20) also counting the number of pulses of the second clock followed by a complete period T and which occur between the start signal (D) and the stop signal (F),
    an analog circuit (6, 8, 12, 10, 13; 21) for determining on the one hand the time t1 separating the signal (D) and the start of the first pulse of the first clock commencing after (D) and on the other hand the time t2 separating the stop signal (F) from the end of the final period of the first clock completed before (F), as well as on the other hand the time separating the signal (D) and the start of the first pulse of the second clock commencing after (D) and also the time separating the stop signal (F) from the end of the final period of the second clock completed before (F), the analog circuit also being able to convert the analog data obtained into digital data,
    a processing circuit (14, 22) for determining the duration of the time slot on the basis of data supplied by the digital circuit and those supplied by the analog circuit previously converted into digital data,
    means determining which of the counts performed on one of the two clocks (H1, H2) is to be taken into account, so as to resolve any ambiguity situation which could lead to a clock period counting error.
  2. Device according to claim 1, the analog circuit also comprising:
    a frequency dividing circuit (6; 53) connected to the first clock,
    a first ramp generator (8; 57) controlled by the output signal of the frequency dividing circuit (6; 53),
    and a first analog-digital converter (10; 52) receiving on the one hand the signal produced by the first ramp generator (8; 57) and on the other the start signal (D) and stop signal (F) of the time slot to be measured.
  3. Device according to claim 2, the start signal (D) and stop signal (F) of the time slot to be measured being transmitted to the first analog-digital converter (10; 52) by means of a flip-flop (12; 33).
  4. Device according to any one of the claims 1 to 3, the digital circuit (20) also comprising:
    a R-S flip-flop (23) controlled on its set input by the start signal (D) delayed after passage in a first delay circuit (42) and, on its reset input by the delayed stop signal (F), following passage in a delay circuit (19),
    a first block (24) having a first counter (25), a first D-flip-flop (26), a first AND gate (27), a first OR gate (40), a second AND gate (44) and a means (45) for the time shaping of the signal,
    and a second block (28) having a second counter (29), a second D-flip-flop (30), a third AND gate (31), a second OR gate (41), a fourth AND gate (46), a signal time shaping means (47),
    a circuit (32) able to perform an OR function for detecting which of the outputs of the flip-flops (26, 30) has switched first.
  5. Device according to claim 4, wherein:
    in the first block (24), the first counter (25) receives on its authorization input CE a counting order from the R-S flip-flop (23),
    the output data of the first counter (25) are transmitted to the processing circuit (22) by means of a switching circuit (36) controlled by the OR gate (32),
    the first D-flip-flop (26) controlled by the first OR gate (40) receives on the one hand the start signal (D) and the stop signal (F) and on the other the pulses from the first clock (H1) and
    the first AND gate (27) implements the AND function between on the one hand the output of the first D-flip-flop (26) and on the other the pulses from the second clock (H2).
  6. Device according to either of the claims 4 and 5, wherein:
    in the second block (28), the second counter (29) receives on its authorization input (CE) a counting order from the R-S flip-flop (23),
    the data from said counter (29) are transmitted to the processing circuit (22) by means of a switching circuit (36),
    the second D-flip-flop (30) controlled by the second OR gate (41) receives on the one hand the start signal (D) and the stop signal (F) and on the other the pulses from the second clock (H2) and
    the second AND gate (31) implements the AND function between the output of said D-flip-flop (30), and pulses from the first clock (H1).
  7. Device according to claims 3 and 4, wherein the flip-flop (33) receives on the one hand the output of an OR gate (34), whose inputs correspond to the delayed signals (D) and (F) and on the other the outputs of the first and third AND gates (27, 31).
  8. Device according to claim 7, comprising a second analog-digital converter (50) controlled by the output of the flip-flop (33) and by the output of a second ramp generator (55), which is itself controlled by the output of a second divider (51) of the pulses of the second clock (H2).
EP95402202A 1994-10-04 1995-10-02 Time interval measuring device Expired - Lifetime EP0706100B1 (en)

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FR9411848A FR2725326B1 (en) 1994-10-04 1994-10-04 DEVICE FOR MEASURING THE DURATION OF A TIME INTERVAL
FR9411848 1994-10-04

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US7843771B2 (en) * 2007-12-14 2010-11-30 Guide Technology, Inc. High resolution time interpolator
CN110737189B (en) * 2019-11-05 2021-02-09 中国电子科技集团公司第四十四研究所 Pulse laser interval measuring circuit
CN112506031B (en) * 2020-11-30 2021-09-21 中国计量科学研究院 High-precision time interval measuring system for laser interference fringe signals

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US4912734A (en) * 1989-02-14 1990-03-27 Ail Systems, Inc. High resolution event occurrance time counter
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FR2725326A1 (en) 1996-04-05
US5717659A (en) 1998-02-10

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