EP0706100A1 - Time interval measuring device - Google Patents

Abstract

The circuit for measuring the time interval between a start signal (D) and an end signal (F) includes a first clock (H) which delivers pulses of period T, and a second clock whose pulses are shifted w.r.t. the first. A digital circuit (2, 3, 4) counts the number of clock pulses which are followed by an entire period T, between the start and end signals. An analogue circuit (6, 7, 12, 10, 13) determines the time fraction of a clock period beyond the integer number of periods counter, and converts this into digital format. A processing circuit (14) then determines the duration of the time interval.

Description

Technical area

The present invention relates to a device for measuring the duration of a time interval.

The field of the invention is that of chronometry, of the precise temporal measurement of a period of time, short or infinitely long, between a start signal and an end of measurement signal.

This type of problem arises in all devices where precise time measurement is necessary over very long periods, in particular in devices used in the field of laser telemetry.

State of the art

• soit à des technique de moyennage qui augmentent considérablement le temps d'acquisition par rapport au temps mesuré. Ce type de technique ne peut pas être employé dans le cas où le temps d'acquisition doit être limité, et, par ailleurs, le moyennage n'est possible que si le phénomène mesuré présente une stationnarité convenable relativement au temps de moyennage.
• à des techniques de type "vernier", ces techniques reposant sur le comptage des périodes d'une horloge, pour une mesure grossière, et sur la détermination d'un complément temporel par une méthode analogique qui donne la précision à la mesure. Une telle technique est décrite dans l'article intitulé "The vernier time-measuring technique" de Robert G. Baron (proceedings of the IRE, janvier 1957), mais cette technique rallonge d'une quantité non négligeable le temps de mesure (5µs de temps de mesure pour une résolution de 20 µs avec des horloges de 100 mégahertz). Cette technique limite donc le nombre de mesures possibles bien en-deçà de la cadence de réalisation de certains événements.

In the area of high-precision time measurement, use is made of:

• or to averaging techniques which considerably increase the acquisition time compared to the measured time. This type of technique cannot be used in the case where the acquisition time must be limited, and, moreover, averaging is only possible if the phenomenon measured has suitable stationarity relative to the averaging time.
• to "vernier" type techniques, these techniques based on counting the periods of a clock, for a rough measurement, and on the determination of a time complement by an analog method which gives the precision to the measurement. Such a technique is described in the article entitled "The vernier time-measuring technique "by Robert G. Baron (proceedings of the IRE, January 1957), but this technique extends the measurement time by a significant amount (5 µs of measurement time for a resolution of 20 µs with clocks of 100 megahertz) .This technique therefore limits the number of possible measurements well below the rate of realization of certain events.

The French patent application filed under the number 93 08145 (July 2, 1993) entitled "Device for measuring the duration of a time interval" describes a time measurement method which removes the ambiguity of counting d '' a clock and takes into account the problems of non-synchronism. This method is not suitable for the measurement of long time durations, greater than 10 µs, due to the discharge of a capacitor of the circuit which can cause a significant error over large measurement intervals, in particular for telemetry applications. at medium distance (more than 1 km).

Statement of the invention

The present invention aims to solve these problems.

• une première horloge qui délivre des impulsions avec une période T,
• un circuit numérique pour compter le nombre d'impulsions de la première horloge qui sont suivies par une période entière T et qui sont comprises entre le signal de début (D) et le signal de fin (F),
• un circuit analogique pour déterminer d'une part le temps t₁ séparant le signal (D) et le début de la première impulsion de la première horloge qui commence après (D) et d'autre part le temps t₂ séparant le signal de fin (F) de la fin de la dernière période de la première horloge qui s'achève avant (F), et apte à convertir les données analogiques obtenues en données numériques,
• un circuit de traitement, pour déterminer la durée de l'intervalle de temps à partir des données fournies par le circuit numérique et celles fournies par le circuit analogique préalablement converties en données numériques.

More specifically, it relates to a device for measuring the duration of a time interval between a start signal (D) and an end signal (F), characterized in that it comprises:

• a first clock which delivers pulses with a period T,
• a digital circuit for counting the number of pulses of the first clock which are followed by an entire period T and which are included between the start signal (D) and the end signal (F),
• an analog circuit for determining on the one hand the time t₁ separating the signal (D) and the start of the first pulse of the first clock which begins after (D) and on the other hand the time t₂ separating the end signal (F ) the end of the last period of the first clock which ends before (F), and capable of converting the analog data obtained into digital data,
• a processing circuit, for determining the duration of the time interval from the data supplied by the digital circuit and that supplied by the analog circuit previously converted into digital data.

This device makes it possible to measure very long time intervals with very high accuracy. In addition, the start (D) and end (F) signals can be completely asynchronous from the clock. This is interesting for applications in the field of telemetry of the "time of flight" type, in which (D) and (F) are given by the departure of a light pulse and by the reception of the pulse reflected on an object. , these two signals (D) and (F) possibly being asynchronous with respect to the clock.

• un circuit diviseur de fréquence, relié à la première horloge,
• un premier générateur de rampes commandé par le signal de sortie du circuit diviseur de fréquence,
• et un premier convertisseur analogique-numérique, recevant d'une part le signal engendré par le premier générateur de rampes et, d'autre part, les signaux de début (D) et de fin (F) de l'intervalle de temps à mesurer.

According to a particular embodiment of the invention, the analog circuit can also comprise:

• a frequency divider circuit, connected to the first clock,
• a first ramp generator controlled by the output signal of the frequency divider circuit,
• and a first analog-to-digital converter, receiving on the one hand the signal generated by the first ramp generator and, on the other hand, the start (D) and end (F) signals of the time interval to be measured .

According to another particular embodiment of the invention, the digital circuit is provided with a second clock, the pulses of which are offset from those of the first clock, the digital circuit also counts the number of pulses of the second clock which are followed by an entire period and which are between the start (D) and end (F) signal, the analog circuit determines on the one hand the time separating the signal (D) and the start of the first pulse of the second clock which begins after (D) and, on the other hand, the time separating the end signal (F) from the end of the last period of the second clock which ends before (F), and this circuit analog is able to convert the analog data obtained into digital data and the device also comprises means capable of determining which of the counts made on one of the two clocks (H₁, H₂) is to be taken into account, so as to solve to This ambiguity could lead to an error in counting a clock period.

Thus, it is possible to remove any ambiguity situation in the event that one of the signals (D) and (F) is confused with a clock pulse.

Other specific aspects and embodiments appear in the dependent claims

Brief description of the figures

• la figure 1 illustre le principe de la mesure d'un intervalle de temps, selon la présente invention,
• la figure 2 est un schéma d'un dispositif pour la mise en oeuvre de l'invention,
• la figure 3 illustre le principe de la méthode selon un mode particulier de réalisation de l'invention, dans le cas où des situations d'ambiguïté doivent être levées,
• la figure 4 est un schéma d'un autre dispositif pour la mise en oeuvre de l'invention selon un second mode particulier de réalisation.

In any case, the characteristics and advantages of the invention will appear better in the light of the description which follows. This description relates to the exemplary embodiments, given by way of explanation and without limitation, with reference to the appended drawings in which:

• FIG. 1 illustrates the principle of the measurement of a time interval, according to the present invention,
• FIG. 2 is a diagram of a device for implementing the invention,
• FIG. 3 illustrates the principle of the method according to a particular embodiment of the invention, in the case where ambiguity situations have to be resolved,
• FIG. 4 is a diagram of another device for implementing the invention according to a second particular embodiment.

Detailed description of embodiments

To measure the duration of a determined time interval, according to the invention, the coarse part of the time interval is measured digitally, and the fine part analogically. The parameters thus acquired are then combined to obtain the result. The time measurement is thus obtained by associating a digital quantity in the form of a number of clock periods counted, and analog quantities obtained by conversion of time into voltage amplitudes.

This principle is illustrated more precisely using the timing diagram of FIG. 1. We seek to measure the time interval t _v between a start pulse D and an end pulse to measure F.

For this, we use a basic clock H, of period T. We count the number n of clock pulses which are followed by an entire period T, and this for the duration t _v . The total time corresponding to the passage of this period is equal to nT. As the clock is not synchronous with the start signal D and end signal F, it is also necessary to determine on the one hand the time t₁, which elapses between the start signal D and the start of the first clock pulse which begins after D, and, on the other hand, the time t₂, which elapses between the end signal F and the end of the last clock period which ends before the signal F. To obtain the duration of the time interval t _v , it then suffices to add the three measured times: t₁ + nT + t₂.

·a.To determine t₁ and t₂, we use a triangular signal R, of period 2T, of amplitude A, and synchronous with the base clock of period T. At any time, if a is the amplitude measured on the ramp, the t elapsed since the start of the ramp is equal to $\frac{\mathbf{\text{T}}}{\mathbf{\text{AT}}}$

· A.

By sampling the ramps on the appearance of the start signal D and the end signal F, we obtain amplitudes a₁ and a₂ representative of t₁ and t₂ respectively.

·a₁.If the starting pulse occurs during a rising ramp, we then have: t₁ = $\frac{\mathbf{\text{T}}}{\mathbf{\text{AT}}}$

· A₁ .

·a₁.If the starting pulse occurs during a downward ramp, we have: t₁ = T- $\frac{\mathbf{\text{T}}}{\mathbf{\text{AT}}}$

· A₁ .

·a₂.If the end pulse F occurs on a rising ramp, we have: t₂ = $\frac{\mathbf{\text{T}}}{\mathbf{\text{AT}}}$

· A₂ .

·a₂.If the end pulse F occurs on a descending ramp, we have: t₂ = T- $\frac{\mathbf{\text{T}}}{\mathbf{\text{AT}}}$

· A₂ .

t₁ and t₂ are then digitized, which gives two corresponding values T₁ and T₂. We then obtain the duration of the time interval t _v = nT + T₁ + T₂.

A device for implementing the invention is shown in FIG. 2. A clock H delivers pulses of period T on one of the inputs of an AND gate, designated by the reference 2. This clock H can be produced from a quartz oscillator, operating for example at a frequency of 200 MHz. The other input of the AND gate receives a signal from the output Q of a flip-flop RS designated by the reference 4, on the input S from which the start signal D is sent, while the input R is driven by the end signal F. The assembly constituted by the AND gate, the flip-flop 4 and the clock H constitutes a digital measurement circuit making it possible to obtain a rough value of the time interval to be measured. This value is equal to nT where n is the number of clock periods T elapsed between the start signal D and the end signal F. It is counted in a counter 3.

In parallel, a division of the frequency of the signals of the clock H is carried out by a divider 6, constituted for example by a rocker, the output of this divider supplying a ramp generator 8. This generator can be produced by the load and the constant current discharge of a capacitor. The period and the slope of these ramps are very well defined. The output of the ramp generator 8 is sent to a fast analog-digital converter 10 (for example of the flash or fast sampler + converter type), another input of which receives a signal coming for example from a flip-flop 12, controlled by the signals D and F at the start and end of the period to be measured. Thus, the converter 10 takes the information on the amplitude of the ramp at the instants of start D and of end F of the time interval to be measured, as well as the information relating to the parity of the ramp at these instants, that is to say, its ascending or descending character. This converter provides information on the values T₁ and T₂. This information is stored in a memory 13.

The rough information relating to nT and the “fine” information relating to the intervals T₁ and T₂ are sent to a processing circuit 14 which calculates the duration t _v of the time interval to be measured.

This device makes it possible to obtain good accuracy, since it makes it possible to dispense with any synchronization of the start signals D and end signals F of measurement with respect to the clock H of the chronometer; it also overcomes the limited capacity of the chronometer to determine a small and a very large time difference, which can vary from a few picoseconds to infinity, due to its frequency which is fixed.

This device also makes it possible to determine large time intervals with constant precision, whatever the duration of this time interval. This is not true in the case of devices for measuring the duration of a time interval according to the prior art, in particular in the case of the device described in French patent application No. 93 08145 of July 2, 1993. Indeed, this latter device involves, at the start of measurement of the time interval, the discharge of a capacitor, and at the end of measurement of the time interval the charge of the same capacitor; however, the charge measured immediately after the arrival of the signal D can vary before the final part of the time interval to be measured is reached, just before the end signal F, and this all the more so since l The time interval to be measured is important. In the device according to the present invention, this problem is avoided by using recurrent ramps.

Finally, this type of device can be easily integrated to make a compact circuit.

A particular embodiment of the invention makes it possible to take account of the problems linked to the situations of ambiguity on the starting signal D and on the arrival signal F. These problems arise when one or the other of these signals , occur simultaneously with a rising or falling edge of the clock signals. The counter of the digital part of the device, part which determines the rough measurement of the time interval, can then count an additional clock pulse, which should not have been counted.

In order to solve this problem, the invention proposes a device which operates on the principle illustrated in FIG. 3. In accordance with what has already been explained above, a clock H₁ delivers signals of period T. A divider makes it possible to generate signals S₁, of period 2T, synchronized with the signals of the clock H₁. It is thus possible to generate rising and falling ramps R₁, of amplitude A. A delay device makes it possible to generate a second clock signal H₂, from the signal H₁, the signals H₂ being offset by T / 2 relative to the signals from H₁. Thus, a falling edge of a slot of H₂ corresponds to a rising edge of a slot of H₁, as can be seen in FIG. 3. This clock signal H₂ makes it possible to generate, in the same way as it has been explained above for the clock H₁, a signal S₂ of period 2T, which will itself control a ramp R₂ of the same amplitude A as the ramp R₁. When the measurement start signal D occurs, the two ramps R₁ and R₂ are sampled simultaneously. If for example there is ambiguity between D and H₁, that is to say if the signal D is superimposed on a rising edge of a slot of H₁, there cannot be simultaneously ambiguity between the signal D and the signals generated by H₂, due to the offset of a half-period between the two channels. Consequently, it suffices to identify the clock which is not in an ambiguous situation with the starting signal D, and then to retain only the sampled value of the corresponding ramp R to determine t₁. For example, if the ambiguity situation arises between the starting signal D and the clock H₁, the valid clock to determine the measurement of t₁ is the clock H₂ and the value to be taken into account is that measured on the R₂ ramp.

The same goes for any ambiguity situation on the signal F. When the end signal F occurs, the two ramps R₁ and R₂ are sampled simultaneously. We take for t₂ the value of the ramp R₁ or R₂ from the clock H₁ or H₂ which does not have any ambiguity with the signal F.

In the case where an ambiguity situation exists simultaneously on D and F, it is possible to add a third circuit with a clock H₃ offset from H₂ and H₁.

In the case where there is no ambiguity, neither with the clock H₁ nor with the clock H₂, the time values obtained (t₁ or t₂) will be taken indifferently on one of the two circuits corresponding to the two clocks.

The device corresponding to this particular embodiment of the invention is illustrated in FIG. 4. In this figure, in a first block 24, a first counter 25 receives on its CE authorization input a counting order coming from a flip-flop 23 and on its input C the clock signals H₁. Data from the first counter 25 are transmitted to a processing circuit 22 via a routing circuit 36 controlled by an OR circuit 32.

The D flip-flops 26 and 30 receive the D and F signals via an OR 40, 41 function on their D input. The flip-flop 23, which delivers the CE authorization signal, is also controlled by the D and F signals both delayed by an amount close to 3 propagation times in gates by devices 19, 42 which consist for example of delays in logic gates. The first AND circuit 27 performs the AND function of the output of the flip-flop 26 and of the clock H₂; the signals of the latter are obtained from H₁ and a delay circuit 18, constituted for example by propagation times in gates.

In the second block 28, a second counter 29 receives on its CE authorization input a counting order coming from the flip-flop 23. The data from this counter 29 is transmitted to the processing circuit 22 via the circuit 36. The second flip-flop type D 30 works as described above. The second AND circuit 31 performs the AND function between the output of circuit 30 and the clock H₁.

The output of the circuit 32 controls the operation of the routing circuit 36 to obtain the reading of the counter 25 or 29, of which the associated D type flip-flop (26 or 30) did not switch first. It detects the first of the flip-flops 26 or 30 which has switched over and it authorizes the reading of the counter whose flip-flop has not changed state.

If there is a situation of uncertainty, for example at the start of the counting, for one or other of the counters, the first of the presence identification circuits 26, 30 which switches validates the choice between the H₁ or H₂ clocks. The validated counter is left unchanged, on the other hand the other counter is reset to zero before the arrival of the second clock pulse according to the signal D. This is achieved by circuits 44, 45 and 46, 47 respectively for the first and second counters. Circuits 44 and 46 are AND circuits, circuits 45 and 47 are time formatting.

A flip-flop 33 (RS type flip-flop) receives on its SET input the output of an OR circuit 34 whose inputs correspond to the signals D and F delayed by circuits 42 and 19. The flip-flop 33 receives on its other input the outputs of two doors AND 27, 31.

This flip-flop 33 controls an input of an analog-digital converter 50 and an input of an analog-digital converter 52. Another input of each of these converters 50, 52 is connected to the clock H₁ (respectively H₂) by l 'through a flip-flop 51 (respectively 53) which makes it possible to generate a signal S₁ respectively S₂ of period 2T, and of a ramp generator 55 (respectively 57) for generating a ramp R1 (respectively R2). Downstream of the analog-digital converters, there are two memories 60, 62 and a switching circuit 56 controlled by the circuit 32.

Claims (8)

Device for measuring the duration of a time interval between a start signal (D) and an end signal (F), characterized in that it comprises: a first clock (H, H₁) which delivers pulses with a period T, as well as a second clock (H₂), the pulses of which are offset from those of the first clock (H₁), - a digital circuit (2, 3, 4; 20) for counting the number of pulses of the first clock which are followed by an entire period T and which are between the start signal (D) and the end signal ( F), the digital circuit (20) also counting the number of pulses of the second clock which are followed by an entire period T and which are included between the start (D) and end (F) signal, - an analog circuit (6, 8, 12, 10, 13; 21) to determine, on the one hand, the time t₁ separating the signal (D) and the start of the first pulse of the first clock which begins after (D ) and, on the other hand, the time t₂ separating the end signal (F) from the end of the last period of the first clock which ends before (F), as well as, on the one hand, the time separating the signal (D) and the start of the first pulse of the second clock which begins after (D) and, on the other hand, the time separating the end signal (F) from the end of the last period of the second clock which ends before (F), the analog circuit being moreover capable of converting the analog data obtained into digital data, - a processing circuit (14, 22), for determining the duration of the time interval from the data supplied by the digital circuit and those supplied by the analog circuit previously converted into digital data, - means capable of determining which of the counts made on one of the two clocks (H₁, H₂) is to be taken into account, so as to resolve any ambiguity situation which could lead to a counting error of a period d 'clock. Device according to claim 1, the analog circuit further comprising: - a frequency divider circuit (6; 53), connected to the first clock, - a first ramp generator (8; 57) controlled by the output signal of the frequency divider circuit (6; 53), - and a first analog-digital converter (10; 52), receiving on the one hand the signal generated by the first ramp generator (8; 57) and, on the other hand, the start (D) and end signals (F) of the time interval to be measured. Device according to claim 2, the start (D) and end (F) signals of the time interval to be measured being transmitted to the first analog-digital converter (10; 52) via a flip-flop (12 ; 33). Device according to one of claims 1 to 3, the digital circuit (20) also comprising: - an RS type flip-flop (23), controlled on its SET input by the start signal (D) delayed after passing through a first delay circuit (42) and, on its RESET input by the end of delay signal (F ) delayed, after passing through a delay circuit (19), - a first block (24) comprising a first counter (25), a first D-type flip-flop (26), a first AND circuit (27), a first OR circuit (40), a second AND circuit (44), a means for temporal shaping of the signal (45), - and a second block (28) comprising a second counter (29), a second D-type flip-flop (30), a third AND circuit (31), a second OR circuit (41), a fourth AND circuit (46), a means for temporal shaping of the signal (47), - A circuit (32) capable of performing an OR function to detect which of the outputs of the flip-flops (26, 30) has switched first. Device according to claim 4, in which, in the first block (24), the first counter (25) receives on its CE authorization input a counting order coming from the flip-flop (23) of RS type, the data output from the first counter (25) are transmitted to the processing circuit (22) via a switching circuit (36) controlled by the OR circuit (32), the first D-type flip-flop (26), controlled by the first OR circuit (40), receives on the one hand the start signal (D) and the interval end signal (F), and on the other hand, the pulses of the first clock (H₁), and the first AND circuit ( 27) performs the AND function between, on the one hand, the output of the first D type flip-flop (26) and, on the other hand, the pulses of the second clock (H₂). Device according to one of claims 4 or 5, in which, in the second block (28), the second counter (29) receives on its authorization input (CE) a counting order coming from the flip-flop (23) of RS type , the data of this counter (29) are transmitted to the processing circuit (22) via a switching circuit (36), the second D-type flip-flop (30), controlled by the second OR circuit ( 41) receives on the one hand the start signal (D) and the interval end signal (F) and, on the other hand, the pulses of the second clock (H₂), and the second AND circuit (31) performs the AND function between on the one hand the output of this flip-flop D (30) and pulses of the first clock (H₁). Device according to Claims 3 and 4, in which the flip-flop (33) receives on the one hand the output of an OR circuit (34) whose inputs correspond to the delayed signals (D) and (F) and, on the other hand , the outputs of the first and third AND circuits (27, 31). Device according to claim 7, comprising a second analog-digital converter (50) controlled by the output of the rocker (33) and by the output of a second ramp generator (55) itself controlled by the output of a second divider (51) of the pulses of the second clock (H₂).

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