WO2019024064A1 - 定时方法、时钟设备和终端设备 - Google Patents

定时方法、时钟设备和终端设备 Download PDF

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Publication number
WO2019024064A1
WO2019024064A1 PCT/CN2017/095918 CN2017095918W WO2019024064A1 WO 2019024064 A1 WO2019024064 A1 WO 2019024064A1 CN 2017095918 W CN2017095918 W CN 2017095918W WO 2019024064 A1 WO2019024064 A1 WO 2019024064A1
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WIPO (PCT)
Prior art keywords
counter
timing
clock
clock device
duration
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PCT/CN2017/095918
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English (en)
French (fr)
Inventor
尹甜
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2017/095918 priority Critical patent/WO2019024064A1/zh
Priority to CN201780000862.6A priority patent/CN109643142B/zh
Priority to EP17908763.0A priority patent/EP3462276A4/en
Priority to US16/177,426 priority patent/US10498524B2/en
Publication of WO2019024064A1 publication Critical patent/WO2019024064A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H03L7/1978—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider using a cycle or pulse removing circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0251—Power saving arrangements in terminal devices using monitoring of local events, e.g. events related to user activity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present application relates to the field of information technology, and more particularly, to a timing method, a clock device, and a terminal device.
  • Bluetooth Low Energy (BLE) technology plays an important role in wireless transmission with low cost and low power requirements. Because of its low power consumption, for example, a button cell can work continuously for one to several years. Therefore, it is widely used in many fields such as medical treatment, home and entertainment.
  • the current protocol specifies that the timing of the clock device used to implement timing is 1.25 ms ⁇ N, that is, every 1.25 ms ⁇ N reaches a timing point.
  • N is an integer that is not 0.
  • the values of N in different application scenarios may be different.
  • N may be called Interval.
  • 1.25 ms ⁇ N may be called Connection Interval (ConnInterval) or timing duration.
  • ConnInterval Connection Interval
  • Fig. 1 the place marked by the black triangle of Fig. 1 is the place to be timed, and the timing points are respectively 1.25ms ⁇ N ⁇ M, and M is a positive integer.
  • This clock cycle can also be referred to as an oscillation cycle, which is the reciprocal of the clock frequency.
  • Q 1 is not an integer, that is, 1.25 ms is not an integer multiple of the clock period, it is difficult for the clock device to achieve accurate timing.
  • the embodiment of the present application provides a timing method, a clock device, and a terminal device.
  • the ratio of the constant C (for example, 1.25 ms) to the clock period is not an integer, accurate timing can still be effectively implemented.
  • a timing method is provided, the method being applied to a clock device having a clock period of T, comprising:
  • the timing point is determined according to the timing duration Q 2 ⁇ T ⁇ N, and each time 1/
  • the clock device includes a first counter for recording the number of clock cycles T elapsed, and a second counter for recording the passed The number of the first durations;
  • the time period of the clock device is adjusted once every P first time durations, including: when the number of the clock cycles T recorded by the first counter is equal to Q 2 , The first counter is set to zero, and the number of the first duration recorded by the second counter is incremented by one; when the number of the first duration recorded by the second counter reaches P, The timing adjustment is described and the second counter is set to zero.
  • the clock device further includes a third counter, where the third counter is used to record the number of the first durations that are passed,
  • the timing of the clock device including: when the number of the clock cycles T recorded by the first counter is equal to Q 2 , The number of the first duration recorded by the third counter is increased by one; when the number of the first duration recorded by the third counter reaches N, it is determined that a timing point is reached, and the third counter is set zero.
  • the timing adjustment is performed every P first time durations, including: reducing the timing of the clock device by one clock cycle T every P first time durations.
  • the timing error of the Mth timing point of the clock device is Mod is the remainder, and M is a positive integer.
  • Performing the adjustment of the timing of the clock device once every P first first durations including: reducing the timing of the clock device by one clock cycle T every time the P first first durations are passed .
  • Performing the adjustment of the timing of the clock device once every P first first durations including: adjusting the timing of the clock device by one clock cycle T every time the P first first durations are passed .
  • the constant C 1.25 ms.
  • a clock device comprising means for performing the method of the first aspect or any of the possible implementations of the first aspect.
  • a clock device in a third aspect, includes a processor and a memory.
  • the memory is used to store instructions that the processor uses to execute the instructions.
  • the processor executes the instructions stored by the memory, the execution causes the processor to perform the method of the first aspect or any of the possible implementations of the first aspect.
  • a computer readable medium for storing a computer program comprising instructions for performing the method of the first aspect or any of the possible implementations of the first aspect.
  • a timing chip comprising the clock device in any of the possible implementations of the second aspect or the second aspect.
  • a terminal device comprising the clock device in any of the foregoing possible implementations of the second aspect or the second aspect.
  • the terminal device can be, for example, a Bluetooth device.
  • Figure 1 is a timing diagram.
  • FIG. 2 is a schematic flowchart of a timing method of an embodiment of the present application.
  • FIG. 3 is a timing diagram of an embodiment of the present application.
  • FIG. 4 is a schematic diagram of timing adjustment of an embodiment of the present application.
  • FIG. 7 is a schematic block diagram of a clock device according to an embodiment of the present application.
  • FIG. 8 is a schematic block diagram of a clock device according to an embodiment of the present application.
  • FIG. 9 is a schematic block diagram of a chip of an embodiment of the present application.
  • Figure 1 is a timing diagram.
  • the timing duration (which can be called ConnInterval) of the clock device used to implement timing is 1.25 ms ⁇ N, that is, every 1.25 ms ⁇ N reaches a timing point.
  • Q 1 is an integer.
  • T the clock period
  • T the T value is small at this time, which will cause the power consumption of the crystal oscillator circuit of the clock device to be too large
  • T the clock period
  • the consumption is reduced, but at this time the clock device needs to use a 32k crystal, which is uncommon and therefore expensive.
  • clock devices with low power and low cost, such as clock devices including 32.768k crystals.
  • the clock cycles of these clock devices usually cannot satisfy Q 1 as an integer. . If Q 1 is not an integer, it is difficult for the clock device to achieve precise timing. Therefore, the embodiment of the present application proposes that when the ratio Q 1 of the constant C (for example, 1.25 ms described above) and the clock period T is not an integer, the clock device is clocked in real time according to the ratio Q 1 and the clock period T during the timing. Adjust to effectively achieve precise timing.
  • FIG. 2 shows a schematic flow chart of the timing method 200 of the embodiment of the present application. As shown in FIG. 2, the method 200 can include:
  • a timing point is determined based on the timing duration of the clock device.
  • the clock device reaches a timing point every time a timing period elapses, and the timing duration of the clock device is N times the first duration.
  • the first duration is equal to Q 2 ⁇ T. Since the constant C/T is not an integer (ie, Q 1 is not an integer), Q 2 ⁇ T will be or As the first time length instead of Q 1 ⁇ T, the clock device considers that it reaches a timing point every N times of Q 2 ⁇ T, thereby achieving accurate timing.
  • FIG. 3 is a timing diagram of an embodiment of the present application.
  • each time N times of the first time that is, Q 2 ⁇ T
  • the place marked by the black triangle of FIG. 3 is the place to be timed
  • the timing points are respectively Q 2 ⁇ T.
  • the first timing point and the second timing point are different by one timing duration
  • the timing duration is equal to N firsts.
  • the duration is equal to Q 2 ⁇ T.
  • the timing duration is Q 2 ⁇ T ⁇ N.
  • the timing offset is Q 2 ⁇ T ⁇ N.
  • the embodiment of the present application adjusts the timing deviation by performing 220 to achieve precise timing of the clock device.
  • the timing of the clock device is adjusted once every P first time periods.
  • the clock device can perform a timing adjustment every time the timing deviation is accumulated to one clock cycle T.
  • the clock device passes the P first time duration, the accumulated deviation reaches one clock cycle T, so that the timing time is adjusted once.
  • the timing point is determined according to the timing duration Q 2 ⁇ T ⁇ N, and each time 1/
  • the actual timing point of the clock device is Q 2 ⁇ T ⁇ N ⁇ M, and the real timing point should be C ⁇ N ⁇ M or (Q 1 ⁇ T) ⁇ N ⁇ M.
  • the clock device can record the number i of the first duration that has passed, and every time the 1/
  • 4 shows an adjustment period including 1/
  • , the position indicated by the black dot in Fig. 4 is the position to be adjusted, at which time the clock device adjusts the timing One clock cycle T.
  • is passed, the timing is adjusted once, and the amount of time for each adjustment is equal to one clock period T.
  • the timing of the clock device is adjusted once every P first time durations, which may include the following two situations:
  • the clock time of the clock device is slowed by one clock cycle T every P first time periods.
  • the clock device can pause for one clock cycle T, thereby adjusting the timing time by one clock cycle T.
  • the clock time of the clock device is adjusted by one clock cycle T every time P first time passes.
  • the timing duration to the next timing point can be determined as Q 2 ⁇ T ⁇ NT.
  • the clock device can implement timing adjustment in 220 by setting different counters.
  • the clock device comprises a first counter and a second counter, the first counter being used for The number of clock cycles T elapsed is recorded, and the second counter is used to record the number of first durations passed.
  • 220 may include 221 and 222.
  • the condition that the count value is incremented by one is that the current counter value of the second counter is not equal to P-1, and the condition of zeroing is that the count value of the first counter reaches Q 2 -1.
  • the condition of adding 1 is that the count value of the first counter reaches Q 2 -1, and the condition of setting the zero is that the count value of the second counter reaches P-1.
  • the first counter records Q 2 clock cycles T (ie, records a first duration), then the count value of the second counter is incremented by 1, and the second counter records the first time duration of the clock device. Make an adjustment.
  • the number of clock cycles T elapsed and the number of first time periods elapsed are respectively recorded by the two counters, so that the timing adjustment can be performed in real time during the process of determining the timing points according to the timing duration, thereby realizing accurate timing.
  • the clock device may further include a third counter, where the third counter is used to record the number of first durations passed, and at this time, 210 may further include 211 and 212.
  • the third counter is also used to count the elapsed first duration, which is different from the second counter in that the second counter is time-adjusted according to the number of first durations recorded, and the third counter
  • the timing point is determined according to the number of the first durations recorded therein, and the count range of the third counter is from 0 to N-1 (a total of N count values).
  • the condition that the count value is incremented by one is that the count value of the first counter reaches Q 2 -1
  • the condition of zero is that the count value of the second counter reaches N-1.
  • the first counter records Q 2 clock cycles T (Q 2 clock cycles T is equal to a first duration), the count value of the third counter is incremented by 1, and the third counter records the clock for each of the first first durations.
  • the device is determined to arrive at a timing point.
  • the determination of the timing point of the clock device can be achieved based on the number of first time periods elapsed recorded by the third counter.
  • the timing error of the Mth timing point of the clock device may be expressed as which is
  • mod is the remainder, that is, mod(N ⁇ M, P) represents the remainder obtained by dividing (N ⁇ M) by P, and M is a positive integer.
  • the actual timing point of the clock device is The real timing point should be 1.25 ⁇ N ⁇ M.
  • first half of the formula (41 ⁇ T) ⁇ N ⁇ M is the actual timing point of the clock device, and the second half The deviation between the actual timing point and the corresponding real timing point. It can be seen that when N ⁇ M is equal to an integral multiple of 25, the deviation between the actual timing point and the real timing point is an integer multiple of the clock period T. N ⁇ M can be understood as the total number of first time elapsed. When each 25 first time periods elapse, the actual timing point and the real timing point are different by one clock period T, so a timing adjustment is performed.
  • the first counter Cnt1 is used to record the number of first cycles passed
  • the second counter Cnt2 is used to record the number i of the first duration passed, the first duration being 41 ⁇ T.
  • the second counter Cnt The count value of 2 is incremented by 1, and the count value of the first counter Cnt1 is set to zero.
  • the count value of the second counter Cnt2 reaches 0 from 24 (a total of 25 count values)
  • the count value of the second counter Cnt2 is set to zero, and the clock device performs a timing adjustment to shorten the time of the clock by one clock period T, such as a clock.
  • the device pauses timing Tms at the beginning of the time.
  • the time point indicated by the black dot in Fig. 5 is the timing at which the timing adjustment is performed.
  • the third counter Cnt3 is used to record the number i of the first duration that has passed, and the count value of the first counter Cnt1 reaches 40 from 0 (a total of 41 count values), and the third counter Cnt3 The count value is incremented by 1, and the count value of the first counter Cnt1 is set to zero.
  • the count value of the third counter Cnt3 reaches 0-1 from N (a total of N count values)
  • the count value of the third counter Cnt3 is set to zero, and the clock device determines that a timing point is reached.
  • the time point indicated by the black triangle in Fig. 6 is a timing point.
  • the 32.768k crystal causes 1.25ms to be an integer multiple of the clock period T of the clock device, the 32.768k crystal has low power consumption and low price.
  • accurate timing can be realized using a 32.768k crystal, thereby simultaneously satisfying low power consumption and low cost timing.
  • the clock device can also use other crystals having different clock cycles for timing, which is not limited herein.
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • clock device in the embodiment of the present application may perform the method in the embodiment of the present application, and have the function of executing the corresponding method.
  • FIG. 7 shows a schematic block diagram of a clock device 700 of an embodiment of the present application.
  • the clock device 700 can include a determining unit 710 and an adjusting unit 720. among them:
  • the timing point is determined according to the timing duration Q 2 ⁇ T ⁇ N, and each time passes 1/
  • the clock device further includes a first counter and a second counter;
  • the first counter is configured to record the number of clock cycles T elapsed, and when the number of the clock cycles T recorded by the first counter is equal to Q 2 , the first counter is set to zero;
  • the second counter is configured to record the number of the first durations that have passed, wherein when the number of clock cycles recorded by the first counter is equal to Q 2 , the second counter will record The number of the first duration is increased by 1, and when the number of the first duration recorded by the second counter reaches P, the second counter is set to zero;
  • the adjusting unit 720 is specifically configured to: when the number of the first durations recorded by the second counter reaches P, adjust the timing of the clock device once.
  • the clock device further includes a third counter
  • the third counter is configured to record the number of the first durations that have passed, wherein when the number of clock cycles T recorded by the third counter is equal to Q 2 , the third counter will record The number of the first duration is increased by 1, and when the number of the first duration recorded by the third counter reaches N, the third counter is set to zero;
  • the determining unit 710 is specifically configured to: when the number of the first durations recorded by the third counter reaches N, determine to reach a timing point.
  • the adjusting unit 720 is specifically configured to: when the P first first durations pass, reduce the timing of the clock device by one clock cycle T.
  • the adjusting unit 720 is specifically configured to: adjust the timing of the clock device by one clock cycle T every time the P first first durations are passed
  • the timing error of the Mth timing point of the clock device is Mod is the remainder, and M is a positive integer.
  • the constant C 1.25 ms.
  • FIG. 8 shows a schematic block diagram of a clock device 800 of an embodiment of the present application.
  • the clock device 800 includes a processor 810 and a memory 820.
  • the processor 810 is configured to execute an instruction stored by the memory 820, and the execution of the instruction causes the processor 810 to perform the following operations:
  • the clock device further includes a first counter and a second counter;
  • the first counter is configured to record the number of clock cycles T elapsed, and when the number of the clock cycles T recorded by the first counter is equal to Q 2 , the first counter is set to zero;
  • the second counter is configured to record the number of the first durations that have passed, wherein when the number of clock cycles recorded by the first counter is equal to Q 2 , the second counter will record The number of the first duration is increased by 1, and when the number of the first duration recorded by the second counter reaches P, the second counter is set to zero;
  • the processor 810 is specifically configured to: when the number of the first durations recorded by the second counter reaches P, adjust the timing of the clock device once.
  • the third counter is configured to record the number of the first durations that are passed, wherein when the number of clock cycles T recorded by the third counter is equal to Q 2 , the third The counter adds 1 to the number of the first durations recorded, and when the number of the first durations recorded by the third counter reaches N, the third counter is set to zero;
  • the processor 810 is specifically configured to:
  • the processor 810 is specifically configured to: when the P first first durations pass, reduce the timing of the clock device by one clock cycle T.
  • the processor 810 is specifically configured to: adjust the timing of the clock device by one clock cycle T every time the P first first durations are passed.
  • the timing error of the Mth timing point of the clock device is Mod is the remainder, and M is a positive integer.
  • the constant C 1.25 ms.
  • the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), and application specific integrated circuits (ASICs). , off-the-shelf programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory can include read only memory and random access memory and provides instructions and data to the processor.
  • a portion of the memory may also include a non-volatile random access memory.
  • the memory can also clock information about the timing parameters associated with the device.
  • each step of the above method may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the steps of the positioning method disclosed in the embodiments of the present application may be directly implemented by the hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.
  • FIG. 9 is a schematic structural diagram of a timing chip of an embodiment of the present application.
  • the timing chip 900 of FIG. 9 includes an input interface 901, an output interface 902, at least one processor 903, and a memory 904.
  • the input interface 901, the output interface 902, the processor 903, and the memory 904 are interconnected by an internal connection path.
  • the processor 903 is configured to execute code in the memory 904.
  • the processor 903 can implement the method 200 performed by the clock device in the method embodiment. For the sake of brevity, it will not be repeated here.
  • the embodiment of the present application further provides a terminal device, which may include any clock device or timing chip in the foregoing embodiment of the present application.
  • the clock device is a Bluetooth device.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one detecting unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

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Abstract

一种定时方法和时钟设备。该方法包括：根据时钟设备的定时时长确定定时点，其中，所述时钟设备的时钟周期为T，所述定时时长为第一时长的N倍，所述第一时长等于Q2×T，Q2=⌈Q1⌉或者Q2=⌊Q1⌋，Q1=C/T，N为正整数，Q1不为整数，C为常量（210）；每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，其中，每次调整的时间量为一个时钟周期T，P=1/|Q2-Q1|（220）。从而在常量C（例如1.25ms）与时钟周期的比值不为整数时，仍能够有效地实现精确定时。采用该方法，能够在常量C（例如1.25ms）与时钟周期的比值不为整数时有效地实现精确定时。

Description

定时方法、时钟设备和终端设备 技术领域
本申请涉及信息技术领域，并且更具体地，涉及一种定时方法、时钟设备和终端设备。
背景技术
低功耗蓝牙(Bluetooth Low Energy，BLE)技术在低成本低功耗需求的无线传输中占有重要地位，由于其功耗极低，比如一节纽扣电池可使其连续工作一年至数年，因而被广泛应用于医疗、家居、娱乐等诸多领域。
对于低功耗蓝牙设备，目前协议规定用来实现定时的时钟设备的定时时长为1.25ms×N，即每经过1.25ms×N则到达一个定时点。其中N为任意不为0的整数，不同应用场景下的N的取值可以不同，N可以称为间隔(Interval)，1.25ms×N可以称为连接间隔(Connection Interval，ConnInterval)或者定时时长。如图1所示，图1的黑色三角形所标识出来的地方就是要定时的地方，定时点分别为1.25ms×N×M，M为正整数。
不同时钟设备的时钟频率不同，因而时钟周期也不同。该时钟周期也可以称为振荡周期，时钟周期为时钟频率的倒数。为了尽可能满足精度要求，时钟设备通常采用时钟周期T＝1.25ms/Q1进行精确定时，Q1为正整数。但是在某些情况下，当Q1不为整数时，即1.25ms不是时钟周期的整数倍时，时钟设备就很难实现精确的定时。
发明内容
本申请实施例提供了一种定时方法、时钟设备和终端设备，在常量C(例如1.25ms)与时钟周期的比值不为整数时，仍能够有效地实现精确定时。
第一方面，提供了一种定时方法，所述方法应用于时钟周期为T的时钟设备，包括：
根据时钟设备的定时时长确定定时点，其中，所述时钟设备的时钟周期为T，所述定时时长为第一时长的N倍，所述第一时长等于Q2×T，
Figure PCTCN2017095918-appb-000001
或者
Figure PCTCN2017095918-appb-000002
Q1＝C/T，N为正整数，Q1不为整数，C为常量，
Figure PCTCN2017095918-appb-000003
为向上 取整，
Figure PCTCN2017095918-appb-000004
为向下取整；
每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，其中，每次调整的时间量为一个时钟周期T，P＝1/|Q2-Q1|。
因此，在定时过程中，若常量C(例如1.25ms)与时钟周期T的比值Q1不为整数，则根据定时时长Q2×T×N确定定时点，并且每经过1/|Q2-Q1|个Q2×T时长后进行一次计时调整，从而保证计时误差维持在可接受范围内而不会随着时间的增加而增大，实现了时钟设备的精确定时。并且能够同时满足低功耗与低成本的定时。
在一些可能的实现方式中，所述时钟设备包括第一计数器和第二计数器，所述第一计数器用于记录所经过的时钟周期T的个数，所述第二计数器用于记录所经过的所述第一时长的个数；
其中，所述每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，包括：当所述第一计数器记录的所述时钟周期T的个数等于Q2时，将所述第一计数器置零，并将所述第二计数器记录的所述第一时长的个数加1；当所述第二计数器记录的所述第一时长的个数达到P时，进行所述计时调整，并将所述第二计数器置零。
在一些可能的实现方式中，所述时钟设备还包括第三计数器，所述第三计数器用于记录所经过的所述第一时长的个数，
其中，每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，包括：当所述第一计数器记录的所述时钟周期T的个数等于Q2时，将所述第三计数器记录的所述第一时长的个数加1；当所述第三计数器记录的所述第一时长的个数达到N时，确定到达一个定时点，并将所述第三计数器置零。
在一些可能的实现方式中，所述每经过P个第一时长进行一次计时调整，包括：每经过P个所述第一时长，将所述时钟设备的计时时间调慢一个时钟周期T。
在一些可能的实现方式中，所述时钟设备的第M个定时点的计时误差为
Figure PCTCN2017095918-appb-000005
mod为取余，M为正整数。
在一些可能的实现方式中，
Figure PCTCN2017095918-appb-000006
所述每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，包括：每经过P个所述第一时长，将所述时钟设备的计时时间调慢一个时钟周期T。
在一些可能的实现方式中，
Figure PCTCN2017095918-appb-000007
所述每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，包括：每经过P个所述第一时长，将所述时钟设备的计时时间调快一个时钟周期T。
在一些可能的实现方式中，常量C＝1.25ms。
在一些可能的实现方式中，1/T＝32.768，P＝25。
第二方面，提供了一种时钟设备，包括执行第一方面或第一方面的任意可能的实现方式中的方法的模块。
第三方面，提供了一种时钟设备，包括处理器和存储器。存储器用于存储指令，处理器用于执行该指令。该处理器执行该存储器存储的指令时，该执行使得该处理器执行第一方面或第一方面的任意可能的实现方式中的方法。
第四方面，提供了一种计算机可读介质，用于存储计算机程序，该计算机程序包括用于执行第一方面或第一方面的任意可能的实现方式中的方法的指令。
第五方面，提供了一种计时芯片，该计时芯片包括上述第二方面或第二方面的任意可能的实现方式中的时钟设备。
第六方面，提供了一种终端设备，该终端设备包括上述第二方面或第二方面的任意可能的实现方式中的时钟设备。该终端设备例如可以为蓝牙设备。
附图说明
图1为定时示意图。
图2时本申请实施例的定时方法的示意性流程图。
图3是本申请实施例的定时示意图。
图4是本申请实施例的计时调整的示意图。
图5是C＝1.25ms，T＝1/32.768时的计时调整的示意图。
图6是C＝1.25ms，T＝1/32.768时的定时示意图。
图7是本申请实施例的时钟设备的示意性框图。
图8是本申请实施例的时钟设备的示意性框图。
图9是本申请实施例的芯片的示意性框图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
图1为定时示意图。用来实现定时的时钟设备的定时时长(可以称为ConnInterval)为1.25ms×N，即每经过1.25ms×N则到达一个定时点。如图1所示，图上黑色三角形所标识出来的位置即是要定时的地方，定时点分别为1.25ms×N×M，其中M＝0,1,2……，∞。
不同时钟设备的时钟频率不同，因而时钟周期也不同。为了尽可能满足高精度要求，时钟设备通常采用时钟周期T＝1.25ms/Q1进行精确定时，这里Q1为1.25ms与时钟周期T的比值。
现有技术中为了保证时钟设备的计时精度，会使Q1为整数。目前采用两种方式使Q1为整数，即让1.25ms等于时钟周期的整数倍。一种方法是采用时钟周期T<1us，但此时T值很小，会导致时钟设备的晶振电路的功耗过大；另一种方法是采用时钟周期T＝62.5us，虽然晶振电路的功耗降低了，但此时时钟设备需要使用32k晶体才能实现，该晶体不常见，因而价格昂贵。
为了同时满足时钟设备的低功耗需求以及低成本需求，可以考虑采用低功率且低成本的某些时钟设备例如包括32.768k晶体的时钟设备，这些时钟设备的时钟周期通常不能满足Q1为整数。若Q1不为整数，时钟设备就很难实现精确定时。因此，本申请实施例提出在常量C(例如上述的1.25ms)与时钟周期T的比值Q1不为整数时，在定时过程中根据该比值Q1和时钟周期T对时钟设备进行实时的计时调整，从而有效地实现精确定时。
图2示出了本申请实施例的定时方法200的示意性流程图。如图2所示，该方法200可以包括：
在210中，根据该时钟设备的定时时长确定定时点。
其中，该时钟设备的时钟周期为T，该定时时长为第一时长的N倍，该第一时长等于Q2×T，
Figure PCTCN2017095918-appb-000008
或者
Figure PCTCN2017095918-appb-000009
Q1＝C/T，N为正整数，Q1不为整数，C为常量，
Figure PCTCN2017095918-appb-000010
为向上取整，
Figure PCTCN2017095918-appb-000011
为向下取整。
具体地说，该时钟设备每经过一个定时时长到达一个定时点，时钟设备的定时时长为第一时长的N倍。在本申请实施例中，该第一时长等于Q2×T。由于常量C/T不为整数(即Q1不为整数)，因而将Q2×T(即
Figure PCTCN2017095918-appb-000012
或者
Figure PCTCN2017095918-appb-000013
)作为第一时长而不是Q1×T，该时钟设备每经过N个Q2×T则认为到达一个定时点，从而实现准确的定时。该常量C例如可以为协议中的1. 25ms，那么此时Q1＝1.25/T。
图3所示为本申请实施例的定时示意图。如图3所示，每经过N个第一时长即Q2×T，则认为到达一个定时点，图3的黑色三角形所标识出来的地方就是要定时的地方，定时点分别为Q2×T×N×M，其中M＝0,1,2……，∞。例如，M＝1时为第一个定时点，M＝2时为第二个定时点，第一个定时点与第二个定时点之间相差一个定时时长，该定时时长等于N个第一时长，该第一时长等于Q2×T。
由于在确定定时点的过程中，是按照第一时长为Q2×T来进计时的，定时时长为Q2×T×N。因而在210中确定的实际的定时点与真实定时点之间存在一定的计时偏差。例如图3中所示的M＝1的定时点与M＝1时的真实定时点之间相差Q2×T×N-Q1×T×N，M＝2的定时点与对应的真实定时点之间相差Q2×T×N×2-Q1×T×N×2，该计时偏差会随着时间的增加而累积，当M＝i时，第i个定时点与对应的真实定时点之间的偏差为Q2×T×T×N×i-Q1×T×T×N×i。
因此，本申请实施例通过执行220来对该计时偏差进行调整，以实现该时钟设备的精确定时。
在220中，每经过P个第一时长，对该时钟设备的计时时间进行一次调整。
其中，每次调整的时间量为一个时钟周期T，P＝1/|Q2-Q1|。
具体地说，由于时钟设备进行计时调整的最小单位为一个时钟周期T，因而每当计时偏差累积到一个时钟周期T时，该时钟设备可以进行一次计时调整。本申请实施例中，时钟设备每经P个第一时长时，累积的偏差达到一个时钟周期T，从而对计时时间进行一次调整。
因此，时钟设备在定时过程中，若常量C与时钟周期T的比值Q1不为整数，则根据定时时长Q2×T×N确定定时点，并且每经过1/|Q2-Q1|个Q2×T时长后进行一次计时调整，从而保证计时误差维持在可接受范围内而不会随着时间的增加而增大，实现了时钟设备的精确定时。并且能够同时满足低功耗与低成本的定时。
下面对如何确定P值进行具体描述。
该时钟设备的实际的定时点为Q2×T×N×M，而真实定时点应当为C×N×M即(Q1×T)×N×M。
其中，真实的定时点为C×N×M＝Q1×T×N×M＝[Q2-(Q2-Q1)]×T×N×M＝(Q2×T)×N×M-[(Q2-Q1)×T]×N×M。
其中，该公式的前半部分(Q2×T)×N×M为该时钟设备实际的定时点，后半部分[(Q2-Q1)×T]×N×M为实际的定时点与对应的真实定时点之间的偏差。可以看出，当N×M等于1/|Q2-Q1|的整数倍时，实际定时点与真实定时点之间的偏差为时钟周期T的整数倍。N×M可以理解为所经过的第一时长的总数，每经过1/|Q2-Q1|个第一时长时，实际定时点与真实定时点之间的相差一个时钟周期T，因此进行一次计时调整。
例如图4所示的本申请实施例的计时调整的示意图。如图4所示，时钟设备可以对经过的第一时长的个数i进行记录，并且每经过1/|Q2-Q1|个第一时长，则进行一次计时调整，该第一时长等于Q2×T。图4示出了一个调整周期，该调整周期内包括1/|Q2-Q1|个第一时长，进行计时调整的时间位置为第1/|Q2-Q1|个第一时长结束的位置即i＝P＝1/|Q2-Q1|的位置，图4的黑色圆点所标识出来的地方就是要进行计时调整的位置，在该时间位置上，时钟设备将计时时间调整一个时钟周期T。
因此，本申请实施例中每经过1/|Q2-Q1|个第一时长，对计时时间进行一次调整，且每次调整的时间量等于一个时钟周期T。
可选地，在220中，每经过P个所述第一时长，对该时钟设备的计时时间进行一次调整，可以包括以下两种情况：
情况1
若
Figure PCTCN2017095918-appb-000014
则每经过P个第一时长，将该时钟设备的计时时间调慢一个时钟周期T。
例如，该时钟设备可以暂停一个时钟周期T，从而将计时时间调整慢一个时钟周期T。
情况2
若
Figure PCTCN2017095918-appb-000015
则每经过P个第一时长，将该时钟设备的计时时间调快一个时钟周期T。
例如，可以将到达下一个定时点的定时时长确定为Q2×T×N-T。
本申请实施例中，该时钟设备可以通过设置不同的计数器来实现220中的计时调整。
可选地，该时钟设备包括第一计数器和第二计数器，该第一计数器用于 记录所经过的时钟周期T的个数，该第二计数器用于记录所经过的第一时长的个数。此时，220可以包括221和222。
在221中，当所述第一计数器记录的时钟周期T的个数等于Q2时，将第一计数器置零，并将第二计数器记录的第一时长的个数加1。
在222中，当第二计数器记录的第一时长的个数达到P时，对该时钟设备的计时时间进行一次调整，并将第二计数器置零。
具体地说，第一计数器用于对所经过的时钟周期T的进行计数，计数的范围从0至Q2-1(共Q2个计数值)；第二计数器用于对所经过的第一时长进行计数，计数的范围从0至P-1(共P个计数值)，其中P＝1/|Q2-Q1|。对第一计数器而言，计数值加1的条件为第二计数器当前的计数值不等于P-1，置零的条件为第一计数器的计数值达到Q2-1。对于第二计数器而言，加1的条件为第一计数器的计数值达到Q2-1，置零的条件为第二计数器的计数值达到P-1。
换句话说，第一计数器每记录Q2个时钟周期T(即记录一个第一时长)，则第二计数器的计数值加1，第二计数器每记录P个第一时长则时钟设备对计时时间进行一次调整。
因此，通过两个计数器分别记录所经过的时钟周期T的个数和所经过的第一时长的个数，从而在根据定时时长确定定时点的过程中，可以实时进行计时调整，从而实现准确的定时。
可选地，该时钟设备还可以包括第三计数器，该第三计数器用于记录所经过的第一时长的个数，此时，210还可以包括211和212。
在211中，当第一计数器记录的时钟周期T的个数等于Q2时，将第三计数器记录的第一时长的个数加1。
在212中，当第三计数器记录的第一时长的个数达到N时，确定到达一个定时点，并将第三计数器置零。
具体地说，第三计数器也用于对所经过的第一时长进行计数，与第二计数器不同的在于，第二计数器是根据其记录的第一时长的个数进行计时调整，而第三计数器时根据其记录的第一时长的个数确定定时点，该第三计数器的计数范围从0至N-1(共N个计数值)。对于第三计数器而言，计数值加1的条件为第一计数器的计数值达到Q2-1，置零的条件为第二计数器的计数值达到N-1。换句话说，第一计数器每记录Q2个时钟周期T(Q2个时钟周 期T等于一个第一时长)，第三计数器的计数值加1，第三计数器每记录N个第一时长则时钟设备确定到达一个定时点。
因此，根据第三计数器记录的所经过的第一时长的个数，能够实现时钟设备的定时点的确定。
可选地，根据本申请实施例的定时方法，时钟设备的第M个定时点的计时误差可以表示为
Figure PCTCN2017095918-appb-000016
即
Figure PCTCN2017095918-appb-000017
其中，mod为取余，即mod(N×M，P)表示(N×M)除以P所得的余数，M为正整数。
下面以C＝1.25ms并且时钟设备包括32.768k晶体为例，结合图5和图6，详细说明本申请实施例的定时方法。
C＝1.25ms时，对于32.768k晶体，时钟周期T＝1/32.768，Q1＝1.25/T＝40.96，
Figure PCTCN2017095918-appb-000018
该时钟设备的实际的定时点为
Figure PCTCN2017095918-appb-000019
Figure PCTCN2017095918-appb-000020
而真实定时点应当为1.25×N×M。
真实定时点
Figure PCTCN2017095918-appb-000021
Figure PCTCN2017095918-appb-000022
其中，该公式的前半部分(41×T)×N×M为该时钟设备实际的定时点，后半部分
Figure PCTCN2017095918-appb-000023
为实际的定时点与对应的真实定时点之间的偏差。可以看出，当N×M等于25的整数倍时，实际定时点与真实定时点之间的偏差为时钟周期T的整数倍。N×M可以理解为经过的第一时长的总数，每经过25个第一时长时，实际定时点与真实定时点之间的相差一个时钟周期T，因此进行一次计时调整。
应理解，
Figure PCTCN2017095918-appb-000024
由于0.04＜0.96，因而可以采用
Figure PCTCN2017095918-appb-000025
从而根据定时时长
Figure PCTCN2017095918-appb-000026
确定的定时点的误差较小。
换句话说，当
Figure PCTCN2017095918-appb-000027
时，可以选择
Figure PCTCN2017095918-appb-000028
当
Figure PCTCN2017095918-appb-000029
Figure PCTCN2017095918-appb-000030
时，可以选择
Figure PCTCN2017095918-appb-000031
如图5所示，第一计数器Cnt1用于记录所经过的第一周期的个数，第二计数器Cnt2用于记录所经过的第一时长的个数i，第一时长为41×T。第一计数器Cnt1的计数值从0达到40时(共41个计数值)，第二计数器Cnt 2的计数值加1，并且第一计数器Cnt1的计数值置0。第二计数器Cnt2的计数值从0达到24时(共25个计数值)，第二计数器Cnt2的计数值置零，同时时钟设备进行一次计时调整，将计时的时间缩短一个时钟周期T，例如时钟设备暂停计时Tms在开始计时。图5中的黑色圆点所表示的时间点即为进行计时调整的时刻。
如图6所示，第三计数器Cnt3用于记录也所经过的第一时长的个数i，第一计数器Cnt1的计数值从0达到40时(共41个计数值)，第三计数器Cnt3的计数值加1，并且第一计数器Cnt1的计数值置0。第三计数器Cnt3的计数值从0达到N-1时(共N个计数值)，第三计数器Cnt3的计数值置零，同时时钟设备确定到达一个定时点。图6中的黑色三角形所表示的时间点即为一个定时点。
尽管32.768k晶体导致1.25ms不是时钟设备的时钟周期T的整数倍，但由于32.768k晶体的功耗低，价格低。通过本申请实施例的定时方法，就可以使用32.768k晶体实现精确的定时，从而同时满足低功耗和低成本的计时。
应理解，本申请实施例中以C＝1.25ms为例进行描述，但常量C的值并不限于此。另外，除了使用32.768k晶体，该时钟设备也可以使用其他具有时钟周期不同的晶体进行定时，这里不作限定。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
上文详细描述了本申请实施例的定时方法，下面将描述本申请实施例的时钟设备。
应理解，本申请实施例中的时钟设备可以执行本申请实施例中的方法，具有执行相应方法的功能。
图7示出了本申请实施例的时钟设备700的示意性框图。如图7所示，该时钟设备700可以包括确定单元710和调整单元720。其中：
该确定单元710，用于根据时钟设备的定时时长确定定时点，其中，所述时钟设备的时钟周期为T，所述定时时长为第一时长的N倍，所述第一时长等于Q2×T，
Figure PCTCN2017095918-appb-000032
或者
Figure PCTCN2017095918-appb-000033
Q1＝C/T，N为正整数，Q1不为整数，C为常量，
Figure PCTCN2017095918-appb-000034
为向上取整，
Figure PCTCN2017095918-appb-000035
为向下取整；
该调整单元，用于每经过P个所述第一时长，对所述时钟设备的计时时 间进行一次调整，其中，每次调整的时间量为一个时钟周期T，P＝1/|Q2-Q1|。
因此，时钟设备在定时过程中，若常量C(例如1.25ms)与时钟周期T的比值Q1不为整数，则根据定时时长Q2×T×N确定定时点，并且每经过1/|Q2-Q1|个Q2×T时长后进行一次计时调整，从而保证计时误差维持在可接受范围内而不会随着时间的增加而增大，实现了时钟设备的精确定时。并且能够同时满足低功耗与低成本的定时。
可选地，所述时钟设备还包括第一计数器和第二计数器；
所述第一计数器，用于记录所经过的时钟周期T的个数，且当所述第一计数器记录的所述时钟周期T的个数等于Q2时，所述第一计数器置零；
所述第二计数器，用于记录所经过的所述第一时长的个数，其中，当所述第一计数器记录的时钟周期的个数等于Q2时，所述第二计数器将记录的所述第一时长的个数加1，且当所述第二计数器记录的所述第一时长的个数达到P时，所述第二计数器置零；
其中，所述调整单元720具体用于：当所述第二计数器记录的所述第一时长的个数达到P时，对所述时钟设备的计时时间进行一次调整。
可选地，所述时钟设备还包括第三计数器，
所述第三计数器，用于记录所经过的所述第一时长的个数，其中，当所述第三计数器记录的时钟周期T的个数等于Q2时，所述第三计数器将记录的所述第一时长的个数加1，且当所述第三计数器记录的所述第一时长的个数达到N时，所述第三计数器置零；
其中，所述确定单元710具体用于：当所述第三计数器记录的所述第一时长的个数达到N时，确定到达一个定时点。
可选地，
Figure PCTCN2017095918-appb-000036
所述调整单元720具体用于：每经过P个所述第一时长，将所述时钟设备的计时时间调慢一个时钟周期T。
可选地，
Figure PCTCN2017095918-appb-000037
所述调整单元720具体用于：每经过P个所述第一时长，将所述时钟设备的计时时间调快一个时钟周期T
可选地，所述时钟设备的第M个定时点的计时误差为
Figure PCTCN2017095918-appb-000038
mod为取余，M为正整数。
可选地，常量C＝1.25ms。
可选地，1/T＝32.768，P＝25。
图8示出了本申请实施例的时钟设备800的示意性框图。如图8所示， 该时钟设备800包括处理器810和存储器820。其中，该存储器820用于存储指令，该处理器810用于执行该存储器820存储的指令，对该指令的执行使得该处理器810执行以下操作：
根据时钟设备的定时时长确定定时点，其中，所述时钟设备的时钟周期为T，所述定时时长为第一时长的N倍，所述第一时长等于
Figure PCTCN2017095918-appb-000039
或者
Figure PCTCN2017095918-appb-000040
Q1＝C/T，N为正整数，Q1不为整数，C为常量，
Figure PCTCN2017095918-appb-000041
为向上取整，
Figure PCTCN2017095918-appb-000042
为向下取整；
每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，其中，每次调整的时间量为一个时钟周期T，P＝1/|Q2-Q1|。
可选地，所述时钟设备还包括第一计数器和第二计数器；
所述第一计数器，用于记录所经过的时钟周期T的个数，且当所述第一计数器记录的所述时钟周期T的个数等于Q2时，所述第一计数器置零；
所述第二计数器，用于记录所经过的所述第一时长的个数，其中，当所述第一计数器记录的时钟周期的个数等于Q2时，所述第二计数器将记录的所述第一时长的个数加1，且当所述第二计数器记录的所述第一时长的个数达到P时，所述第二计数器置零；
其中，所述处理器810具体用于：当所述第二计数器记录的所述第一时长的个数达到P时，对所述时钟设备的计时时间进行一次调整。
可选地，所述第三计数器，用于记录所经过的所述第一时长的个数，其中，当所述第三计数器记录的时钟周期T的个数等于Q2时，所述第三计数器将记录的所述第一时长的个数加1，且当所述第三计数器记录的所述第一时长的个数达到N时，所述第三计数器置零；
其中，所述处理器810具体用于：
当所述第三计数器记录的所述第一时长的个数达到N时，确定到达一个定时点。
可选地，
Figure PCTCN2017095918-appb-000043
所述处理器810具体用于：每经过P个所述第一时长，将所述时钟设备的计时时间调慢一个时钟周期T。
可选地，
Figure PCTCN2017095918-appb-000044
所述处理器810具体用于：每经过P个所述第一时长，将所述时钟设备的计时时间调快一个时钟周期T。
可选地，所述时钟设备的第M个定时点的计时误差为
Figure PCTCN2017095918-appb-000045
mod为取余，M为正整数。
可选地，常量C＝1.25ms。
可选地，1/T＝32.768，P＝25。
应理解，在本申请实施例中，处理器可以是中央处理单元(Central Processing Unit，CPU)，该处理器还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
该存储器可以包括只读存储器和随机存取存储器，并向处理器提供指令和数据。存储器的一部分还可以包括非易失性随机存取存储器。例如，存储器还可以时钟设备相关计时参数的信息。
在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的定位方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
图9是本申请实施例的计时芯片的一个示意性结构图。图9的计时芯片900包括输入接口901、输出接口902、至少一个处理器903、存储器904，所述输入接口901、输出接口902、所述处理器903以及存储器904之间通过内部连接通路互相连接。所述处理器903用于执行所述存储器904中的代码。
可选地，当所述代码被执行时，所述处理器903可以实现方法实施例中的时钟设备所执行的方法200。为了简洁，这里不再赘述。
本申请实施例还提供了一种终端设备，该终端设备可以包括上述本申请实施例中的任意一种时钟设备或者计时芯片。
可选地，该时钟设备为蓝牙设备。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方 法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，该单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
该作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个检测单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上，仅为本申请的具体实施方式，但本申请实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请适合私利的保护范围之内。因此，本申请实施例的保护范围应该以权利要求的保护范围为准。

Claims (18)

  1. 一种定时方法，其特征在于，所述方法包括：
    根据时钟设备的定时时长确定定时点，其中，所述时钟设备的时钟周期为T，所述定时时长为第一时长的N倍，所述第一时长等于Q2×T，
    Figure PCTCN2017095918-appb-100001
    或者
    Figure PCTCN2017095918-appb-100002
    Q1＝C/T，N为正整数，Q1不为整数，C为常量，
    Figure PCTCN2017095918-appb-100003
    为向上取整，
    Figure PCTCN2017095918-appb-100004
    为向下取整；
    每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，其中，每次调整的时间量为一个时钟周期T，P＝1/|Q2-Q1|。
  2. 根据权利要求1所述的方法，其特征在于，所述时钟设备包括第一计数器和第二计数器，所述第一计数器用于记录所经过的时钟周期T的个数，所述第二计数器用于记录所经过的所述第一时长的个数；
    其中，所述每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，包括：
    当所述第一计数器记录的所述时钟周期T的个数等于Q2时，将所述第一计数器置零，并将所述第二计数器记录的所述第一时长的个数加1；
    当所述第二计数器记录的所述第一时长的个数达到P时，对所述时钟设备的计时时间进行一次调整，并将所述第二计数器置零。
  3. 根据权利要求2所述的方法，其特征在于，所述时钟设备还包括第三计数器，所述第三计数器用于记录所经过的所述第一时长的个数，
    其中，每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，包括：
    当所述第一计数器记录的所述时钟周期T的个数等于Q2时，将所述第三计数器记录的所述第一时长的个数加1；
    当所述第三计数器记录的所述第一时长的个数达到N时，确定到达一个定时点，并将所述第三计数器置零。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，
    Figure PCTCN2017095918-appb-100005
    所述每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，包括：
    每经过P个所述第一时长，将所述时钟设备的计时时间调慢一个时钟周期T。
  5. 根据权利要求1至3中任一项所述的方法，其特征在于，
    Figure PCTCN2017095918-appb-100006
    所述每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，包括：
    每经过P个所述第一时长，将所述时钟设备的计时时间调快一个时钟周期T。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，所述时钟设备的第M个定时点的计时误差为
    Figure PCTCN2017095918-appb-100007
    mod为取余，M为正整数。
  7. 根据权利要求1至6中任一项所述的方法，其特征在于，常量C＝1.25ms。
  8. 根据权利要求1至7中任一项所述的方法，其特征在于，1/T＝32.768，P＝25。
  9. 一种时钟设备，其特征在于，所述时钟设备包括：
    确定单元，用于根据时钟设备的定时时长确定定时点，其中，所述时钟设备的时钟周期为T，所述定时时长为第一时长的N倍，所述第一时长等于Q2×T，
    Figure PCTCN2017095918-appb-100008
    或者
    Figure PCTCN2017095918-appb-100009
    Q1＝C/T，N为正整数，Q1不为整数，C为常量，
    Figure PCTCN2017095918-appb-100010
    为向上取整，
    Figure PCTCN2017095918-appb-100011
    为向下取整；
    调整单元，用于每经过P个所述第一时长，对所述时钟设备的计时时间进行一次调整，其中，每次调整的时间量为一个时钟周期T，P＝1/|Q2-Q1|。
  10. 根据权利要求9所述的时钟设备，其特征在于，所述时钟设备还包括第一计数器和第二计数器；
    所述第一计数器，用于记录所经过的时钟周期T的个数，且当所述第一计数器记录的所述时钟周期T的个数等于Q2时，所述第一计数器置零；
    所述第二计数器，用于记录所经过的所述第一时长的个数，其中，当所述第一计数器记录的时钟周期的个数等于Q2时，所述第二计数器将记录的所述第一时长的个数加1，且当所述第二计数器记录的所述第一时长的个数达到P时，所述第二计数器置零；
    其中，所述调整单元具体用于：
    当所述第二计数器记录的所述第一时长的个数达到P时，对所述时钟设备的计时时间进行一次调整。
  11. 根据权利要求10所述的时钟设备，其特征在于，所述时钟设备还包括第三计数器，
    所述第三计数器，用于记录所经过的所述第一时长的个数，其中，当所述第三计数器记录的时钟周期T的个数等于Q2时，所述第三计数器将记录 的所述第一时长的个数加1，且当所述第三计数器记录的所述第一时长的个数达到N时，所述第三计数器置零；
    其中，所述确定单元具体用于：
    当所述第三计数器记录的所述第一时长的个数达到N时，确定到达一个定时点。
  12. 根据权利要求9至11中任一项所述的时钟设备，其特征在于，
    Figure PCTCN2017095918-appb-100012
    所述调整单元具体用于：
    每经过P个所述第一时长，将所述时钟设备的计时时间调慢一个时钟周期T。
  13. 根据权利要求9至11中任一项所述的时钟设备，其特征在于，
    Figure PCTCN2017095918-appb-100013
    所述调整单元具体用于：
    每经过P个所述第一时长，将所述时钟设备的计时时间调快一个时钟周期T。
  14. 根据权利要求9至13中任一项所述的时钟设备，其特征在于，所述时钟设备的第M个定时点的计时误差为
    Figure PCTCN2017095918-appb-100014
    mod为取余，M为正整数。
  15. 根据权利要求9至14中任一项所述的时钟设备，其特征在于，常量C＝1.25ms。
  16. 根据权利要求9至15中任一项所述的时钟设备，其特征在于，1/T＝32.768，P＝25。
  17. 一种终端设备，其特征在于，所述终端设备包括上述权利要求9至16中任一项所述的时钟设备。
  18. 根据权利要求17所述的终端设备，其特征在于，所述终端设备包括蓝牙设备。
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