EP1521143A1 - Zeit-Digital Umsetzer - Google Patents

Zeit-Digital Umsetzer Download PDF

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Publication number
EP1521143A1
EP1521143A1 EP03103642A EP03103642A EP1521143A1 EP 1521143 A1 EP1521143 A1 EP 1521143A1 EP 03103642 A EP03103642 A EP 03103642A EP 03103642 A EP03103642 A EP 03103642A EP 1521143 A1 EP1521143 A1 EP 1521143A1
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EP
European Patent Office
Prior art keywords
signal
event
register
time
samples
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03103642A
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English (en)
French (fr)
Inventor
Jean-Luc Bolli
Jean-François GOUMAZ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Acqiris SA
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Acqiris SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acqiris SA filed Critical Acqiris SA
Priority to EP03103642A priority Critical patent/EP1521143A1/de
Priority to CA002482677A priority patent/CA2482677A1/en
Priority to US10/955,282 priority patent/US7423937B2/en
Priority to JP2004287119A priority patent/JP2005106826A/ja
Publication of EP1521143A1 publication Critical patent/EP1521143A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac

Definitions

  • the present invention relates to the field of coders of time, and more specifically time-to-digital converters, designated also TDC (Time-Digital-Converters).
  • TDC Time-Digital-Converters
  • Time-to-Digital Converters are used where one wants to accurately measure and code the temporal position of a event, or a plurality of events, represented by electrical pulses, with respect to a reference signal, defining the origin of the time scale.
  • TDCs are used for example in the field of physics corpuscular, to measure the passage times of particles elementals produced during an interaction, in the different zones of a segmented particle detector.
  • TDCs also find applications in many others areas in which accurate measurement of arrival times is required of electrical impulses.
  • TDC applications include time correlated microscopy of photons, optical tomography, component testing electronic spectroscopy, time-of-flight measurement spectroscopy, OTDR in the field of time.
  • a well-known technique of coding time intervals is to electronically count the number of pulses of a signal clock, and copy the counter value during the event of interest in a register.
  • a limitation of this technique is that the measurement accuracy, is limited by the rate of the clock signal. For a resolution of 10 picoseconds, for example, a clock signal of 100 gigahertz is required, so that this level of precision is hardly attainable by this technical.
  • Another known technique is to convert the interval to measure in a proportionally longer interval, for example with a double-ramp converter, in which one charges and then discharges a capacitor with two constant currents of different values.
  • the time required for the voltage across the capacitor returns to zero is proportional to the desired time interval, and can be measured with a counter whose rate is relatively low.
  • a disadvantage of this technique is the relatively large idle time associated with each event measured, so that this technique is difficult to apply to multiple and close impulses, such as for example the signals generated by the particle detectors elementary (multi-hit events).
  • Another disadvantage of the above technique is related to the difficulty in achieving constant and independent sources of currents the ramp voltage. Any difference in behavior between the two sources leading to conversion errors.
  • An object of the present invention is to present a coder of time free from the disadvantages of the prior art.
  • Another object of the present invention is to propose an encoder of time that joins a high resolution and depth, allowing very precise measurements of extended time intervals.
  • Another object of the present invention is to enable realize a time encoder whose resolution is programmable and adaptable to the needs of the application.
  • Another object of the invention is to provide a time coder requiring no calibration procedure to maintain its accuracy.
  • a device for measuring the temporal position of an event comprising: a signal generator bootable, to generate a synchronous periodic signal with the said event, and whose phase is correlated with the temporal position of the event, characterized in that said measuring device comprises a first analog-to-digital converter to measure a plurality samples of a first reference signal during said event, the values of said samples determining said phase of said signal periodic.
  • the input signal 2 is an analog or digital signal comprising corresponding voltage or current pulses in general to events whose temporal position is to be determined precisely.
  • the signal 2 is connected to an input of a discriminator 37, to obtain a digital trigger signal 6 (TRIG, TR), whose front corresponds to the event signaled by the impulse 2.
  • TOG digital trigger signal
  • the discriminator may be preceded by an input signal conditioning circuit 2, no shown in FIG. 1.
  • the conditioning circuit can for example be include overvoltage protection elements, a line of delay, an amplifier, attenuators, impedance adapters and everything other electrical or electronic element necessary to adapt the characteristics of signal 2 to discriminator 37.
  • a second input of the discriminator 37 is connected to the converter DAC 35, which provides a constant voltage level 5 and representing a threshold level to be exceeded for an event to be detected by the converter 10.
  • the threshold level 5 will be placed low enough to detect small impulses as well, but far enough away from the noise level to limit false triggers.
  • the DAC 35 makes it easy to adapt the value of the threshold 5 to measurement conditions.
  • the DAC 35 may be replaced by a fixed or variable reference voltage generator.
  • the discriminator 37 is a constant fraction discriminator (CFD), which triggers the pulse of trigger when the input level has reached a predetermined fraction of its peak value.
  • CFD constant fraction discriminator
  • the discriminator 37 detects the rising edge of the input signal 2.
  • logic gate 39 controlled by the input 38 makes it possible to obtain a signal trigger logic 6 having the required polarity.
  • the generator 81 produces the sinusoidal signal 13 serving as the time base for the converter 10.
  • the sinusoid 13 is generated from an external clock signal 82, as indicated on the Figure 1a, or by a local generator of time not shown.
  • the signal frequency 13 is chosen according to the application and the desired temporal resolution, within limits imposed by the speed of components used. In a typical case we can recommend a frequency of 100 MHz, although obviously the present invention also includes devices whose rate is higher or lower, According to the case.
  • the trigger digital signal 6 is sent to a system coarse measuring device 15, described hereinafter with reference to FIGS. 2a.
  • the coarse measurement circuit 15 comprises the real-time counter 61 and the two registers 64, 65.
  • the real-time counter 61 counts the signal periods sinusoidal 13, and is used to power the two buses 3 and 4, whose content changes synchronously, being incremented each cycle of the time base 13, during all the time in which the converter 10 is active.
  • the bus 4 is shifted by half a period with respect to bus 3 by a timing logic circuit not shown.
  • the number of bits of buses 3 and 4 is chosen according to the maximum temporal distance between two events you want save. Admitting that the time base runs at 100 MHz, and that the bus 3 and 4 include 32 bits each, the maximum duration will be 43 seconds. If a more limited duration is enough, we can limit the depth buses 3 and 4 and the counter 61, for example at 24 bits for a depth of 167 ms.
  • Registers 64 and 65 sample the contents of buses 3 and 4 to the moment of each event signaled by the rising edge of the signal of trigger 6. The contents of the registers are then copied into a zone of memory provided for this purpose in logic unit 71.
  • the system of coarse measurement 15, including the real-time counter 61, the two buses 3, 4, the timing unit and the registers 64, 65 are made inside an FPGA (Field Programmable Gate Array) type integrated circuit.
  • FPGA Field Programmable Gate Array
  • the FPGA circuit will also include the logic unit 71.
  • the trigger signal 6 is also sent to a device of fine measurement 17, comprising the pulse generator 40 and the ADC 52.
  • the pulse generator 40 triggers a burst of pulses 8 in correspondence of each event marked by an impulse of trigger signal 6.
  • Signal 8 serves as a clock for the ADC 52 which samples the sinusoidal signal 13 corresponding to each signal pulse 8.
  • the 8 signal generated is, by the way the circuit 40 operates, synchronous with the trigger signal 6.
  • the signal 8 contains therefore, by the value of its phase, the information on the moment of arrival of the event.
  • the values sampled by the ADC 52 are stored in the unit logic 71. Taking several samples of the sinusoid 13 allows to determine the phase of the latter at the moment of the signal of trigger 6, with a high resolution, as we will see later.
  • the amplitude A is chosen so as to occupy as much as possible the scale of ADC 52, but without exceeding it.
  • the sampling period T s is judiciously chosen according to the period T 0 of the sampled sinusoid. Preferably, a substantially faster rate will be adopted than that of the sinusoid 13, to accelerate the conversion time. For example we can choose pulses separated by 1 ns, and an ADC 52 with a conversion rate of 1 GS / s.
  • the three unknowns A, T s and D are determined at each new trigger signal, and their value is ignored, or used for monitoring purposes only.
  • This measurement method has the advantage of not requiring any calibration, the accuracy of the measurement then based solely on the absolute accuracy and stability of the frequency ⁇ 0 .
  • the quantities A, T s and D are however substantially constant, and could be determined once and for all or periodically by a suitable calibration method. It is also possible in the present invention to separately evaluate the quantities A, T s and D during an automatic calibration or on the initiative of an operator, thus reducing the number of pulses required to reach the desired resolution and limiting the In a further variant of the invention, the calibration of A, T s and D may also be performed only when certain predetermined conditions are met, for example once for the first hit of each event, but not for successive hits.
  • pulses 8 are sampled. If by example ADC 52 has an internal pipeline architecture, one or more pulses at the beginning and at the end of the salvo are only needed to wake up the ADC and extract the data from the pipeline. In this case we may increase the number of hits in each salvo, in order to have always a sufficient number of samples.
  • the generator 40 shown in FIG. LC oscillator that can be booted by the transistor 42.
  • a sinusoid is present at the terminal 45 whose frequency is determined by the values of L and C.
  • Counter 4 counts a number predefined pulse of the discriminated signal 46, and resets the signal Enable, to cut the burst of pulses to the desired length.
  • Figure 7 shows an alternating circuit for the generator pulses 40 having delay lines 43.
  • Each cell consisting of a delay line 43 and an XOR gate 44 produces a impulse shifted in time.
  • the adder ⁇ recomposes pulses to give rise to the burst of pulses 8.
  • the two registers 64 and 65 record two measurements independent of the temporal position of the event by compared to two time bases 3 and 4 isochronous and offset by half period. This duplication makes it possible to avoid ambiguities due to metastability of buses 3 and 4 during transitions 90, visible in FIG. 2.
  • the counting and reading routine may be stored in the logical unit 71 and executed by a local processor, or executed by a master processor, which has access to the raw data stored in unit 71 by an appropriate communication bus, such as for example a PCI, VME or VXI bus.
  • an appropriate communication bus such as for example a PCI, VME or VXI bus.
  • the time encoder according to the invention 20 comprises a generator 810 which produces the two sinusoidal signals in quadrature 13 and 14 serving as a time base for the converter 10.
  • a generator 810 which produces the two sinusoidal signals in quadrature 13 and 14 serving as a time base for the converter 10.
  • I In phase
  • Q Quadrature
  • Signals 13 and 14 are generated at from an external clock signal 82, as can be seen in FIG. or by a local oscillator not shown.
  • the frequency of the signals 13 and 14 is chosen according to the resolution that one wishes to obtain, as in the first embodiment already described.
  • the I and Q 810 signal generator is now described with 3 and 4.
  • the reference signal 82 coming from the outside or a local oscillator, is applied to the inputs of both flip-flops 83, 84 for generating two square signals out of phase by 90 ° whose frequency is half that of signal 82.
  • Both band pass filters or identical low-pass 85 and 86 transform square signals into signals sinusoidal.
  • the latches 83, 84 are replaced by a clock generator 89.
  • the circuit 89 produces at its outputs A and B two signals squares each having a specific phase relationship with the signal of reference 82 programmable by the input bus 120. In the circuit of 4 the delay between the I and Q signals can thus be easily calibrated.
  • the programmable generator 89 is integrated in the FPGA.
  • the frequency of the reference signals I and Q can be changed, to adapt to the conditions of measurement, by appropriate means not shown.
  • the trigger digital signal 6 is sent to a system coarse measurement 15, identical to that already described in relation to the first embodiment of this invention and shown in FIGS. 2a.
  • the trigger signal 6 is also sent to a device of fine measurement 17, comprising the pulse generator 40 and the two ADCs 51 and 52.
  • the pulse generator 40 triggers a burst of pulses 8 in correspondence of each event marked by an impulse of trigger signal 6.
  • Signal 8 serves as clock for both ADC 51 and 52 which sample the two sinusoidal signals in quadrature 13 and 14 in correspondence of each pulse of the signal 8.
  • this embodiment of the invention provides a pair of sinusoids in quadrature as a time reference, the invention is not not limited by this example.
  • a converter according to the invention could also use two signals out of phase by an angle other than 90 ° or different shapes, for example triangles, instead of sinusoids 13 and 14.
  • the relative arrival time t 0 of the pulse 6 can thus be determined more precisely, analogously to that described in the first embodiment above, or by means of averaging or interpolation, for example a linear regression of the values ⁇ i .
  • the real time counter 128 of the time encoder 100 counts the number of CK pulses from the beginning to the end of the measurement. Its depth, in bits determines the TDC range, which is the maximum time between the first and the last event recorded by the TDC module.
  • the value of counter 161 is available on the CTR bus. Typically we will provide a 32-bit depth for a clock rate of 1 GHz CK and a depth of 4.3 seconds, although of course other values are possible for these parameters.
  • the time encoder 100 also comprises at least two channels 99. Several channels can share a single basic circuit of time 181 and a common counter 161 to form a TDC multi-channel that can sample multiple signals at a time, each signal being measured by one of the TDC channels.
  • the digital trigger signal TR is generated from the signal input by the comparator 37, the DAC 35 and the gate 38, as already Explain.
  • the signal TR is applied to the clock input of a D flip-flop 107, making it possible to implement a function for accepting triggers, and gives rise, when the control signal ENA is in the high state, to a signal accepted trigger TRA.
  • the TRA signal whose initial flank is synchronous with the event to measure, triggers a synchronized sinus generator (GSS) 140.
  • the circuit 140 is constructed similarly to the circuit 40 shown in FIG. FIG. 5, and comprises an LC oscillator controlled by a circuit of start / stop. In the stopped state a constant current is injected into the inductance L, and the quality factor Q of the resonator is kept low by the low resistance of diodes D1, D2 in the conduction state.
  • the output of the GSS 140 (SIN) is of single-ended type, the invention extends however also to the case of a differential output.
  • the sinusoidal signal SIN is applied to the input of digitization of an ADC 151.
  • the ADC 151 continuously samples the output of the generator 140, according to the rate imparted by the present CK signal at his clock entrance.
  • the circuit 113 composed by the cascade of the flip-flops 108 and 109, generates the accepted trigger signal synchronized to the TRAS clock.
  • This circuit includes at least two chain D flip-flops and has the function of producing a signal whose transitions are synchronous with those of the CK, and lacking metastable states. This signal will be used to freeze the counter's status. real-time system.
  • Samples measured by ADC 52 are transmitted to a register of interpolation data (RDI) 185.
  • This digital memory of samples accepts data from ADC 151 when the signal TRAS is in the high state, and records only the output data of the ADC interesting for determining the moment of arrival of the event, as will be explained later.
  • the selection of events useful for determining time arrival is performed by the acquisition sequence controller 127.
  • This circuit contains a sample counter to accept to determine the number of samples to be recorded at each event. When this number is reached the signal RESET resets the flip-flop 107 to zero. Signals TRA and TRAS therefore return to the low state, the first immediately, and the second after a number of clock cycles that is determined by the number of latches in series in circuit 113.
  • the acquisition sequence controller 127 provides two modes selectable operating modes. In a first mode (multi-hit mode) resets himself to be ready to accept a new event immediately after a recorded event. In one second mode of operation (single-hit mode) it keeps the signal from RESET high, prohibiting the acquisition of new events, until the receiving a new reset command.
  • a first mode multi-hit mode
  • a second mode of operation single-hit mode
  • the real-time register 164 stores the state of the CTR bus at moment of positive transition of TRAS.
  • the value recorded in the register 164 is a rough measure of the instant of the TR trigger.
  • the time zone of acceptance of a trigger TRA it is possible for the time zone of acceptance of a trigger TRA to be determined from the coarse measurement and the known delay introduced by the synchronization circuit, within the uncertainty range Z acc , corresponding to a period of the clock CK.
  • the timing diagram 9 is valid for a synchronization with 2 flip-flops; The same reasoning can however extend to a different synchronization circuit.
  • the interpolation of the data acquired by the ADC provides, as in the first embodiment of the invention, the exact time ⁇ T of the transition of TRA inside the window Z acc .
  • the unknowns to be determined are 5 (A, ⁇ 0 , ⁇ 0 , ⁇ 0 , D) and the algorithm used will be a 5-parameter fit, making it possible to determine ⁇ t as soon as N, the number of samples, is greater than or equal to 5.
  • the position and the size of the pulse TRAS, corresponding to the acquisition window of the RDI register 162, will be chosen to store a sufficient number of samples E i , taking also into account the delay introduced by the ADC 151 (pipeline delay) as shown in Figure 9.
  • Elements 107, 113 and 127 have, in this example, basically the function of generating the TRAS timing signal to select the events really useful for the determination the moment the TR trigger is triggered. This selection could however, be carried out or completed also in a example by a piece of software, reside in the control unit of the encoder 100, or in an external computer.
  • the proposed circuits can also work with other waveforms, different from the sinusoidal form. Any shape repetitive waveform and synchronous with a trigger that can in principle be used. For example one could replace the generators 51, 52 and 151 by sawtooth or triangle signal generators.
  • time encoder of the present invention can advantageously integrated in a multi-channel device, comprising several channels 99 in a module that can be interfaced with a bus of communication.
  • the different channels of a module can be sequenced to reach a close dead time zero in single channel mode.
  • the TDC according to the invention can be produced as an element modular, provided with a connector to connect to a bus of data, such as a PCI, VXI or VME bus.
  • a bus of data such as a PCI, VXI or VME bus.
  • each module constitutes a card having a connector on one edge, so that it can be plugged in removably and connected electrically with a motherboard.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
EP03103642A 2003-10-01 2003-10-01 Zeit-Digital Umsetzer Withdrawn EP1521143A1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP03103642A EP1521143A1 (de) 2003-10-01 2003-10-01 Zeit-Digital Umsetzer
CA002482677A CA2482677A1 (en) 2003-10-01 2004-09-28 Time converter
US10/955,282 US7423937B2 (en) 2003-10-01 2004-09-30 Time converter
JP2004287119A JP2005106826A (ja) 2003-10-01 2004-09-30 時間変換器

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EP03103642A EP1521143A1 (de) 2003-10-01 2003-10-01 Zeit-Digital Umsetzer

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EP (1) EP1521143A1 (de)
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CA (1) CA2482677A1 (de)

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FR2933774A1 (fr) * 2008-07-11 2010-01-15 Mathieu Duprez Procede electronique de mesure instantanee d'un intervalle de temps utilisant un circuit logique programmable(ou fpga en anglais) et une horloge de reference
WO2013034770A3 (en) * 2011-09-08 2013-05-02 Borowski, André Time - to - digital converter and method therefor
CN105068405A (zh) * 2015-08-28 2015-11-18 中国科学技术大学 Fpga实现的单通道信号脉宽高精度测量方法和装置
CN111007520A (zh) * 2019-12-30 2020-04-14 中国科学院微电子研究所 基于fpga的多通道时间测量系统、方法及激光扫描仪

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CN101467067B (zh) * 2006-06-15 2012-11-07 皇家飞利浦电子股份有限公司 用于飞行时间pet的集成多通道时间-数字转换器
US8098787B1 (en) * 2007-12-13 2012-01-17 Altera Corporation Method and apparatus for precision quantization of temporal spacing between two events
KR101223953B1 (ko) * 2011-07-05 2013-01-21 한국 천문 연구원 표준 시각 동기용 주파수를 이용한 자체 온도 보상 기능을 갖는 고 분해능 정밀 시각 측정 장치 및 방법
US9594353B2 (en) * 2013-05-31 2017-03-14 Gyorgy Gabor Cserey Device and method for determining timing of a measured signal
US9606228B1 (en) 2014-02-20 2017-03-28 Banner Engineering Corporation High-precision digital time-of-flight measurement with coarse delay elements
RU2598975C1 (ru) * 2015-05-26 2016-10-10 Геннадий Николаевич Абрамов Нониусный рециркуляционный преобразователь время-код повышенного быстродействия
US9866208B2 (en) 2015-06-15 2018-01-09 Microsoft Technology Lincensing, LLC Precision measurements and calibrations for timing generators
RU2707380C1 (ru) * 2018-12-19 2019-11-26 Геннадий Николаевич Абрамов Нониусный рециркуляционный преобразователь время-код повышенного быстродействия
DE102019205731A1 (de) * 2019-04-18 2020-10-22 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Zeit-zu-Digital-Wandler-Anordnung
JP7298317B2 (ja) * 2019-06-07 2023-06-27 セイコーエプソン株式会社 電子時計の制御方法および電子時計
CN114779607B (zh) * 2021-05-10 2023-11-28 深圳阜时科技有限公司 时间测量电路、时间测量方法、时间测量芯片、时间测量模组和电子设备
CN113934132B (zh) * 2021-10-12 2022-05-27 湖南师范大学 一种基于北斗时钟信号的高精度时间同步系统及同步方法
CN114253117B (zh) * 2021-11-05 2023-06-06 上海星秒光电科技有限公司 光子到达时间的测量方法、装置、电子设备及存储介质

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2933774A1 (fr) * 2008-07-11 2010-01-15 Mathieu Duprez Procede electronique de mesure instantanee d'un intervalle de temps utilisant un circuit logique programmable(ou fpga en anglais) et une horloge de reference
WO2013034770A3 (en) * 2011-09-08 2013-05-02 Borowski, André Time - to - digital converter and method therefor
US10079608B2 (en) 2011-09-08 2018-09-18 Fastree 3D Bv Time-to-digital converter and method therefor
CN105068405A (zh) * 2015-08-28 2015-11-18 中国科学技术大学 Fpga实现的单通道信号脉宽高精度测量方法和装置
CN105068405B (zh) * 2015-08-28 2017-10-03 中国科学技术大学 Fpga实现的单通道信号脉宽高精度测量方法和装置
CN111007520A (zh) * 2019-12-30 2020-04-14 中国科学院微电子研究所 基于fpga的多通道时间测量系统、方法及激光扫描仪

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JP2005106826A (ja) 2005-04-21
CA2482677A1 (en) 2005-04-01
US20050122846A1 (en) 2005-06-09
US7423937B2 (en) 2008-09-09

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