EP0698269A1 - Procede et dispositif de transmission de donnees a correction d'erreurs fonde sur des codes semi-cycliques - Google Patents

Procede et dispositif de transmission de donnees a correction d'erreurs fonde sur des codes semi-cycliques

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Publication number
EP0698269A1
EP0698269A1 EP95907126A EP95907126A EP0698269A1 EP 0698269 A1 EP0698269 A1 EP 0698269A1 EP 95907126 A EP95907126 A EP 95907126A EP 95907126 A EP95907126 A EP 95907126A EP 0698269 A1 EP0698269 A1 EP 0698269A1
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EP
European Patent Office
Prior art keywords
symbols
block
check
error
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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EP95907126A
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German (de)
English (en)
Inventor
Constant Paul Marie Jozef Baggen
Ludovicus Marinus Gerardus Maria Tolhuizen
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Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Philips Electronics NV
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Priority to EP95907126A priority Critical patent/EP0698269A1/fr
Publication of EP0698269A1 publication Critical patent/EP0698269A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1866—Error detection or correction; Testing, e.g. of drop-outs by interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2921—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes wherein error correction coding involves a diagonal direction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H03M13/293—Decoding strategies with erasure setting
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/007—Unequal error protection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • G11B2020/1836—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information using a Reed Solomon [RS] code

Definitions

  • the invention relates to a method for transmitting a digital information signal in the form of a plurality of s sequences of information symbols, each symbol having a uniform bit length and each such sequence of symbols occurring in a respective input channel, check words being included in the transmitted signal as a result of encoding to enable correction of erroneous symbols caused by said transmitting, said method comprising the steps of:
  • the invention also relates to a device for executing the method.
  • a decoding strategy therefor have been disclosed in US Patent 4,477,940 (PHN 10.242 Ref. I) to the present Assignee; a further particular decoding strategy has been disclosed in US Patent 4,683,572 (PHN 10.931, Ref.II), again to the same Assignee as the present application.
  • all codes used for the present invention are linear codes, so that the sum of two code words is again a code word. This also allows for explicitly or implicitly converting a code word of a systematic code into a code word of a non-systematic code and vice versa.
  • the references relate to the error protection of the well-known Compact Disc system for recording and transmitting high-quality audio signals.
  • Various extensions of that system have been based on the above error protection technology.
  • the digital error protection is sufficient to exactly reproduce the original digital input signal, whilst in case of reproduction of an audio signal, a last recourse can be found by masking uncorrectable errors through some kind of interpolation on the audio signal itself.
  • the above system has been widely and successfully commercialized, a need for higher performance has been felt, in respect of attainable data rate as well as in respect of increased robustness against errors to be offered by the code itself.
  • the invention is characterized in that said first and second check symbols are generated to satisfy a respective parity check matrix, each having s+p+q columns, but p and q rows, respectively, wherein p.q > 1 of semi-cyclic codes, said delaying putting adjacent symbols of said first arranging state into uniformly- spaced instances of said second arranging state, and in that said q second check symbols are retro-coupled into said first error correcting encoder in accordance with said first arranging state.
  • p.q > 1 of semi-cyclic codes said delaying putting adjacent symbols of said first arranging state into uniformly- spaced instances of said second arranging state, and in that said q second check symbols are retro-coupled into said first error correcting encoder in accordance with said first arranging state.
  • the invention also relates to a method for decoding with error correction, to a device for transmitting with error protection, to a device for decoding with error correction, and to a carrier provided with information spaced and disposed for application in conjunction with the above method and/or devices as specified in various claims.
  • a trailing sequence of said first and second check symbols is generated by said delaying and retrocoupling and is limited to a series of s+q-1 first blocks comprising only notional information symbols. This produces a first code format that is applicable to separating data segments from each other, so that no code interactions occur.
  • said trailing sequence of first and second check symbols is overlayed through symbolwise addition to an initial sequence of first and second check symbols at a commencing part of said finite sequence, thereby realizing a cylindrical storage format.
  • This is feasible through the use of linear codes and allows a shorter length format for the same amount of user data, such as expressible in physical carrier area.
  • This allows for earlier decoding of a so- called tail-up format in that no wrapping around is effected.
  • Figure 1 shows an overall block diagram of an encoding device
  • Figure 3 shows a diamond code in systematic form
  • Figure 4 shows correspondence of the present code to a product code
  • Figure 5 offers a detailed explanation of an encoding embodiment
  • Figure 6 shows positions of the various code symbols
  • Figure 7 offers a detailed explanation of a decoding embodiment
  • Figure 8 shows an overall block diagram of a decoding device
  • Figure 9 shows a symbol disposition on a carrier
  • Figures 10 and 11 show matrices for explanation of a block code
  • Figure 12 shows a convolutionally encoded data block
  • Figure 13 shows encoding of repeated data blocks
  • Figure 14 shows cylindrically encoded data blocks
  • Figure 15 shows alignment of short bursts with odd-even interleave
  • Figure 16 shows odd/even interleave with symbol permutation
  • Figure 17 shows an improved storage organization that features unequal error protection
  • Figure 18 shows a finite support convolutional diamond code word
  • Figure 19 shows a block-convolutional diamond code word
  • FIG 19 shows concatenated code blocks according to Figure 19
  • Figure 21 shows preparation of blocks for encoding.
  • Figure 1 shows an overall block diagram of an encoding device.
  • the stream of data symbols arrives at input 100 which by way of example, may be 8 bits wide to accommodate eight-bit symbols.
  • Block 102 is the input storage that takes up the symbols according to order of arrival, and according to a selection mechanism that assigns the symbols to appropriate channels. The delay allows the various symbols to be presented to the first encoder stage 104 at the correct instants.
  • the encoder 104 needs to receive the incoming symbols at the same data rate as the input 100; for each data symbol received it determines the contribution thereby to the various preliminary first check symbols of the word of the first code to which the data symbol in question belongs. If necessary, it may calculate the contributions by the data symbols to preliminary check symbols of a cycle of first code words as applicable to the format shown in Figure 9, infra, as an example. This situation applies if the symbols of a particular code word do not arrive contiguously, but are interspersed with symbols of one or more other words in a cyclic manner.
  • Block 106 is the intermediate storage to align the data symbols and first check symbols for processing by a second encoder stage 108.
  • Block 108 calculates, in a similar way as the block 104, the second check symbols associated with the second code words.
  • Block 110 is the output storage that takes up the data symbols and first and second check symbols for sequentially correct presentation to serial output 112.
  • the second check symbols are also retro-coupled, via delays 107, into the encoder 104 in which they also contribute to the appropriate first code word.
  • both p and q in Figure 1 have the value 8.
  • the value of s the number of data or user symbols, is much larger, but a value of 118 gave good results. A higher degree of protection has been attained with s having a value of 52. The detailed timing will be discussed with respect to Figures 2 and 5-7.
  • each row represents a sequence of symbols, each symbol covering one of the squares, and each square being occupied by exactly one symbol. Usually, each symbol has eight bits, although this number is not an absolute restriction.
  • the arrowed indications Cl and C2 indicate the positioning of the Cl code words and C2 code words, respectively: Cl words lie in a vertical direction and C2 words in a diagonal direction. All code words form part of a so-called semi-cyclic code or weakly cyclic.
  • the definition of such a code C is as follows:
  • n-symbol word at the left that starts with a symbol zero is a word of the code C
  • the word rotated over one symbol as shown, which word in consequence ends with a symbol zero is also a word of the code C.
  • words that start with a greater number of zeroes can be rotated over a relatively greater number of symbol positions.
  • rotation in the other direction would not necessarily result in a code word.
  • Various codes having the above property can be given but a conspicuous class is formed by the shortened Reed-Solomon codes that are also used in the references.
  • a shortened BCH code is a more general code that also applies.
  • the data symbols are assigned to a plurality of sequences as indicated by the reference 20. For clarity, only a few sequences thereof have been shown.
  • Indication 22 refers to the four check symbols of each Cl code word.
  • Indication 24 refers to the two check symbols of each C2 code word. These numbers are given by way of example only; in practice, the code words often have higher numbers of check symbols.
  • the first non-zero data symbol is the symbol d in row 26 and column 40 (symbol 2640).
  • Encoding of the Cl code word that is positioned in column 40 yields the symbols c, b, a, 1, respectively as shown, symbol 3440 having the value 1 through normalization. It can be proven that with the semi-cyclic codes according to the invention the symbol 3440 cannot be zero.
  • Alignment of columns 40 and 42 implies rotation over one position in the vertical direction; according to the definition of semi-cyclic codes, supra, this produces again a word of the code, because symbol 3640 is now a zero. This property applies because all other symbols of columns 40, 42 are zero.
  • a similar reasoning produces the contents of blocks 3044, 3244, 3444, 3644, as shown, together constituting the non-zero part of the Cl word in column 44.
  • the dimension along each column is also one greater than the number of check symbols of the Cl code. Because of the shape of the parallelogram, the code is called the diamond code. On the basis of the properties of the selected codes, the symbols 2640 and 3440 both differ from zero. Now, another data symbol of column 40 may differ from zero, for example symbol 2540 which, through normalization by a predetermined factor, could again have the value d. It will be shown in which columns of second check symbols this non-zero symbol 2540 would have effects. First of all, shifting the diamond pattern of Figure 2 upwards by one block would again give code words in all three columns 40, 42, 44, due to the semi-cyclic character of the code.
  • FIG. 3 shows a diamond code in systematic form. There is a single grey column that contains s information symbols of arbitrary value. This causes p Cl check symbols in the same column that may be made non-zero through the encoding, as well as in subsequent columns. In the next q rows the non-zero C2 check symbols may occur only in the hatched region. The dotted line starting from the top symbol of the data column determines the slanted edge at the right hand side.
  • the shape of the elementary diamond (including one user symbol) is also given in dotted lines.
  • the slanted edges of the various regions have been given as straight lines. In practice such edges follow the discrete positions of the symbols, and the region has stepped edges (cf. Figure 17).
  • Figure 4 by way of comparison gives a product code format.
  • Product codes per se are considered common general knowledge.
  • block D of data symbols has a dimension of 6 rows and 7 columns.
  • the code word is calculated.
  • the check symbols in blocks Q QP for each of the eleven columns, i.e. seven columns of data symbols and four columns P of check symbols, the code word is calculated.
  • the block QP contains the row check symbols for which the column check symbols in block Q operate as data symbols. Thus, the additional two row code words need not be calculated.
  • the generating of the check symbols according to the present invention positions the symbols of a particular code word in a convolution-like manner, although the production rules of the constituent codes are pure block codes.
  • the present code has a property that corresponds to one of a product code: the second check symbols bring about error protection for the data symbols, for the first check symbols, and for the second check symbols themselves, and the first check symbols also bring about error protection for the data symbols, for the first check symbols themselves, and for the second check symbols.
  • the reason is that the first check symbols are calculated through the retrocoupling described with reference to Figure 1.
  • An extra advantage of the type of encoding of the present code versus product codes is that about 50% less storage space is required for the processing as compared to product codes. Additional advantages with respect to the CD format are reduced decoding latency and simplified block synchronization.
  • Figure 5 gives an exemplary block diagram of an elementary encoding device wherein the sizes of the code-words have been substantially restricted in order to show the various delays as clearly as possible.
  • Figure 6 gives positions of the various code symbols.
  • On the carrier the symbols of any particular column may be stored contiguously, column by column.
  • the first check symbols are formed on the basis of a single column as indicated by a first rectangle in Figure 6.
  • the second check symbols are formed on the basis of a diagonal string of symbols as indicated by a second rectangle in Figure 6.
  • the second code words may have a greater depth of interleaving, for example in that any particular word of the second code has symbols in every second, third, etc. column.
  • the data symbols 1.9, 2.9 and 3.9 arrive from the left in a first arranging state at the input of the first encoder for producing the first check symbol 4.9.
  • a plurality of first check symbols is produced, because a single check symbol does not render a symbol error correctable; indeed, it is desirable that each code word on its own in principle renders at least one symbol error correctable.
  • the delay incurred by the generation process in block 150 is ignored.
  • delay block 152 the realignment for producing a second arranging state is effected.
  • the delays differ by one column period, and decrease from three periods to nominally zero.
  • the indications are shown of the symbols arriving at that particular instant, thereby realizing the second arranging state. From the four symbols thus received the second encoder produces the two second check symbols 5.10 and 6.11.
  • the second check words are delayed so as to be in concord with the first arranging state at the input of the first encoder 150.
  • the delays again differ by one column period, and the indications of the second check symbols arriving at the input of the first encoder 150 are 5.9 and 6.9, respectively, and belong to the same column as the data symbols arriving there. This means that the first encoder produces the correct column that may be transferred to the storage medium or carrier as indicated by the arrow 158.
  • the time could run in the opposite direction in the Figure, so that inputs and outputs are interchanged.
  • the delays could be implemented in RAM. In that case the delays as well as the feedback are realized by appropriate addressing of the RAM.
  • the matrix multiplications necessary for encoding can be effected by means of suitably programmed standard hardware, or by special purpose hardware. If the two codes have sufficient likeness, parts of the encoders could be used in common.
  • odd-even interleaving can be applied: see the above prior art references. This means that odd-channels are delayed by a uniform amount with respect to the even channels, or vice versa.
  • the odd-even interleaving is applied to the information transferred to the carrier as indicated by reference numeral 158. Odd-even interleaving then is to be applied to the decoder as well, inverse to that applied to the signals supplied to the carrier 158.
  • Block 159 in Figure 7 can be modified to take this interleaving into account.
  • a further improvement can be provided by scrambling at the output; this is effected by adding a systematic bit pattern to the stream of encoded symbols. This solves problems caused by a malfunctioning apparatus generating zero bits only.
  • Figure 7 gives a detailed explanation of the decoding to conform with the set-up of Figures 5, 6.
  • Block 159 is the first decoder for the first code words.
  • the decoding is supposed to be instantaneous, so that the symbol numbering is not influenced by the decoding. Any actual delay, however, would not alter the reasoning.
  • the symbols are delayed with monotonously decreasing delays (D) in block 160, causing the respective symbols of one second code word to be realigned at the input of second decoder 162.
  • the decoding is again supposed to be instantaneous. If the decoding has satisfactory results, the output of the second decoder 162 may be forwarded to a user directly via a second delay stage 164 which has the inverse delays values as compared to block 160. If not, the output of second decoder 162 is forwarded to the user via second delay stage 164 and a third decoder stage 166. In this latter option, the first code word is presented to third decoder stage 166 that in fact may share hardware with the block 159. If the Cl and C2 codes are sufficiently alike, also block 162 could join in the sharing. At the output 168 the user symbols are presented. In case the third decoding operation is foregone, it may nevertheless be advantageous to keep the second delay stage 164, be it only for the user symbols. If necessary, the second code words may be reconstituted and decoded again by repeating the block 162, 160.
  • Figure 8 shows a block diagram of a decoding device of more realistic dimensions.
  • the stream of encoded symbols arrives at input 114 that again may be 8 bits wide for eight-bit symbols.
  • Block 116 is the input storage that takes up the symbols according to order of arrival and according to a selection mechanism that assigns the symbols to their original channels. The delay allows the various symbols to be presented to the first decoder stage 118 at the correct instants. Decoder 118 needs to receive the incoming symbols at the same data rate as the input 114; for each code symbol received it first determines the contribution thereby to the various preliminary syndrome symbols of the word of the first code to which the symbol in question belongs, as symbolized by the exclamation mark in block 130.
  • the decoder executes the decoding proper which may have various ones of the standard outcomes: find that the code word is correct and thus forego any correction (a), find certain errors correctable and correct them according to findings (b), or detect that the word is uncorrectable at least as far as the correction strategy goes (c).
  • Case (a) may assign to all symbols of the correct word an O.K. flag.
  • Case (b) may selectively assign to the corrected symbols of the code word in question a correction flag and for the remainder again the O.K. flag.
  • Case (c) may assign to all symbols of the code word in question an unreliability flag, which flag may further specify various unreliability levels.
  • the use of flags per se as produced by an earlier processing stage such as the demodulation has been taught by both references I, II.
  • Block 120 is the intermediate storage to align the code symbols, inclusive of second and first check symbols, for processing by the second decoder stage 122.
  • Block 122 in a similar way as the block 118, calculates the syndrome symbols associated with the second code words and executes the decoding and in principle has the same three possible outcomes as the decoder 118.
  • the strategy may be different: firstly because many errors will have been corrected already by the earlier stage 118, and secondly because additional help is provided by the unreliability flags provided by the first decoding stage that may be used as erasure pointers, and by the O.K. flags that may advise on the maximum numbers of error symbols and erasure symbols, respectively, to be decoded. In consequence, after the second stage the number of residual errors generally has diminished.
  • the decoding of the second code words has been indicated by the exclamation mark in block 132.
  • Block 124 is the intermediate storage to align the code symbols, inclusive of second and first check symbols, for processing by the third decoder stage 126.
  • Block 126 in a similar way as the block 118, calculates the syndrome symbols associated with the first code words and executes the decoding and in principle has again the same three possible outcomes as the decoder 118. However, the strategy may again be different as explained with respect to the decoder stage 122. Furthermore, due to the intermediate passage through the second decoder stage, the number of residual errors subsequent the third stage generally is still less than subsequent to the second decoder stage.
  • the decoding of the first code words has now been indicated by the exclamation mark in block 134.
  • the hardware of the third level decoder can to a fair extent be shared with the hardware of the first stage, in case the codes are identical, although the strategies applied generally are not.
  • the hardware pertaining to the Cl and C2 codes, respectively, may also be shared if the codes have corresponding character, in particular if one code is a sub-code of the other.
  • Another difference with respect to the Compact Disc system consists in that the latter has decoding in opposite sequence with respect to encoding. According to the present invention, the sequence of decoding s is in principle arbitrary.
  • Block 128 is the output storage that takes up the data symbols for sequentially correct presentation to serial output 130. Generally speaking, the check symbols will not be considered further thereafter.
  • Figure 9 shows a physical symbol disposition on a carrier. These data form a source for the decoding.
  • the format has a synchronization header labeled SYNC, and an auxiliary header part labeled ADD. The latter can be used for storing information that does not directly belong to the main body of information, such as an address.
  • the format can be defined in such a way that only a predetermined fraction of the formats as shown effectively gets the parts SYNC and/or ADD.
  • each format has alternating symbols labeled X and Y, respectively, to effect an odd-even interleave among the symbols. This is a countermeasure against short error bursts. Within the sequence of symbols, such as 1.1X ... 6.
  • the symbols are stored monotonously with respect to their occurrence in the first arranging state as shown by their numbers, inclusive of the associated first and second check symbols.
  • the number of symbols of the various code words is much higher than six. Note that the notation is different from the one in Fig. 6 that shows the various channels which here are serialized. For simplicity, extra effects through scrambling have been ignored.
  • the user data are supplied in segments, for example of 16 kbytes each.
  • the data of a respective segment are written into respective storage blocks, together with the parity or check symbols associated with those data.
  • a change in the data of a specific storage block and an update of the parity symbols should preferably be accomplished without affecting the data or parity symbols in other storage blocks.
  • the encoding method discussed above may benefit from a modification in order to improve its efficiency.
  • the modification of data of a single Cl-word influences not only the Cl check symbols of this particular word, but also the next-following s+q-1 Cl-words, see Figure 3.
  • the total number of columns containing check words relating to this datablock is m+127.
  • Figure 13 shows encoding of repeated data blocks, each of which separately has the dimensions of the single block of Figure 12.
  • a code word of the new block code is an mxn matrix 900 as shown in Fig. 10.
  • the matrix 900 has columns, for example column 902, rows, for example row 904, and cyclic diagonals, for example cyclic diagonal 906.
  • a cyclic diagonal is an arrangement of respective matrix elements that are in respective ones of successive columns and in respective ones of successive rows, the rows being cyclically continued. For example, as shown in the drawing, whenever a cyclic diagonal with an orientation from left to right and from top to bottom reaches the right-hand edge of the matrix, it is cyclically continued at the left-hand side.
  • the matrix 900 contains a number of m cyclic diagonals of this orientation.
  • Each of the matrix columns is in Cl and each cyclic diagonal is in C2.
  • Decoding of a block code word can be achieved by combining decoders Cl and C2 as described above. Encoding of such relatively broad cylinders is explained with reference to Figure 11, showing an (n-l+2m)xn matrix 1000.
  • the first n-1 columns at the left contain zeroes and are referred to hereinafter as the all-zero columns.
  • the next m columns are called data columns.
  • Each data column comprises s data symbols in the s top rows and p+q parity symbols in the p+q bottom rows.
  • the last m columns are called the lead-out columns.
  • Each of the lead-out columns contains only zeroes in its s top rows. Note that owing to the properties of encoding described above the last m-(s+q-l) lead-out columns contain zeroes only.
  • the parity symbols in the data columns and in the lead-out columns are computed according to the manner explained above in order to make all these columns Cl- words and to make all diagonals with at least one element in the data columns C2-words.
  • the i-th column of the block code word equals the sum of the i-th data column and the i-th lead-out column.
  • all columns of the block code word are in Cl .
  • all cyclic diagonals are in C2.
  • the parity symbols in the lead-out columns are combined with those of the data column through a logic operation, for example EXOR.
  • Figure 14 shows cylindrically encoded data blocks, extending the performance of the arrangement according to Figure 12.
  • part of the redundancy information is identical to that produced in Figure 12, but another part is produced by superposing the "tail" at the right in Figure 12 over the region directly below the user symbols.
  • C2 code words denoted by arrows: one that runs in a straight manner from top left to bottom right, and one that is wrapped around, so that it starts again at the left- hand side after having reached the right-hand side.
  • the device disclosed can be used for encoding in the following manner.
  • the contents of the delay means for example the delay block 152, are set to zero.
  • the ms data symbols are applied to the encoding device.
  • the Cl and C2 parities for the data columns are computed and stored.
  • (s+q-l)s zero symbols are applied to the encoder device and each computed parity symbol is added to the parity symbol generated a time period of m Cl words before.
  • the addition can be accomplished either on a Cl-word- to-Cl-word basis or using partial or full parallelism. A further extension of the above will be discussed hereinafter.
  • this aligning of short bursts with odd-even interleave is shown in Figure 15.
  • the solution is shown in Figure 16, involving a collective and uniform transposition of low-numbered channels after the interleaving delay shown by a block, to high-numbered channels, and inversely for the low numbered channels.
  • This permutation can be effected in various other ways, such as by permutation within a fraction of the s sequences.
  • the inverse measure is undertaken. 5.
  • the so-called cylinder-storage for limited length blocks within a short- length stretch of the medium has been considered.
  • the odd-even permutation under #4 should then be performed on a block basis.
  • the cylinder after the C1/C2 encodings consists of n rings, n being the codeword length (i.e. the total number of rows).
  • the even rings should be uniformly rotated over one position relative to the odd rings.
  • the delayed symbols, or alternatively the undelayed symbols should then be permuted as described above.
  • the odd/even deinterleave should not be undone before delivery at the user location. In fact, confinement of errors is only possible if erroneous bytes are known and optimally such bytes should be detected by decoding the Cl code that would be the best indicator. Therefore, odd/even interleave in the encoder should only be present as a postprocessing stage after the other encoding and before the data are written on a carrier. Likewise, in the decoder the odd/even deinterleave should only be present as a preprocessing stage before the data enters the Cl decoder for the first time. 6. Upon decoding, the output can be fixed at the output of block 166, that is after the second Cl decoding as shown in Figure 7.
  • Another solution is the following: if the first Cl decoding in the block 159 is sufficiently successful, the output of the block 159 is directly connected to a user. If the first decoding is not sufficiently successful, the output of the block 166 is connected to the user.
  • the presentation to the user in always in the correct sequence of symbols. Supplying the user information at an earlier stage of decoding will speed up the access. Outputting may alternatively be after block 164.
  • Figure 17 shows an improved storage organization that features unequal error protection. The idea is based on the fact that a sector may contain 2048 user bytes plus
  • SUBSTITUTE SHEET S 2o particular header information consisting of a few bytes.
  • This header information often contains an address, counter data or other information that is used for selectively accessing one or more particular sectors.
  • the header in each sector constitutes part of the first Cl word and as such is protected by both the Cl correctability and by the C2 correctability.
  • the sector format still has a few spare bytes. These now are put into the first Cl word of the sector and filled with additional Cl check words, thereby improving the error protection for the header.
  • the enhanced code Cl' is a subcode of the original code Cl; this allows double use of hardware and/or software facilities.
  • Cl' has T more check symbols than Cl, there should be at least a number of (T+q-1) Cl words between the Cl ' word encoding header information from a sector and the first Cl' word encoding header information from the next sector.
  • T+q-1 the Cl ' code words containing the headers are decoded. Only if the correct decoding of a Cl' code word in question proves to be impossible, it would be necessary to go for the complete decoding of the associated Cl words and C2 words. Because usually only the first Cl' word needs to be decoded, access to the header is extremely fast. However, even in case the Cl' word decoding fails, still the full decoding is still not always necessary.
  • the sectors can be numbered in a monotonous but unevenly spaced sequence. If the predecessor sector has a lower number than sought and the sector in question has an uncorrectable Cl' header word, first the next sector is tried. It is only if the latter has a higher number than sought that the full decoding of the intermediate sector is undertaken. If this UEP (Unequal Error Protection) feature is used in combination with the cylindrical storage as taught under #3, the extra-protected Cl words have their redundancy mapped on top of other extra protected Cl words in order to keep the limited extension of their parities intact.
  • UEP Unequal Error Protection
  • Figure 18 shows a finite support or size convolution ⁇ diamond code word; it generally corresponds to Figure 12, but has two additional check symbols per C2 codeword.
  • the smallest addressable storage block contains 8 sectors of 2088 data bytes each. Each sector is stored in 18 columns, because each column has 116 data bytes. The necessary on-disc space now amounts to 129 additional columns, so that at this level the efficiency is only about 44%. For a single sector, the storage efficiency is even much lower, i.e. of the order of 10%. These figures are generally considered much too low.
  • Figure 19 shows a block-convolutional diamond code word that adds 14 columns of redundant symbols, which number is exactly equal to the number of C2 check symbols per codeword. Even for a block having only a single sector of user words the efficiency is thus raised to about 47% .
  • the number of extra parity columns is independent of the width of the information block.
  • each column is a code word of the Cl code and each diagonal is a code word of the C2 code.
  • the latter code word includes the zero symbols at the right outside the block indicated in Figure 19. If applicable, also the zero symbols at the left outside the block of Figure 19 are included.
  • the codes used are linear codes, which means that the sum of two code words is again a code word.
  • Figure 20 shows a concatenation of code blocks according to Figure 19. This type of formatting is very advantageous for a storage organization where writing of fresh data on the medium is allowed next to the reading.
  • the heavy arrow shown runs along a particular diagonal, i.e. in the direction of the C2 code words.
  • Each of the two "blocks" crossed by this arrow contributes a separate valid code word, regardless of the distance between two blocks, even if this distance is zero. It is not necessary that the blocks are of equal size. This means that once the start of a particular block in a sequence of blocks is known, that block may be decoded, without keeping track of any other block, by stuffing any other symbol on a C2 diagonal with zeroes outside the inner contents of the block(s) in question. This comes down to simulating an artificial, error-free information environment.
  • the storage format as described has two purposes.
  • the long tail at the right in Figure 18 need no longer be present, thus raising the efficiency of the storage.
  • linking information or synchronizing information is required that allows the decoder clock to be resynchronized to the medium synchronization, particularly at the start of each block.
  • such linking information is preferably replaced by columns of only zeroes or is completely skipped inasmuch as its contents are inconsequential.
  • the length of such synchronizing information is arbitrary, provided it corresponds to a multiple of columns. If a player or decoder can recognize such synchronizing information, all arbitrary data formats can be intermixed and at the same time read by the standard Diamond decoder without compromising on corrective power. If a synchronizing information cannot be recognized by the decoder, the associated column is erased, which causes a slightly lower corrective power. Provided that the synchronization mechanism does not become desynchronized, a mixed sequence of contiguous blocks according to the above can then still be read correctly. In practice, the size of such synchronizing information corresponds to about three columns.
  • Figure 21 shows the preparation of a block for encoding.
  • Encoding is effected as a sequence of two successive steps.
  • the first step consists of the preparation of the information symbols of the parity-only columns (here fourteen) at the right such that the encoder arrives at the all-zero state at the end of the encoding of the last parity column.
  • this can be done by using the standard C2-code encoder for this limited number of symbols.
  • the information symbols present in the C2 code words to be formed in this way are treated as being the lowest-order information symbols contained in these code words, as indicated by the diagonal arrows.
  • the check symbols so generated are put in positions that are data symbols of C2 code words.
  • the column-wise and further diagonal encodings are undertaken in the standard manner as explained earlier.
  • b for each data symbol of the rightmost column, except for the lowest data symbol thereof, the associated C2 code word is formed; these are shown hatched.
  • the order of generating is arbitrary. The lowest data symbol will be considered under point #c.
  • c starting from right, with respect to the lowest information symbol of the information column in question, a pair of code words is formed, that contains first a C2 code word, and next a Cl code word. The latter occupies the column wherein the final Cl parity symbol of the Cl code word just formed, is positioned.
  • the C2 parity symbols operate as data symbols for one or more subsequent Cl code words, and vice versa.
  • the order of generating is mandatory, except for the last Cl code word that may be delayed. All C2 code words of part b must be generated before the first Cl code word of part c. There is no interrelationship in the sequence of execution between parts a and c. d: after generating all pairs of parts a and c, a diamond shape containing pXq parity symbols remains to be generated. According to Figure 22, these are formed as q Cl code words; this necessitates the final C2 code word of part a.
  • the parity symbols are located in a series of consecutive, although not necessarily final, positions of the code word.
  • the decoder must synchronize to the start of a new column of symbols. Synchronization on the sector level is not expressly needed, because any word that is present on a diagonal is a word of the C2 code. If a diagonal contains more than one word, these are concatenated words of the C2 code, which means that the decoder will always be operative. Of course, knowledge of the beginnings of the respective C2 words allows to separate them, which raises the correction capability of the decoder.
  • any Diamond sector independent of the sector size, may be shifted horizontally along the lines shown, while still remaining a code word. Moreover, through the linearity of the codes used, symbol- wise addition of two code words again produces a code word.
  • a practical computational sequence would be as follows: first calculate part b, then subtract as shown in Figure 24. then calculate parts a, c, d as in Figure 25, and finally add the last q parity columns to the first q columns as shown in Figure 26.
  • the generation of the parities of the upright tail can be done efficiently with a feedback shift register encoder operating according to g2(x) that is the ge ⁇ nerator polynomial of code C2.
  • the heavy arrows show one composite C2 code word for m about equal to 44.
  • the shift register contains the q parity symbols pertaining to the C2 code word that should then be written at that part of part b: these parity symbols have been indicated by the arrows extending from the data block to the right in Figure 27.
  • Figure 28 illustrates a modified processing method for the narrow (m ⁇ s) cylinder format.
  • the lower p+q rows of parities are calculated on the basis of the data symbols.
  • the latter symbols are modified however by subtracting from the first q co- lumns thereof the correspondingly positioned C2 parities from the q column of part b as discussed with reference to Figure 25.
  • the so subtracted symbol is on the same row, but m positions to the right.
  • For q ⁇ m no more than one subtraction from each data symbol is necessary.
  • the procedure is modified: from each data symbol of the first m columns is subtracted the parity symbol on the same row, but m positions to the right, and also the parity symbols 2m, 3m ...
  • the data symbols will be stored in an appropriate RAM memory.
  • the accessing of the necessary symbol locations is by loading the address generators with the correct addresses, and presenting the symbols themselves to Galois Field arithmetic.
  • a Diamond decoder according to the foregoing is present that also may serve for generating the parity symbols in the writing mode.
  • an easy way of Cl word en ⁇ coding may be by using the Cl word decoder, while treating all parity symbols as erasure symbols.
  • Cl parity symbols generally fill completely the rows in which they occur of the strip of symbols, where in particular in Figure 23 part a has maximum size (and in consequence part c is national only).
  • nairow (m ⁇ s) data block the number of C2 words is larger, at a generally lower number of symbols, than the number of C2 words necessary for deco ⁇ ding, because various C2 words after encoding are aggregated; this has been shown by the folding in Figure 27.
  • their data contents for the separate and for the composite words are identical. This may mean that encoding by means of an erasure decoder may take too much time.
  • a different approach for encoding narrow blocks is based on the recognizing that the usage of two semi-cyclic codes in the case of very narrow strips may be less than optimum. This is seen best for a strip that contains only a single Cl code word: in that case, the Cl code word and the C2 code word would no longer add their protection capabilities together, because they would share zeroes. It has been found that an improved degree of error protection can be attained by making p and q variable, while keeping their sum constant, such depending on the width of the block as measured in Cl code words. An extreme solution is to render the value q equal to zero, as soon as the block width is lower than a predetermined bound.
  • Detecting of the block size can be done on the basis of a size indicator included in the block header.
  • the feature of narrow block is particularly useful with computer data and the like, as distinct from audio-video data. The latter are often of relatively huge size.
  • various parts of the hardware can be rendered shared for interspersed blocks with various different values of q.
  • a carrier such as a disk, there are essentially no technical blockades to such interspersing, once encoder and/or decoder can cope therewith.

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Abstract

Un signal numérique est transmis sous forme d'une pluralité de (s) séquences de symboles d'information ayant la même longueur en bits. Chaque séquence se trouve dans un canal d'entrée qui lui est propre, les mots de contrôle étant inclus dans la transmission par codage. Un premier bloc de symboles, un de chaque canal d'entrée, est soumis, disposé selon un premier agencement, à un premier codeur correcteur d'erreurs pour générer une série de (p) symboles de premier contrôle. Puis chaque symbole du premier bloc et chacun des (p) symboles de premier contrôle sont différés d'un retard différent de manière à obtenir un second bloc de symboles disposé selon un second agencement et soumis à un second codeur correcteur d'erreurs. Cela génère une série de (q) symboles de second contrôle destinés à être transmis. Les symboles de premier et de second contrôle sont générés pour satisfaire des matrices de contrôle de parité ayant respectivement (s+p+q) colonnes et (p) et (q) lignes de codes semi-cycliques. Le retard transforme des symboles contigus disposés selon le premier agencement en des instances contiguës disposées selon le second agencement et les (q) symboles de second contrôle sont renvoyés au premier codeur disposés selon le premier agencement.
EP95907126A 1994-02-16 1995-02-14 Procede et dispositif de transmission de donnees a correction d'erreurs fonde sur des codes semi-cycliques Withdrawn EP0698269A1 (fr)

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EP94203394 1994-11-22
EP95907126A EP0698269A1 (fr) 1994-02-16 1995-02-14 Procede et dispositif de transmission de donnees a correction d'erreurs fonde sur des codes semi-cycliques
PCT/IB1995/000100 WO1995023384A2 (fr) 1994-02-16 1995-02-14 Procede et dispositif de transmission de donnees a correction d'erreurs fonde sur des codes semi-cycliques

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EP0850473B1 (fr) * 1996-06-13 2002-11-27 Koninklijke Philips Electronics N.V. Procede et dispositif servant a effectuer une correction de paquets d'erreurs sur des pistes dans un format de stockage a pistes multiples
JPH1074613A (ja) 1996-08-30 1998-03-17 Tokin Corp テープ、粘着テープ及び自己融着テープ
US6725412B1 (en) * 2000-08-15 2004-04-20 Dolby Laboratories Licensing Corporation Low latency data encoder
AU2003249708A1 (en) * 2002-07-03 2004-01-23 Hughes Electronics Corporation Method and system for memory management in low density parity check (ldpc) decoders
US7418644B2 (en) * 2004-03-01 2008-08-26 Hewlett-Packard Development Company, L.P. System for error correction coding and decoding
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US4998252A (en) * 1987-08-06 1991-03-05 Sony Corporation Method and apparatus for transmitting digital data
US5224106A (en) * 1990-05-09 1993-06-29 Digital Equipment Corporation Multi-level error correction system
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