EP0685857A1 - Chip-induktivität Anordnung - Google Patents
Chip-induktivität Anordnung Download PDFInfo
- Publication number
- EP0685857A1 EP0685857A1 EP95303410A EP95303410A EP0685857A1 EP 0685857 A1 EP0685857 A1 EP 0685857A1 EP 95303410 A EP95303410 A EP 95303410A EP 95303410 A EP95303410 A EP 95303410A EP 0685857 A1 EP0685857 A1 EP 0685857A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- substrate
- layer
- inductor
- chip device
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 229910000679 solder Inorganic materials 0.000 claims abstract description 38
- 238000001465 metallisation Methods 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000004642 Polyimide Substances 0.000 claims abstract description 9
- 229920001721 polyimide Polymers 0.000 claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 25
- 229910052802 copper Inorganic materials 0.000 claims description 25
- 239000010949 copper Substances 0.000 claims description 25
- 238000007747 plating Methods 0.000 claims description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 claims description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical group [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 239000011651 chromium Substances 0.000 claims description 6
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910001120 nichrome Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910017083 AlN Inorganic materials 0.000 claims description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 2
- 238000010344 co-firing Methods 0.000 claims description 2
- 238000005470 impregnation Methods 0.000 claims description 2
- 239000007791 liquid phase Substances 0.000 claims description 2
- 230000000712 assembly Effects 0.000 abstract 1
- 238000000429 assembly Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 45
- 235000012431 wafers Nutrition 0.000 description 19
- 239000000463 material Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 239000011230 binding agent Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- QGVYLCICHZYPJA-UHFFFAOYSA-N [Cr].[Cu].[Au] Chemical compound [Cr].[Cu].[Au] QGVYLCICHZYPJA-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- VVRQVWSVLMGPRN-UHFFFAOYSA-N oxotungsten Chemical class [W]=O VVRQVWSVLMGPRN-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000011573 trace mineral Substances 0.000 description 1
- 235000013619 trace mineral Nutrition 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/29—Terminals; Tapping arrangements for signal inductances
- H01F27/292—Surface mounted devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
Definitions
- the invention concerns an inductor chip device, and in particular, but not exclusively, an inductor chip device for mounting on a multichip module, a direct-chip-attach assembly, or a surface-mount assembly.
- Very compact inductors have also been realised in an integrated form within the upper metallisation layers of a multichip module substrate structure. Such inductors can provide inductance values between 1 and 100 nH within a 1mm square footprint, with self-resonant frequencies between 20 GHz and 500 MHz. Q-factor in these multichip-module inductors is determined by the inductor resistance at low frequencies, while the peak Q-factor is related to the nature and dielectric structure of the substrate employed. High-resistivity silicon substrates with inductors defined in an aluminium-polyimide multichip-module structure can provide Q-factors between about 5 and 20, depending upon the inductor structure and inductance value. The peak Q-factor occurs at a frequency between one-quarter and one-half the self-resonant frequency.
- an inductor chip device for mounting on a multichip module, on a direct-chip-attach assembly or on a surface-mount assembly, comprising a dielectric substrate, a spiral metallisation structure defined on one major surface of the substrate, and a plurality of solder bumps for effecting said mounting defined on the other major surface of the substrate, the spiral structure being electrically connected to the plurality of solder bumps by means of metal-filled vias.
- the capacitance of the inductor to ground is minimised and therefore the self-resonant frequency is maximised.
- the capacitance to ground will be determined essentially by the dielectric constant of the substrate and its thickness, a greater thickness giving a lower capacitance and a higher self-resonant frequency.
- the geometry of the inductor structure may be a circular, square, rectangular or polygonal spiral configuration.
- a square format is to be preferred, whereas if the inductor device is to be mounted onto a direct-chip-attach or surface-mount device, a rectangular format is preferable.
- the substrate may be either a pre-fired alumina or aluminium nitride substrate with vias formed by the laser-drilling of the substrate when in its pre-fired state and by the filling of the holes thereby produced by a copper-tungsten composite material produced by a liquid phase impregnation process.
- the substrate may be a co-fired alumina substrate, the vias being sintered tungsten or molybdenum vias formed in the substrate during co-firing.
- the spiral structure may be a copper metallisation structure, and may be photolithographically defined.
- Use of copper for the metallisation minimises the series resistance of the inductor and therefore maximises the Q-factor.
- Defining the inductor geometry by means of a photolithographic patterning process enables very accurate inductor dimensions to be achieved, and ensures therefore a high reproducibility of inductance value from device to device.
- the spiral metallisation structure may comprise a thin, metallic adhesion layer, a plating seed layer and a thick copper layer, deposited in that order on the substrate.
- the adhesion layer may be a chromium, titanium or nichrome adhesion layer
- the plating seed layer may be a copper plating seed layer.
- the solder bumps are preferably formed on a multilayer metallisation structure comprising a chromium adhesion layer, a chromium-copper layer, and a copper or copper-plus-gold layer deposited in that order on the substrate.
- the inductor chip device may include at least one further metallisation layer and dielectric layer, the spiral structure being defined in the metallisation layer formed on the major surface of the substrate and in the at least one further metallisation layer.
- the at least one further dielectric layer may be a polyimide layer.
- the advantage of employing a multilayer structure is that the inductance value may be significantly increased.
- an approximately fourfold increase (2 squared) in inductance per unit area may be achieved for a given number of turns, n.
- At least one further solder bump may be included to ensure mechanical stability when the inductor device is mounted on a multichip-module device, etc.
- the minimum number of solder bump connections that is required is that number which effects the necessary electrical connections between the inductor structure and the multichip-module device, etc.
- the electrical connections may include not only end connections to the inductor, but also one or more tap connections inbetween. However, where the total number of electrical connections in the inductor chip device is insufficient to maintain mechanical stability when the chip device is mounted, extra non-electrical solder bump connections may be needed.
- the absolute minimum number of solder bump connections may therefore be said to be three, but four such connections would be a normal practical minimum.
- an inductor chip device for mounting to a multichip-module assembly comprising an alumina substrate 12, on one major surface 13 of which is disposed a metallisation layer 14 configured as a square spiral. On the other major surface 15 is disposed a further metallisation layer 16 configured as a number of pads or islands, upon which are formed a corresponding number of solder bumps 17.
- the two ends 20, 21 of the spiral inductor structure are electrically connected to two of the solder bumps 17 through two metal-filled via structures 18 and 19, respectively.
- the two bumps to which the via structures 18, 19 are connected are shown as 22 and 23, respectively in Figure 2.
- additional bumps 24-26 which serve not to electrically connect the inductor to the multichip-module assembly (not shown), but to ensure a firm seating of the inductor chip on the assembly.
- the inductor chip device is flip-chip solder-bonded to mating solder-bump, or other, structures on the multichip-module device.
- the substrate 12 and metal-filled vias of the inductor chip device may be fabricated by a process such as that described in patent specification GB 2,226,707 in the name of Micro Substrates Inc.
- a high-density, polycrystalline alumina ceramic wafer with a well defined surface finish and a uniform thickness may be first processed to provide an array of narrow holes through the thickness of the wafer. This may be achieved by a laser drilling process, using a CO2 or neodinium-YAG laser source, to produce narrow ( ⁇ 125 ⁇ m diameter) holes which are slightly tapered from front to back. The disposition of the holes will follow the pattern shown in Figure 2.
- the array of through wafer holes may then be filled with a conducting, metallic plug via structure using a copper-tungsten liquid-phase-impregnated composite structure.
- the tungsten material is employed in a powder form in an organic binder and solvent carrier system and the via holes are filled with the tungsten powder "ink" by a screen-printing process, assisted by vacuum or applied pressure.
- any excess tungsten ink may be removed and the wafer fired in a partially oxidising atmosphere (for example, wet hydrogen) to burn off the organic binder and to partially sinter the remaining tungsten powder without the formation of tungsten oxides.
- a peak process temperature of 1400-1600 °C may be required for this process stage.
- a partially oxidising atmosphere is also important in this step to ensure good adhesion between the tungsten plug metallisation and the alumina ceramic.
- the resulting structure comprises a porous tungsten via in every laser-drilled through-via in the alumina wafer.
- a fully dense plug via structure may then be achieved by the infiltration of liquid copper into the porous tungsten via.
- the copper may be applied by the screen-printing of a copper "ink” material or by a similar process, followed by the heat treatment of the wafer to remove the binder, if one is employed, and then to melt the copper (typically in an hydrogen atmosphere at above 1083 °C).
- the liquid copper naturally wets the tungsten, particularly in the presence of certain trace element (surface) additives such as nickel, and thus fills the porous plug via structure to create a solid plug via on cooling to ambient temperature. Any excess material may then be removed by a final lapping and polishing operation that also provides the required surface finish and wafer thickness.
- Wafers may conveniently be produced at dimensions identical to those of silicon IC wafers, for example 100 mm diameter, 380 ⁇ m thickness or 150 mm diameter, 525 ⁇ m thickness, to facilitate processing.
- the use of a solid via structure greatly facilitates subsequent processing of the wafer since a polished, planar surface is provided that can be readily coated with resist, polyimide or other processing materials by IC-like spin-coating processes.
- a planar surface also aids low defectivity and low particulate levels in wafer processing.
- the inductor structure is then defined on one face of the wafer.
- a thin metallic adhesion layer (using a reactive metal system such as chromium, titanium or nichrome) and a plating seed layer (in the form of a thin copper layer) are sputter-deposited onto the surface in succession. These layers are typically between 0.05 and 0.5 ⁇ m thick.
- the adhesion layer provides a strong bond to the alumina surface and also a good electrical connection to the copper-tungsten solid plug vias.
- the copper layer provides a compatible surface onto which to plate additional copper.
- a thick layer of a photoresist material is applied to this face of the wafer and patterned to define a spiral opening structure into which the copper metallisation that forms the inductor itself is then plated.
- the copper plating should be of the maximum thickness consistent with good control of the plated structure and small spacing between the inductor turns (for lowest resistance at a given inductor pitch and hence maximum Q-factor).
- the inductor geometry will be limited by the resolution and feature aspect ratios that can be defined in the resist, together with the properties of the plating solution (throwing power and plating efficiency). Materials exist that can allow at least 25 ⁇ m copper thicknesses at feature separations of as little as 10 ⁇ m. This should lead to inductor peak Q-factors of at least 100 in inductors of mm dimensions.
- the resist mask and the plating seed layer and adhesion layer are stripped by suitable solvent and etchant treatments from all surface areas apart from where the inductors are defined.
- the completed plated copper inductor structure is coated with a suitable passivation, e.g. a polyimide.
- solder bump structures are defined, some over the exposed copper-tungsten plug vias that make the connections between the inductor input and output points on the other face of the wafer, and some at other points on the surface, as will be explained below.
- the solder bump structure requires a solderable metallisation layer to which the solder bump itself is wetted and which defines the area of the solder bump.
- Chromium-copper or chromium-copper-gold multilayer metallisation structures are suitable for this requirement.
- the first, chromium, layer provides adhesion and an ohmic connection to the underlying copper-tungsten plug via surface, while an alloyed chromium-copper layer follows which provides solderability without layer dissolution (for multiple solder bump melting operations).
- the final copper or copper-plus-gold layers provide initial solderability, these metals dissolving into the solder on bump reflow and reprecipitating on cooling as intermetallic compounds of tin.
- the gold if employed, allows the solderable layer to be exposed to the atmosphere without oxidation prior to solder deposition.
- Solderable metallisation layers of this type may be defined by sequential vapour deposition through an etched metal foil or similar physical masking structure.
- the solder itself is a tin-lead eutectic composition (63Sn-37Pb by weight, melting point 183 °C) for direct-chip-attach or surface-mount applications, or is a 95Pb-5Sn composition (melting point 310 °C) for multichip-module applications.
- the solder may be applied by electrodeposition using a seed layer and photoresist masking scheme similar to that described for the plating of the copper inductor structure on the first face of the wafer. Alternatively a physical masking structure may be employed with a vapour deposition process similar to that described for the solderable metallisation deposition.
- the solder may be deposited as separate layers of lead and tin, or as an alloy.
- solder bumps After deposition and patterning of the solderable metallisation and solder layers, the solder bumps are reflowed by heating to above the solder liquidus temperature under inert or reducing atmosphere conditions. Solder bump diameters close to those of the copper-tungsten plug vias are appropriate for the flip-chip inductor structure, i.e. 125 ⁇ m diameter. Bump heights between 30 and 100 ⁇ m are suitable, depending upon whether the inductor is to be used in a direct-chip-attach, surface-mount or multichip-module application. Such bump geometries are also typical for flip-chip solder-bonded integrated circuits for multichip-module and direct-chip-attach applications.
- a total of five solder bumps are defined, two over the input and output plug via connections to the inductor, and a further three distributed across the alumina surface to provide mechanical support for the mounted flip-chip inductor.
- preferred dimensions are 0.5, 1.0, 1.25, 1.5 or 2.0 mm square. This gives some consistency with the trend in discrete surface-mount component sizes, which are currently following a reduction from 0805 (2.0 ⁇ 1.25 mm) to 0603 (1.5 ⁇ 0.75 mm) to 0402 (1.0 ⁇ 0.5 mm).
- the temporary passivation layers which were employed to protect the inductor face are removed, the wafer is inspected and dimensional and electrical measurements are made to determine inductor yield and to ensure that the component characteristics are within the prescribed limits. Any defective inductors are identified, for example by ink marking, and the individual inductor components are separated by mechanical sawing or laser scribing.
- a co-fired alumina substrate is used instead of a pre-fired substrate, the vias being then of sintered tungsten or molybdenum.
- the steps for obtaining the copper spiral metallisation and the solder bumps are as described for the first embodiment.
- a multilayer inductor is formed in a pre-fired substrate by the plating of copper layers separated by a polyimide dielectric. Vias are defined through the interlayer polyimide material by dry etching, in order electrically to link the inductor spirals situated in the inner metallisation layers and that in the outer metallisation layer.
- Dielectric materials other than polyimide may be used for the intermediate layer or layers, and means other than dry etching may be employed for defining the interlayer vias.
- solder bumps Although a total of five solder bumps are shown in Figure 2, more or less may be required, depending mainly on the size of the chip being produced. Also, there may be more than two solder bumps in electrical contact with the inductor metallisation structure. Thus, for instance, an inductor spiral may be tapped at some point or points along its length, or a multilayer inductor may be tapped at its interlayer junctions. These variations require an appropriate number of metal-filled vias to form the electrical connections, and correspondingly fewer solder bumps may then be required purely for maintaining mechanical stability.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Coils Or Transformers For Communication (AREA)
- Semiconductor Integrated Circuits (AREA)
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Manufacturing Cores, Coils, And Magnets (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9411107 | 1994-06-03 | ||
GB9411107A GB2290171B (en) | 1994-06-03 | 1994-06-03 | Inductor chip device |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0685857A1 true EP0685857A1 (de) | 1995-12-06 |
EP0685857B1 EP0685857B1 (de) | 1999-09-08 |
Family
ID=10756121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP95303410A Expired - Lifetime EP0685857B1 (de) | 1994-06-03 | 1995-05-22 | Chip-induktivität Anordnung |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0685857B1 (de) |
JP (1) | JPH07335439A (de) |
AT (1) | ATE184419T1 (de) |
DE (1) | DE69511940T2 (de) |
ES (1) | ES2139841T3 (de) |
GB (1) | GB2290171B (de) |
Cited By (7)
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WO1999033108A1 (en) * | 1997-12-22 | 1999-07-01 | Conexant Systems, Inc. | Wireless inter-chip communication system and method |
DE10144464A1 (de) * | 2001-09-10 | 2003-04-10 | Infineon Technologies Ag | Elektronische Bauteil mit Induktionsspule für Hochfrequenzanwendungen und Verfahren zur Herstellung desselben |
FR2830683A1 (fr) * | 2001-10-10 | 2003-04-11 | St Microelectronics Sa | Realisation d'inductance et de via dans un circuit monolithique |
US6621378B2 (en) | 2000-06-15 | 2003-09-16 | Matsushita Electric Industrial Co., Ltd. | Filter |
NL1036092C (nl) * | 2008-10-21 | 2010-04-22 | Tetradon B V | Werkwijze en inrichting voor een modulair opgebouwde transformator. |
US11367555B2 (en) | 2017-03-01 | 2022-06-21 | Murata Manufacturing Co., Ltd. | Mounting substrate |
US11908617B2 (en) | 2020-04-17 | 2024-02-20 | 3D Glass Solutions, Inc. | Broadband induction |
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GB2292016B (en) * | 1994-07-29 | 1998-07-22 | Plessey Semiconductors Ltd | Inductor device |
US6303423B1 (en) | 1998-12-21 | 2001-10-16 | Megic Corporation | Method for forming high performance system-on-chip using post passivation process |
KR20030048691A (ko) * | 2001-12-12 | 2003-06-25 | 삼성전자주식회사 | 작은 값의 적은 변화를 가지는 고주파 인덕터 및 그 제조방법 |
US8384189B2 (en) | 2005-03-29 | 2013-02-26 | Megica Corporation | High performance system-on-chip using post passivation process |
DE102006057332B4 (de) | 2006-12-05 | 2018-01-25 | Infineon Technologies Ag | Zusammenbau aufweisend ein Substrat und einen auf dem Substrat montierten Chip |
JP6574207B2 (ja) | 2014-05-05 | 2019-09-11 | スリーディー グラス ソリューションズ,インク3D Glass Solutions,Inc | 光活性基板を製造する、2d及び3dインダクタ、アンテナ、並びにトランス |
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WO2020139955A1 (en) | 2018-12-28 | 2020-07-02 | 3D Glass Solutions, Inc. | Annular capacitor rf, microwave and mm wave systems |
KR20210147040A (ko) | 2019-04-05 | 2021-12-06 | 3디 글래스 솔루션즈 인코포레이티드 | 유리 기반의 빈 기판 집적 도파관 디바이스 |
KR102601781B1 (ko) | 2019-04-18 | 2023-11-14 | 3디 글래스 솔루션즈 인코포레이티드 | 고효율 다이 다이싱 및 릴리스 |
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JPS6215850A (ja) * | 1985-07-13 | 1987-01-24 | Oki Electric Ind Co Ltd | マルチチツプパツケ−ジ基板 |
DE3927181A1 (de) * | 1988-08-19 | 1990-03-01 | Murata Manufacturing Co | Spulenchip und herstellungsverfahren dafuer |
GB2226707A (en) | 1988-11-03 | 1990-07-04 | Micro Strates Inc | Ceramic substrate for hybrid microcircuits and method of making the same |
EP0398485A1 (de) * | 1989-05-16 | 1990-11-22 | Gec-Marconi Limited | Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung |
EP0497556A1 (de) * | 1991-01-30 | 1992-08-05 | Sharp Kabushiki Kaisha | Gedruckte Spulenanordnung für doppelte Abstimmschaltung |
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JPS5873127A (ja) * | 1981-10-28 | 1983-05-02 | Hitachi Ltd | Icチツプのはんだ溶融接続方法 |
DE3502770A1 (de) * | 1985-01-28 | 1986-07-31 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung einer flachspule sowie flachspule fuer ein stosswellenrohr |
US5349743A (en) * | 1991-05-02 | 1994-09-27 | At&T Bell Laboratories | Method of making a multilayer monolithic magnet component |
GB2263582B (en) * | 1992-01-21 | 1995-11-01 | Dale Electronics | Laser-formed electrical component and method for making same |
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1994
- 1994-06-03 GB GB9411107A patent/GB2290171B/en not_active Expired - Fee Related
-
1995
- 1995-05-22 DE DE69511940T patent/DE69511940T2/de not_active Expired - Fee Related
- 1995-05-22 EP EP95303410A patent/EP0685857B1/de not_active Expired - Lifetime
- 1995-05-22 ES ES95303410T patent/ES2139841T3/es not_active Expired - Lifetime
- 1995-05-22 AT AT95303410T patent/ATE184419T1/de not_active IP Right Cessation
- 1995-05-23 JP JP7148222A patent/JPH07335439A/ja active Pending
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JPS6215850A (ja) * | 1985-07-13 | 1987-01-24 | Oki Electric Ind Co Ltd | マルチチツプパツケ−ジ基板 |
DE3927181A1 (de) * | 1988-08-19 | 1990-03-01 | Murata Manufacturing Co | Spulenchip und herstellungsverfahren dafuer |
GB2226707A (en) | 1988-11-03 | 1990-07-04 | Micro Strates Inc | Ceramic substrate for hybrid microcircuits and method of making the same |
EP0398485A1 (de) * | 1989-05-16 | 1990-11-22 | Gec-Marconi Limited | Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung |
EP0497556A1 (de) * | 1991-01-30 | 1992-08-05 | Sharp Kabushiki Kaisha | Gedruckte Spulenanordnung für doppelte Abstimmschaltung |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999033108A1 (en) * | 1997-12-22 | 1999-07-01 | Conexant Systems, Inc. | Wireless inter-chip communication system and method |
US6621378B2 (en) | 2000-06-15 | 2003-09-16 | Matsushita Electric Industrial Co., Ltd. | Filter |
DE10144464A1 (de) * | 2001-09-10 | 2003-04-10 | Infineon Technologies Ag | Elektronische Bauteil mit Induktionsspule für Hochfrequenzanwendungen und Verfahren zur Herstellung desselben |
DE10144464C2 (de) * | 2001-09-10 | 2003-07-17 | Infineon Technologies Ag | Elektronisches Bauteil mit Induktionsspule für Hochfrequenzanwendungen und Verfahren zur Herstellung desselben |
FR2830683A1 (fr) * | 2001-10-10 | 2003-04-11 | St Microelectronics Sa | Realisation d'inductance et de via dans un circuit monolithique |
EP1302954A1 (de) * | 2001-10-10 | 2003-04-16 | STMicroelectronics S.A. | Herstellungsverfahren eines Induktors und eines Kontaktlochs in einer integrierten Schaltung |
NL1036092C (nl) * | 2008-10-21 | 2010-04-22 | Tetradon B V | Werkwijze en inrichting voor een modulair opgebouwde transformator. |
US11367555B2 (en) | 2017-03-01 | 2022-06-21 | Murata Manufacturing Co., Ltd. | Mounting substrate |
US11908617B2 (en) | 2020-04-17 | 2024-02-20 | 3D Glass Solutions, Inc. | Broadband induction |
Also Published As
Publication number | Publication date |
---|---|
GB9411107D0 (en) | 1994-07-27 |
ATE184419T1 (de) | 1999-09-15 |
ES2139841T3 (es) | 2000-02-16 |
EP0685857B1 (de) | 1999-09-08 |
GB2290171A (en) | 1995-12-13 |
JPH07335439A (ja) | 1995-12-22 |
GB2290171B (en) | 1998-01-21 |
DE69511940D1 (de) | 1999-10-14 |
DE69511940T2 (de) | 2000-05-04 |
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