EP0650069B1 - Analoges mehrkanaliges Prüfsystem - Google Patents

Analoges mehrkanaliges Prüfsystem Download PDF

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Publication number
EP0650069B1
EP0650069B1 EP94307668A EP94307668A EP0650069B1 EP 0650069 B1 EP0650069 B1 EP 0650069B1 EP 94307668 A EP94307668 A EP 94307668A EP 94307668 A EP94307668 A EP 94307668A EP 0650069 B1 EP0650069 B1 EP 0650069B1
Authority
EP
European Patent Office
Prior art keywords
output
input
outputs
test
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP94307668A
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English (en)
French (fr)
Other versions
EP0650069A3 (de
EP0650069A2 (de
Inventor
Thomas P. Dagostino
Arnold M. Frisch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
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Tektronix Inc
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Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of EP0650069A2 publication Critical patent/EP0650069A2/de
Publication of EP0650069A3 publication Critical patent/EP0650069A3/de
Application granted granted Critical
Publication of EP0650069B1 publication Critical patent/EP0650069B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer

Definitions

  • the present invention relates to analog probe systems, and more particularly to an analog multi-channel probe system for embedment into a device under test (DUT) that provides for high speed analog and digital signals to be routed to points where they may be measured by conventional methods.
  • DUT device under test
  • test points are externally inaccessible due to the spacing of leads on integrated circuits, the density of parts on a printed circuit board, or the burying of such points within a multi-layer multi-chip module or printed circuit board. Therefore testing with conventional instruments and automated test equipment (ATE) is possible only at interfaces where the circuit or board connections are accessible.
  • ATE automated test equipment
  • EP-A-0 481 703 relates to a structure including test circuitry formed on and within a substrate.
  • This document describes a device under test and an embedded analog multi-channel probe system formed on the same substrate, the analog multi-channel probe system comprising:
  • the present invention provides a system comprising a device under test and an embedded analog multi-channel test probe system as set out in claim 1.
  • a plurality of input signals INPUT 0-7 from test points of a device under test are input to respective programmable input buffer amplifiers 12 .
  • Each input buffer amplifier 12 may be selectively enabled by an appropriate input enable signal.
  • the input buffer amplifiers 12 provide high impedance and low capacitance to the input signals to allow minimum loading on the signal being measured, and convert the voltage at the input to a current at the output.
  • the output from each input buffer amplifier 12 is input to respective analog multiplexers 14 .
  • the analog multiplexers 14 each have a number of outputs equal to the desired number of output signals plus one. The particular output line from any of the analog multiplexers 14 on which the signal at the input appears is determined by a select command for each analog multiplexer.
  • the respective outputs less one from the analog multiplexers 14 are input to respective programmable output buffer amplifiers 16.
  • the extra output from the analog multiplexers 14 is for an uncommitted probe as a reference circuit.
  • the analog multiplexers 14 steer the input currents to the desired outputs.
  • Each output buffer amplifier 16 may be selectively enabled by an appropriate output enable signal, and converts the current at the input to a voltage at the output. In this manner between zero and m of the input signals INPUT 0-7 may be routed to between zero and m of the output buffer amplifiers 16, i.e., OUTPUT 0-3 as shown.
  • a reference input signal REF from the device under test is applied to an uncommitted input buffer amplifier 18 and an uncommitted output buffer amplifier 20 coupled in series.
  • the reference input signal REF may be selected alternatively from among any of the input signals INPUT 0-7 by coupling the extra output from the analog multiplexers 14 to the uncommitted output amplifier 20.
  • a reference source 22 provides many voltage references, such as ECL+, ECL-, TTL and GND.
  • the voltage references and the reference input signal REF are applied as inputs to analog routing switches 24 the outputs of which are input to respective differential input/output amplifiers 26 .
  • a reference select signal is applied to the analog routing switches 24 to determine which reference levels are output.
  • the output signals from the output buffer amplifiers 16 are applied as the other inputs to the differential input/output amplifiers 26 .
  • the multiple routing switches 24 may be replaced with a single routing switch having the output applied in parallel to all of the differential input/output amplifiers 26 . In this way only a single reference level is selected which is applied to all of the differential input/output amplifiers 26 . Differential output signals minimize the effects of local crosstalk and noise sources as they travel to a measurement point.
  • the differential output signals from the differential input/output amplifiers 26 are input to respective selectable termination circuits 28 , such as 50 ohm circuits, to provide appropriate connections for conventional test and measurement instruments at the measurement points.
  • a termination enable signal determines whether the particular differential output signal is terminated or passed straight through to the differential output terminals.
  • the input signals may be referenced to the internally generated voltage levels or to the reference signal REF from the DUT.
  • a standard IEEE 1149.1 boundary scan interface 30 (Fig. 1B), or similar program bus, is provided for programming the analog multi-channel probe system.
  • a test access port (TAP) controller 32 provides appropriate signals from a test clock TCK and a test master signal TMS.
  • Test input data TDI is loaded serially into a control register 34, an instruction register 36 and a bypass register 38.
  • a test data output multiplexer 40 is coupled to have as inputs the outputs from the control register 34, the instruction register 36 and the bypass register 38 to provide test output data TDO back to the boundary scan interface.
  • a decoder logic circuit 42 converts the contents of the control register 34 into respective enable/select signals for the input and output buffer amplifiers 12, 16, the analog multiplexers 14 and routing switches 24 , and the termination circuits 28.
  • the present invention provides a programmable analog multi-channel probe system for embedment into a device under test, such as a printed circuit board, integrated circuit or multi-chip module, that couples any test point of the device under test to an external measurement point where conventional instrumentation may be used to measure the voltage(s) at the selected test point(s).
  • a device under test such as a printed circuit board, integrated circuit or multi-chip module

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)

Claims (8)

  1. System, das einen Prüfling und ein eingebettetes analoges mehrkanaliges Prüfsystem umfasst, wobei das analoge mehrkanalige Prüfsystem Folgendes umfasst:
    n Eingangstrennverstärker (12), wobei n eine positive Ganzzahl ist, jeder Eingangstrennverstärker (12) über einen Eingang, der mit einem Prüfpunkt des Prüflings gekoppelt ist, einen Ausgang sowie einen Steueranschluss verfügt, durch den der Eingangstrennverstärker selektiv aktiviert werden kann, wobei, wenn der Eingangstrennverstärker (12) aktiviert ist, er ein Prüfsignal an dessen Ausgang bereitstellt;
    eine Prüfsignal-Selektoreinrichtung, die Folgendes umfasst: n analoge Multiplexer (14), einen analogen Multiplexer (14) für jeden Eingangstrennverstärker (12), wobei jeder analoge Multiplexer (14) einen Eingang hat, der mit einem separaten Ausgang der Ausgänge des Eingangstrennverstärkers (12) gekoppelt ist, sowie m Ausgänge, wobei m eine positive Ganzzahl ist, und einen Steueranschluss, durch den der Eingang des Multiplexers (14) selektiv mit einem beliebigen seiner m Ausgänge gekoppelt werden kann, wobei die Prüfsignal-Selektoreinrichtung m Selektor-Ausgänge hat und der i-te Ausgang, wobei i = 1 . . . m, jedes Multiplexers mit dem i-ten Selektor-Ausgang gekoppelt ist;
    m Ausgangstrennverstärker (16), wobei jeder Ausgangstrennverstärker (16) einen Eingang, der mit einem separaten Ausgang der m Selektor-Ausgänge gekoppelt ist, und einen Ausgang hat, der mit einem externen Messpunkt und einem Steueranschluss gekoppelt ist, durch die der Ausgangstrennverstärker (16) wahlweise aktiviert werden kann, so dass ein beliebiger Prüfpunkt mit einem beliebigen externen Messpunkt gekoppelt werden kann, gemäß der Festlegung durch Steuerbefehle, die an die Steueranschlüsse des Eingangs- und Ausgangstrennverstärkers (12, 16) und an die analogen Multiplexer (14) und an Umwandeleinrichtungen (22, 24, 26) angelegt werden, um die Ausgangssignale von den Ausgangstrennverstärkern (16) in Differenzausgangssignale umzuwandeln in Bezug auf einen ausgewählten Referenzpegel von einer Vielzahl von Referenzpegeln.
  2. System nach Anspruch 1, das ferner eine Einrichtung (28) umfasst, um selektiv einen vorgegebenen Abschluss für die Differenzausgangssignale bereitzustellen.
  3. System nach Anspruch 1, wobei die Umwandeleinrichtung (22, 24, 26) Folgendes umfasst:
    eine Einrichtung (24) zum Auswählen eines Referenzpegels aus der Vielzahl von Referenzpegeln als Ausgangssignal;
    eine Einrichtung (22) zum Erzeugen der Vielzahl von Referenzpegeln; und
    eine Einrichtung (26) zum Erzeugen der Differenzausgangssignale aus den Ausgangssignalen der Ausgangstrennverstärker als Funktion des ausgewählten Referenzpegels.
  4. System nach Anspruch 3, wobei die Umwandeleinrichtung (22, 24, 26) ferner eine Einrichtung umfasst, um von dem Prüfling ein Referenzsignal abzuleiten, das der Selektoreinrichtung als ein weiteres Eingangssignal zugeführt wird, so dass das Ausgangssignal der Selektoreinrichtung aus den Referenzpegeln und dem Referenzsignal ausgewählt wird.
  5. System nach Anspruch 1, wobei die Umwandeleinrichtung (22, 24, 26) Folgendes umfasst:
    eine Einrichtung zum Ableiten eines Referenzpegels von dem Prüfling; und
    eine Einrichtung (26) zum Erzeugen der Differenzausgangssignale aus den Ausgangssignalen der Ausgangstrennverstärker (16) als Funktion des Referenzpegels.
  6. System nach Anspruch 1, das ferner eine auf jeden Steueranschluss anzuwendende Einrichtung zum Programmieren von entsprechenden Befehlen umfasst, so dass spezifizierte Prüfpunkte mit spezifizierten externen Messpunkten koppelbar sind.
  7. System nach Anspruch 1, wobei die Umwandeleinrichtung eine Vielzahl von Differenzeingangs-/-ausgangsverstärkern (26) umfasst, wobei die Differenzeingangs-/ausgangsverstärker (26) jeweils ein separates Ausgangssignal der Ausgangstrennverstärker (16) als erstes Eingangsignal und ein Referenzsignal als zweites Eingangssignal und ein Paar von Ausgangsanschlüssen aufweisen, um ein Differenzausgangsignal bereitzustellen.
  8. System nach Anspruch 7, wobei die Umwandeleinrichtung Folgendes umfasst:
    eine Einrichtung (24) zur Auswahl eines Referenzpegels aus der Vielzahl von Eingangsreferenzpegeln; und
    eine Einrichtung zur Erzeugung der Differenzausgangsignale aus dem ausgewählten Referenzpegel und den Ausgangssignalen der Ausgangstrennverstärker (16).
EP94307668A 1993-10-22 1994-10-19 Analoges mehrkanaliges Prüfsystem Expired - Lifetime EP0650069B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/139,651 US5418470A (en) 1993-10-22 1993-10-22 Analog multi-channel probe system
US139651 1993-10-22

Publications (3)

Publication Number Publication Date
EP0650069A2 EP0650069A2 (de) 1995-04-26
EP0650069A3 EP0650069A3 (de) 1996-02-28
EP0650069B1 true EP0650069B1 (de) 2002-08-28

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP94307668A Expired - Lifetime EP0650069B1 (de) 1993-10-22 1994-10-19 Analoges mehrkanaliges Prüfsystem

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US (1) US5418470A (de)
EP (1) EP0650069B1 (de)
JP (1) JP2893242B2 (de)
DE (1) DE69431229T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2278689B (en) * 1993-06-02 1997-03-19 Ford Motor Co Method and apparatus for testing integrated circuits
US5610530A (en) * 1994-10-26 1997-03-11 Texas Instruments Incorporated Analog interconnect testing
US5629617A (en) * 1995-01-06 1997-05-13 Hewlett-Packard Company Multiplexing electronic test probe
US5583447A (en) * 1995-02-03 1996-12-10 Hewlett-Packard Company Voltage probe with reverse impedance matching
IL120927A (en) * 1995-06-07 2000-06-01 Samsung Electronics Co Ltd Method and apparatus for testing a megacell in an ASIC using JTAG
US5905383A (en) * 1995-08-29 1999-05-18 Tektronix, Inc. Multi-chip module development substrate
US6108637A (en) * 1996-09-03 2000-08-22 Nielsen Media Research, Inc. Content display monitor
US5818252A (en) * 1996-09-19 1998-10-06 Vivid Semiconductor, Inc. Reduced output test configuration for tape automated bonding
US5949284A (en) * 1997-11-10 1999-09-07 Tektronix, Inc. CMOS buffer amplifier
US6687865B1 (en) * 1998-03-25 2004-02-03 On-Chip Technologies, Inc. On-chip service processor for test and debug of integrated circuits
EP1398640B1 (de) * 1998-06-16 2009-09-09 Infineon Technologies AG Einrichtung zur Vermessung und Analyse von elektrischen Signalen eines integrierten Schaltungsbausteins
WO2002014883A2 (en) * 2000-08-10 2002-02-21 Xilinx, Inc. Analog signal testing circuit and -method
JP2002286813A (ja) * 2001-03-28 2002-10-03 Agilent Technologies Japan Ltd トラック・ホールド回路を内蔵した集積回路及び試験方法
US6990618B1 (en) 2002-12-03 2006-01-24 Cypress Semiconductor Corporation Boundary scan register for differential chip core
DE10306620B4 (de) * 2003-02-18 2007-04-19 Infineon Technologies Ag Integrierte Testschaltung in einer integrierten Schaltung
CN1795393B (zh) * 2003-05-28 2010-06-02 Nxp股份有限公司 信号完整性自测结构
DE10340828A1 (de) * 2003-09-04 2005-04-28 Infineon Technologies Ag Testanordnung und Verfahren zur Auswahl eines Testmodus-Ausgabekanals
US7138814B2 (en) * 2003-11-21 2006-11-21 Agere Systems Inc. Integrated circuit with controllable test access to internal analog signal pads of an area array
CN100377102C (zh) * 2004-02-21 2008-03-26 鸿富锦精密工业（深圳）有限公司 主机板功能测试板
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
US7408406B2 (en) * 2006-05-24 2008-08-05 Tektronix, Inc. Mode selection amplifier circuit usable in a signal acquisition probe
US7443180B2 (en) * 2006-12-06 2008-10-28 International Business Machines Corporation On-chip probing apparatus
US20120197570A1 (en) * 2011-01-27 2012-08-02 Mehran Ramezani Measurement of Parameters Within an Integrated Circuit Chip Using a Nano-Probe
DE112022002912T5 (de) * 2021-06-03 2024-03-14 Tektronix, Inc. Remote-köpfe mit mehreren eingängen für sequenzielles testen

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961254A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
EP0042878B1 (de) * 1980-06-25 1986-02-19 Kommanditgesellschaft Ritz Messwandler GmbH & Co. Überwachungsvorrichtung für eine Messverstärkerstrecke
US4357703A (en) * 1980-10-09 1982-11-02 Control Data Corporation Test system for LSI circuits resident on LSI chips
DE3526485A1 (de) * 1985-07-24 1987-02-05 Heinz Krug Schaltungsanordnung zum pruefen integrierter schaltungseinheiten
US4931722A (en) * 1985-11-07 1990-06-05 Control Data Corporation Flexible imbedded test system for VLSI circuits
GB2214319B (en) * 1987-01-16 1991-09-25 Teradyne Inc Automatic test equipment
US5053700A (en) * 1989-02-14 1991-10-01 Amber Engineering, Inc. Method for wafer scale testing of redundant integrated circuit dies
FR2648916B1 (fr) * 1989-06-27 1991-09-06 Cit Alcatel Agencement de test de cartes a circuit imprime et son application au test de cartes a circuit imprime formant un equipement de multiplexage-demultiplexage de signaux numeriques
JP2676169B2 (ja) * 1989-12-27 1997-11-12 三菱電機株式会社 スキャンパス回路
DE69133311T2 (de) * 1990-10-15 2004-06-24 Aptix Corp., San Jose Verbindungssubstrat mit integrierter Schaltung zur programmierbaren Verbindung und Probenuntersuchung
US5254940A (en) * 1990-12-13 1993-10-19 Lsi Logic Corporation Testable embedded microprocessor and method of testing same
JPH04225180A (ja) * 1990-12-27 1992-08-14 Toshiba Corp 半導体測定装置
JP2744723B2 (ja) * 1991-08-29 1998-04-28 株式会社テック オーブントースター
US5315241A (en) * 1991-09-18 1994-05-24 Sgs-Thomson Microelectronics, Inc. Method for testing integrated circuits

Also Published As

Publication number Publication date
US5418470A (en) 1995-05-23
JPH07191100A (ja) 1995-07-28
DE69431229T2 (de) 2003-03-13
EP0650069A3 (de) 1996-02-28
EP0650069A2 (de) 1995-04-26
DE69431229D1 (de) 2002-10-02
JP2893242B2 (ja) 1999-05-17

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