EP0622854A1 - Halbleiterschalter mit IGBT und Thyristor - Google Patents

Halbleiterschalter mit IGBT und Thyristor Download PDF

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Publication number
EP0622854A1
EP0622854A1 EP94302926A EP94302926A EP0622854A1 EP 0622854 A1 EP0622854 A1 EP 0622854A1 EP 94302926 A EP94302926 A EP 94302926A EP 94302926 A EP94302926 A EP 94302926A EP 0622854 A1 EP0622854 A1 EP 0622854A1
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EP
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Prior art keywords
semiconductor layer
semiconductor
type layer
impurity concentration
layer
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EP94302926A
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French (fr)
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EP0622854B1 (de
Inventor
Hideo Kobayashi
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Hitachi Ltd
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Hitachi Ltd
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Priority claimed from JP5100712A external-priority patent/JP2797890B2/ja
Priority claimed from JP30411993A external-priority patent/JPH07161967A/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H01L29/745—Gate-turn-off devices with turn-off by field effect
    • H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect

Definitions

  • the semiconductor above can be regarded as a complex of an MISFET and a pnp transistor.
  • Fig. 27 shows an equivalent circuit of the semiconductor device of Fig. 26. Next, the operation principle will be described by reference to Figs. 26 and 27.
  • Fig. 3 shows simulation results of lines of current flow on the side of the cathode electrode 2 in the stationary on state of the complex semiconductor device of Fig. 1. Since the thyristor region is added to the IGBT in the best form, when compared with lines of current flows of the conventional IGBT shown in Fig. 28, electrons supplied from the cathode electrode 2 via the MIS channel uniformly flow in a state where the electrons are fully extended in the thyristor region. Consequently, the on-state voltage can be sufficiently lowered.
  • the electrons flown from the n1+-type layer 16 via the n-channel MISFET (M1) and the n-channel MISFET (M2) into the n2+-type layer 17 are injected to the n-type layer 13 thanks to the operation of the npn transistor (Q2).
  • the hole injection from the p1+-type layer is further increased and hence the thyristor including the pnp transistor (Q1) and the npn transistor (Q2) ignites and the complex semiconductor device is set to the on state.
  • the shape can be quite simple in the plan view.
  • the gate length of the portion 41 having the longer gate length of the insulated gate electrode 4 is set to be larger than the sum of the diffusion depths of the portion 151 of the p-type layer 15 and the p ⁇ -type layer 18, and the gate length of the portion 42 having the shorter gate length of the insulated gate electrode 4 is set to be equal to or less than the sum of the diffusion depths of the portion 151 of the p-type layer 15 and the p ⁇ -type layer 18 (preferably, equal to or less than the diffusion depth of the portion 151 of the p-type layer 15).
  • the complex semiconductor device can be easily produced without using any complicated shape in the plan view and any special technology.
  • Figs. 8 to 10 are schematic plan views on the insulted gate electrode side showing a variation of the complex semiconductor device shown in Figs. 7A and 7B.
  • the portion 41 having the longer gate length and the portion 42 having the shorter gate length of the insulated gate electrode 4 are formed alternately in a direction such that the portions 41 and 42 are adjacent to each other between the adjacent ones of a plurality of insulated gate electrodes arranged in parallel in a direction vertical to the direction.
  • Fig. 9 shows a case in which the portions 41 are adjacent to each other and the portions 42 are adjacent each other.
  • Fig. 10 shows a case in which the portion 41 are connected to each other in Fig. 9. In the configuration of Fig.
  • the plural notched portions 9a disposed in the p ⁇ -type layer 9 are of a band shape and extend in a direction substantially vertical to a pair of opposing edges of the substrate 1, namely, a direction substantially vertical to the longitudinal direction of the insulated gate electrodes (G) 12. Furthermore, the notches 9a are arranged with an equal interval therebetween along the longitudinal direction of the electrodes (G) 12. In this case, as for the portion where the p ⁇ -type layer 9 is arranged, the p ⁇ -type layer 9 intervenes between the n ⁇ -type layer 2 and n2+-type layer 8.
  • the n ⁇ -type layer 2 and n2+-type layer 8 are directly coupled with each other via the notched portions 9a.
  • two electrodes (G) 12 are electrically connected to each other at a position not shown in the diagram.
  • TR1 indicates a first pnp transistor including the p1+-type layer 4, the n ⁇ -type layer 2, and the p ⁇ -type layer 9
  • TR2 denotes a first npn transistor including the n ⁇ -type layer 2, the p ⁇ -type layer 9, and the n2+-type layer 8
  • TR3 indicates a second pnp transistor including the p1+-type layer 4, the n ⁇ -type layer 2, and the p2+-type layer 6
  • TR4 denotes a second npn transistor including the n ⁇ -type layer 2, the p2+-type layer 6, and the n1+-type layer 7,
  • MTR1 denotes an n-channel MISFET including the insulated gate electrode (G) 10, the n1+-type layer 7, the p-type layer 5, and the n2+-type layer 8,
  • r0 designates a lateral resistance of the p ⁇ -type layer 9, r1 stands for a lateral resistance of the p2+-
  • first pnp transistor (TR1) and the first npn transistor (TR2) configure a thyristor
  • the n-channel MISFET (MTR1), the second pnp transistor (TR3), and the second npn transistor (TR4) form an IGBT.
  • the complex semiconductor device can be regarded as a complex semiconductor device in which, as shown in the equivalent circuit of Fig. 15, the IGBT and the thyristor are commonly connected to each other by the MISFET (MTR1) on the respective cathode sides.
  • MISFET MISFET
  • the lateral resistance r1 of the p2+-type layer 6 is sufficiently low due to the high impurity concentration of the p2+-type layer 6 and hence the parasitic thyristor including the n1+-type layer 7, the p2+-type layer 6, the n ⁇ -type layer 2, and the p1+- type layer 4 cannot be easily turned on.
  • the n-type layer 3 having a relatively high impurity concentration suppresses the hole injection efficiency in the first and second npn transistors (TR1) and (TR2).
  • TR1 and (TR2) npn transistors
  • the impurity concentration and the thickness of the n-type layer 3 are to be appropriately set according to desired characteristics of the complex semiconductor device.
  • the means of suppressing the hole injection efficiency is not limited to the means setting the n-type layer 3, namely, there may be employed another means having the similar function.
  • the n-type layer 3 may be configured to be partially connected via a short circuit to the anode electrode (A) 13 or there may be disposed any known means in the junction portion between the p1+-type layer 4 and the n ⁇ -type layer 2 to lower the lifetime of minority carriers.
  • the potential applied to the insulated gate electrode (G) 10 is set to a value equal to or less than the potential applied to the cathode electrode (K) 14.
  • the inversion layer (channel) formed in the surface portion of the p-type layer 5 below the insulated gate electrode (G) 10 is extinguished and hence the injection of electrons flowing from the n1+-type layer 7 into n+-type layer 8 is interrupted.
  • the injection of electrons flowing from the n2+-type layer 8 into the n ⁇ -type layer 2 is interrupted; consequently, the injection of holes from the p1+-type layer 4 into the n ⁇ -type layer 2 is stopped and hence the complex semiconductor device is set to the off state.
  • Fig. 16A is a diagram for explaining simulation results of lines of current flows in the cross section of the B-B line portion of the complex semiconductor device shown in Fig. 13 on the cathode side of the device in the on state.
  • Fig. 16A the same constituent elements as those of Figs. 12A and 12B are assigned with the same reference numerals.
  • Fig. 16A As shown in Fig. 16A, according to this device, as compared with the lines of current flows on the cathode side of the known IGBT in the on state (Fig. 16B), electrons supplied from the cathode electrode (K) 14 via the channel of the MISFET (MTR1) are fully extended to uniformly flow in the thyristor region. Consequently, the inter-terminal voltage in the on-state operation (resistance in the on-state operation) can be sufficiently reduced as compared with the known IGBT.
  • the complex semiconductor device can be easily turned on and off by applying and removing a potential of a predetermined polarity to and from the insulated gate electrode (G) 10. Furthermore, thanks to adoption of the saturation characteristic of the n-channel MISFET (MTR1), there is obtained an aspect of a current limiting action even in the thyristor operation.
  • the structure shown in Figs. 12A and 12B is used as a cell such that several hundred to several tens of thousand of cells are integrated in an identical semiconductor substrate to be connected to each other for operation in a parallel fashion.
  • the parallel operation when each cell has the current limiting action, the current is not concentrated onto a particular cell or onto particular several cells so as to be uniformly loaded onto the respective cells. Consequently, it is advantageously possible to prevent destruction of the complex semiconductor device due to the current concentration.
  • Figs. 17 to 19 are schematic plan views showing second, third, and fourth examples in which the constitution and the arrangement positions of the notched portions of the p ⁇ -type layer 9 are respectively altered in the complex semiconductor device shown in Figs. 12A and 12B.
  • Figs. 20A to 20C are lateral cross-sectional views of A-A, B-B, C-C, D-D, and E-E line portions of Figs. 17 to 19.
  • numeral 9b indicates the notched portion of a second shape
  • numeral 9c denotes the notched portion of a third shape
  • numeral 9d indicates the notched portion of a fourth shape.
  • the same constituent elements as those shown in Figs. 12A and 12B are assigned with the same reference numerals.
  • the contacting portions of the notched portions 9b of the second shape with the n2+-type layer 8 and the n ⁇ -type layer 2 are limited to the portions adjacent to the insulated gate electrode (G). Consequently, in the case employing the p ⁇ -type layer 9 having such notched portions 9b, as compared with the case using the p ⁇ -type layer 9 having the notched portions 9a shown in Figs. 12A and 12B, it is possible to increase the area where the p ⁇ -type layer 9 is arranged.
  • the contact portions of the notched portions 9d of the fourth shape with the n2+-type layer 8 and the n ⁇ -type layer 2 are separately disposed to be apart from each other in a portion apart from the insulated gate electrode (G) 10.
  • the shape of the notched portions disposed in the p ⁇ -type layer 9 is not limited to the notched portions 9a shown in Figs. 12A and 12B and the notched portions 9b, 9c and 9d of the second, third, and fourth shapes. Namely, there may be disposed notched portion having another shape.
  • the inter-terminal voltage in the on-state operation (resistance in the on-state operation) of the complex semiconductor device can be minimized, which is favorable because fears of decrease in the breakdown voltage is removed.
  • Fig. 21 is a schematic cross-sectional view showing the constitution of further another embodiment of the complex semiconductor device according to the present invention.
  • numeral 15 indicates a third n-type layer of a high impurity concentration (n3+-type layer, sixth semiconductor layer) disposed on an n ⁇ -type layer 2 of the principal surface 1b and arranged to be apart from the n2+-type layer 8
  • numeral 16 designates a p-type impurity layer (p-type layer, seventh semiconductor layer) arranged between the n2+-type layer 8 and the n3+-type layer 15 and between the n ⁇ -type layer 2 and the n3+-type layer
  • numeral 17 denotes a second p-type layer of a low impurity concentration (p2 ⁇ -type layer, eighth semiconductor layer) disposed on the surface of the p2+-type layer 6 exposed between the n1+-type layer 7 and the n2+-type layer 8
  • a numeral 18 stands for a fourth n-type impurity layer (n4 layer, ninth semiconductor layer) disposed on the surface of the p-type layer 16 exposed between the n2+
  • MTR1 designates a first MISFET including the first insulated gate electrode (G1) 19, the n1+-type layer 7, the p2+-type layer 6 including the p2 ⁇ -type layer 17, and the n2+-type layer 8 and MTR2 denotes a second MISFET including the second insulated gate electrode (G2) 20, the n2+-type layer 8, the p-type layer 16 including the n4 layer 18, and the n3+-type layer 15.
  • G2 the same constituent elements as those shown in Figs. 12A and 12B are assigned with the same reference numerals.
  • the difference between the embodiment of Fig. 21 and that of Figs. 12A and 12B resides only in that the embodiment of Figs. 12A and 12B includes the p ⁇ -type layer 9 having the notched portions 9a and the like between the n ⁇ -type layer 2 and the n2+-type layer 8, whereas the p ⁇ -type layer 9 of this kind is missing in the embodiment of Fig. 21.
  • the embodiment of Figs. 12A and 12B does not include the second MISFET (MTR2), whereas the embodiment of Fig. 21 includes the second MISFET (MTR2).
  • the embodiment of Fig. 21 is substantially equal in the configuration to that of Figs. 12A and 12B. In consequence, description will not be further given of the configuration of the embodiment of Fig. 21.
  • Fig. 22 is a circuit diagram showing an electrically equivalent circuit of the complex semiconductor device shown in Fig. 21.
  • TR1 indicates a first pnp transistor including the p1+-type layer 4, the n ⁇ -type layer 2, and the p-type layer 16;
  • TR2 denotes a first npn transistor including the n ⁇ -type layer 2, the p-type layer 16, and the n3+-type layer 15;
  • TR3 designates a second pnp transistor including the p1+-type layer 4, the n ⁇ -type layer 2, and the p2+-type layer 6;
  • TR4 stands for a second npn transistor including the n ⁇ -type layer 2, the p2+-type layer 6, and the n1+-type layer 7;
  • MTR1 indicates a first MISFET including the first insulated gate electrode (G1) 19, the n1+-type layer 7, the p2+-type layer 6 having the p2 ⁇ -type layer 17, and the n2+-type layer 8;
  • MTR2 indicates a second MISFET including the second insulated gate electrode (G2) 20, the n
  • the IGBT and the thyristor are commonly coupled with each other by the first MISFET (MTR1) on their cathode sides, thereby configuring a complex semiconductor device.
  • MSR1 first MISFET
  • Figs. 23A and 23B are characteristic diagrams showing a state of the complex semiconductor device in the embodiment of Fig. 21.
  • Fig. 12A shows flows of carriers in the device, whereas Fig. 12B shows the impurity concentration distributions in the A-A and B-B line cross-sectional portions.
  • the n-channel MISFET (MTR1) is of the depletion or normally-on type due to the n-type layer 18 disposed on the surface of the p-type layer 16.
  • the first and second insulated gate electrodes (G1, G2) 19 and 20 of these MISFETs (MTR1, MTR2) are electrically connected to each other at a position not shown in the diagram.
  • a negative potential and a positive potential are applied respectively to the cathode electrode (K) 14 and the anode electrode (A) 13 such that each of the first and second insulated gate electrodes (G1, G2) 19 and 20 is applied with a positive potential higher than that of the cathode electrode (K).
  • an inversion layer (channel) is formed in the p2 ⁇ -type layer 17 below the first insulated gate electrode (G1) 19 and the n1+-type layer 7 is connected via the channel to the n2+-type layer 8 so as to set the first MISFET (MTR1) to the on state.
  • the first npn transistor (TR2) is set to the on state. Consequently, the electrons flowing from the cathode electrode (K) 14 via the first MISFET (MTR1) and the second MISFET (MTR2), which has been similarly set to the on state, into the n3+-type layer 15 are injected from the n3+-type layer 15 directly into the n ⁇ -type layer 2. In consequence, the thyristor including the first pnp transistor (TR1) and the second npn transistor (TR2) ignites and the complex semiconductor device is set to the on state.
  • the lateral resistance r1 of the p2+-type layer 6 is sufficiently low due to the high impurity concentration of the p2+-type layer 6, and the parasitic thyristor including the n1+-type layer 7, the p2+-type layer 6, the n ⁇ -type layer 2, and the p1+-type layer 4 cannot be easily turned on.
  • the potential of the first and second insulated gate electrodes (G1, G2) 19 and 20 are set to a value equal to or less than that of the cathode electrode (K).
  • the inversion layer (channel) is distinguished from the p2 ⁇ -type layer 17 below the electrode (G1) 19 and hence the electrode injection from the n1+-type layer 7 into the n2+-type layer 8 is interrupted so as to turn the first MISFET (MTR1) off.
  • the second n-channel MISFET (MTR2) cannot be easily turned off because it is of the depletion type, there does not arise any problem since the complex semiconductor device is set to the off state when the first n-channel MISFET (MTR1) is turned off.
  • the MIS current necessary to ignite the thyristor is required to pass only one channel resistance of the the first n-channel MISFET (MTR1).
  • the thyristor current is required to pass two channels of the first n-channel MISFET (MTR1) and the second n-channel MISFET (MTR2), since the second n-channel MISFET (MTR2) is of the depletion type, the channel resistance is quite small.
  • the thyristor current is substantially identical to a current which flows only through the channel resistance of the first n-channel MISFET (MTR1) and hence the inter-terminal voltage in the on-state operation (resistance in the on-state operation) can be sufficiently decreased. This enables a high breakdown voltage and a large current to be easily obtained for the complex semiconductor device.
  • the complex semiconductor device in the embodiment of Fig. 21 can be easily turned on and off, like the embodiment of Fig. 12, by applying and removing a potential of a predetermined polarity to and from the first and second insulated gate electrodes (G1, G2) 19 and 20.
  • the saturation characteristic of the first n-channel MISFET (MTR1) since there is employed the saturation characteristic of the first n-channel MISFET (MTR1), a current limiting action is provided even in the thyristor operation. In consequence, also in a case where the structure shown in Fig.
  • each cell 21 is adopted as a cell so as to integrate several hundred to several tens of thousand cells in an identical semiconductor substrate and to connect the cells to each other for a parallel operation, since each cell has the current limiting action, the current is not concentrated onto a particular one cell or several particular cells but is uniformly loaded onto the respective cells. Consequently, it is advantageously possible to prevent destruction of the complex semiconductor device due to the current concentration.
  • the embodiment of Fig. 21 is advantageous in that the ignition characteristic and the reproducibility of the on-state voltage of the thyristor are superior and the device can be easily produced. That is, in the embodiment of Figs.
  • the size of each of the notched portions 9a to 9d (the portions of the direct connection) or the distance between each of the notched portions 9a to 9d (the portions of the direct connection) and the insulated gate electrode (G) 10 will be apart from the respective designed values.
  • the contact portions between the n ⁇ -type layer 2 and the n2+-type layer 8 can be manufactured according to the gate self-alignment technology. Consequently, the portions are limited to be between the first and second insulated gate electrodes (G1, G2) 19 and 20 regardless of the photomask aligning precision. In consequence, the contact areas and positions between the n ⁇ -type layer 2 and the n2+-type layer 8 cannot alter for each production of the complex semiconductor device. As a result, the complex semiconductor devices can be attained with the fixed characteristics and quality.
  • the threshold voltage of the first n-channel MISFET (MTR1) is controlled by the impurity concentration of the p2 ⁇ -type layer 17 disposed on the surface of the p2+-type layer 6 and independent of the impurity concentration of the p2+-type layer 6. Consequently, the impurity concentration of the p2+-type layer 6 can be set to a sufficiently high value so as to enclose the n1+-type layer 7.
  • the lateral resistance r1 of the p2+-type layer 7 below the n1+-type layer 7 can be set to be smaller than that of the embodiment of Figs.
  • the parasitic thyristor including the n1+-type layer 7, the p2+-type layer 6, the n ⁇ -type layer 2, and the p1+-type layer 4 cannot be easily turned on. This leads to an aspect that a much larger current can be obtained for the device.
  • the p2 ⁇ -type layer 17 disposed on the surface of the p2+-type layer 6 and the n4 layer 18 disposed on the surface of the p-type layer 16 can be simultaneously and easily formed by disposing the p2+-type layer 6 and the p-type layer 16 and achieving thereafter an ion injection of compensating n-type impurities into the surfaces thereof. This unnecessitates any special manufacturing technologies.
  • means for conducting an ion injection of compensating n-type impurities into the respective surfaces of the p2+-type layer 6 and the p-type layer 16 is similarly applicable to the embodiment of Figs. 12A and 12B. Namely, this is possible by providing a high impurity concentration for the p-type layer 5 shown in Fig. 12A or by replacing the p-type layer 5 with the p2+-type layer 6 and by conducting an ion injection of compensating n-type impurities into these surfaces, thereby disposing a p-type layer having a lower impurity concentration.
  • FIGs. 24A and 24B are configuration diagrams showing constitution examples of a complex semiconductor device analogous to the embodiment of Fig. 21.
  • Fig. 24A is a schematic cross-sectional perspective view and Fig. 24B is a schematic plan view.
  • numeral 21 indicates an insulation layer, and the same constituent elements as those of Fig. 21 are assigned with the same reference numerals.
  • the cathode electrode (K) and the insulation layer are partially removed.
  • the difference between the construction example and the embodiment of Fig. 21 is as follows.
  • the construction example in association with the configuration of arrangement of the cathode electrode (K) 14, there is used an ohmic contact to each of the n1+-type layer 7 and the p2+-type layer 6 and there is disposed an electric insulation by the insulation layer 21 from the first and second insulation gate electrodes (G1, G2) 19 and 20, the n2+-type layer 8, and the n3+-type layer 15 such that the insulation layer 21 covers the overall surface of the principal surface 1b.
  • the embodiment of Fig. in association with the configuration of arrangement of the cathode electrode (K) 14, there is used an ohmic contact to each of the n1+-type layer 7 and the p2+-type layer 6 and there is disposed an electric insulation by the insulation layer 21 from the first and second insulation gate electrodes (G1, G2) 19 and 20, the n2+-type layer 8, and the n3+-type layer 15 such that the insulation layer 21 covers the overall surface
  • the fine machining of the cathode electrode (K) 14 is unnecessitated. Moreover, the electric resistance between the cathode electrode (K) 14 and the n1+-type layer 7 and the p2+-type layer 6 and hence the heat dissipation efficiency from the semiconductor substrate 1 can be improved.
  • the first and second insulation gate electrodes (G1, G2) 19 and 20 are connected to each other at a position not shown in the diagram.
  • Fig. 25 is an electric circuit diagram showing an example of a motor driving inverter system including the complex semiconductor device according to the present invention.
  • T1 and T2 indicate a pair of direct-current (dc) terminals connected to a dc power source
  • T3 to T5 denote alternating-current (ac) terminals disposed as many as there are phases of an alternating current (ac) connected to a three-phase induction motor
  • SW11, SW12, SW21, SW22, SW31, and SW32 designate complex semiconductor devices of the present invention
  • D11, D12, D21, D22, D31, and D32 stand for flywheel diodes
  • SB11, SB12, SB21, SB22, SB31, and SB32 represent snubber circuits including a series connection of a parallel circuit of a diode and a resistor and a capacitor.
  • the complex semiconductor devices of the present invention SW11, SW12, SW21, SW22, SW31, and SW32 form series connection circuits for three phases in which each of the circuits includes a series connection of two complex semiconductor devices selected therefrom. These series circuits are connected between the pair of dc terminals T1 and T2. In this case, the series connection points of the two complex semiconductor devices SW11 and SW12, SW21 and SW22, and SW31 and SW32 are respectively connected to the ac terminals T3, T4, and T5.
  • the flywheel diodes D11, D12, D21, D22, D31, and D32 are respectively linked in an inverse parallel connection with complex semiconductor devices SW11, SW12, SW21, SW22, SW31, and SW32; moreover, the snubber circuits are also respectively linked in an inverse parallel connection with the complex semiconductor devices SW11, SW12, SW21, SW22, SW31, and SW32, thereby configuring as a whole a motor driving inverter system.
  • each of the devices SW11, SW12, SW21, SW22, SW31, and SW32 of the present invention can be easily turned on and off by applying and removing a potential to the insulated gate electrode (G) thereof.
  • G insulated gate electrode
  • each of the devices SW11, SW12, SW21, SW22, SW31, and SW32 uses the saturation characteristic of the MISFET integrated therein, there can be developed a current limiting action even in the thyristor operation. Consequently, a large current can be controlled at a high speed by a low on-state voltage without destroying the complex semiconductor devices.
  • the inverter system above can be implemented as a small-sized and lightweight apparatus with a decreased loss, a low noise, and the like thanks to easy achievement of a high-frequency operation and easy control thereof.
  • the IGBT there can be implemented a large-capacity and a low-loss inverter system developing a decreased on-state voltage.
  • the thyristor region is added to the IGBT in the best form, the electrons supplied from the cathode electrode via the MIS channel are sufficiently extended to flow in the thyristor region and hence the on-state voltage can be fully lowered without deteriorating the ignition characteristic.
  • the p-type base layer of the IGBT and the p-type base layer of the thyristor region are disposed to be separated from each other and the n-type emitter layer of the thyristor region is partially brought into contact with the n-type base layer so that the MIS current (electrons) and the thyristor current (electrons) flow only through one (series) MISFET, thereby achieving an easy ignition and attaining a low on-state voltage (a large current).
  • the semiconductor device is operated with a high breakdown voltage and a large current.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP94302926A 1993-04-27 1994-04-25 Halbleiterschalter mit IGBT und Thyristor Expired - Lifetime EP0622854B1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP5100712A JP2797890B2 (ja) 1993-04-27 1993-04-27 複合半導体装置
JP100712/93 1993-04-27
JP10071293 1993-04-27
JP304119/93 1993-12-03
JP30411993 1993-12-03
JP30411993A JPH07161967A (ja) 1993-12-03 1993-12-03 複合半導体装置

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EP0622854A1 true EP0622854A1 (de) 1994-11-02
EP0622854B1 EP0622854B1 (de) 1999-11-24

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EP94302926A Expired - Lifetime EP0622854B1 (de) 1993-04-27 1994-04-25 Halbleiterschalter mit IGBT und Thyristor

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EP (1) EP0622854B1 (de)
DE (1) DE69421749T2 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0736909A2 (de) * 1995-04-05 1996-10-09 Fuji Electric Co. Ltd. Thyristor mit isoliertem Gate
US5874751A (en) * 1995-04-05 1999-02-23 Fuji Electric Co., Ltd. Insulated gate thyristor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10125896A (ja) * 1996-10-16 1998-05-15 Fuji Electric Co Ltd 絶縁ゲート型サイリスタ

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57206279A (en) * 1981-06-12 1982-12-17 Hitachi Ltd Gto inverter device
GB2204995A (en) * 1987-05-19 1988-11-23 Gen Electric Monolithically integrated semiconductor circuit having bidirectional conducting capability and method of fabrication
US4847671A (en) * 1987-05-19 1989-07-11 General Electric Company Monolithically integrated insulated gate semiconductor device
EP0340445A1 (de) * 1988-04-22 1989-11-08 Asea Brown Boveri Ag Abschaltbares Leistungshalbleiterbauelement
US4958211A (en) * 1988-09-01 1990-09-18 General Electric Company MCT providing turn-off control of arbitrarily large currents
DE4025122A1 (de) * 1989-10-24 1991-04-25 Asea Brown Boveri Abschaltbares leistungshalbleiter-bauelement in form eines mos-gesteuerten thyristors mct
JPH0529607A (ja) * 1991-07-23 1993-02-05 Fuji Electric Co Ltd Ｍｉｓゲート制御型サイリスタ半導体装置
GB2267996A (en) * 1992-06-01 1993-12-22 Fuji Electric Co Ltd Dual gate mos thyristor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57206279A (en) * 1981-06-12 1982-12-17 Hitachi Ltd Gto inverter device
GB2204995A (en) * 1987-05-19 1988-11-23 Gen Electric Monolithically integrated semiconductor circuit having bidirectional conducting capability and method of fabrication
US4847671A (en) * 1987-05-19 1989-07-11 General Electric Company Monolithically integrated insulated gate semiconductor device
EP0340445A1 (de) * 1988-04-22 1989-11-08 Asea Brown Boveri Ag Abschaltbares Leistungshalbleiterbauelement
US4958211A (en) * 1988-09-01 1990-09-18 General Electric Company MCT providing turn-off control of arbitrarily large currents
DE4025122A1 (de) * 1989-10-24 1991-04-25 Asea Brown Boveri Abschaltbares leistungshalbleiter-bauelement in form eines mos-gesteuerten thyristors mct
JPH0529607A (ja) * 1991-07-23 1993-02-05 Fuji Electric Co Ltd Ｍｉｓゲート制御型サイリスタ半導体装置
GB2267996A (en) * 1992-06-01 1993-12-22 Fuji Electric Co Ltd Dual gate mos thyristor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 17, no. 313 (E - 1381) 15 June 1993 (1993-06-15) *
PATENT ABSTRACTS OF JAPAN vol. 7, no. 58 (E - 163) 10 March 1983 (1983-03-10) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0736909A2 (de) * 1995-04-05 1996-10-09 Fuji Electric Co. Ltd. Thyristor mit isoliertem Gate
EP0736909A3 (de) * 1995-04-05 1997-10-08 Fuji Electric Co Ltd Thyristor mit isoliertem Gate
US5874751A (en) * 1995-04-05 1999-02-23 Fuji Electric Co., Ltd. Insulated gate thyristor

Also Published As

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DE69421749D1 (de) 1999-12-30
US5621226A (en) 1997-04-15
DE69421749T2 (de) 2000-06-08
EP0622854B1 (de) 1999-11-24

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