EP0602588A2 - Dispositif pour le décodage d'images animées - Google Patents

Dispositif pour le décodage d'images animées Download PDF

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Publication number
EP0602588A2
EP0602588A2 EP19930120123 EP93120123A EP0602588A2 EP 0602588 A2 EP0602588 A2 EP 0602588A2 EP 19930120123 EP19930120123 EP 19930120123 EP 93120123 A EP93120123 A EP 93120123A EP 0602588 A2 EP0602588 A2 EP 0602588A2
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Prior art keywords
address
data
picture
supplied
memory
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EP19930120123
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German (de)
English (en)
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EP0602588A3 (fr
Inventor
Hiroshi C/O Sony Corporation Sumihiro
Hideki C/O Sony Corporation Koyanagi
Seiichi C/O Sony Corporation Emoto
Tohru C/O Sony Corporation Wada
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]

Definitions

  • This invention relates to a moving picture decoding device for reading picture data from a picture memory responsive to a motion vector for decoding the moving picture.
  • MC-DCT motion compensated inter-frame prediction and discrete cosine transform
  • Fig. 1 shows a circuit for an encoding device conforming to the above-mentioned MC-DCT hybrid system.
  • moving picture signals such as television signals
  • These input signals are supplied to a motion detection circuit 113 and a subtractive node 114 via a picture memory 112 employed as a frame memory.
  • An output of the subtractive node 114 is transmitted to a DCT circuit 115 for discrete cosine transformation and thence supplied to a quantizer 116 for quantization before being supplied to a series circuit consisting of a inverse quantization unit 117 and an inverse DCT (IDCT) circuit 118 as a local decoder.
  • IDCT inverse DCT
  • An output of the IDCT circuit 118 is supplied via an additive node 119 to a picture memory 120 employed as a frame memory.
  • An output read from the picture memory 120 is transmitted to the motion detection circuit 113 and to a motion compensation circuit 121.
  • the motion detection information such as the motion vector from the motion detection circuit 113 is transmitted to the motion compensation circuit 121 and to a variable length coding circuit 123.
  • An output of the motion compensation circuit 121 is supplied to the subtractive node 114 and to the additive node 119.
  • the input signals are stored temporarily in the picture memory 112 and subsequently read out and processed on the basis of a block of a pre-set size.
  • the motion detection circuit 113 compares the values of pixels of a signal block from the picture memory 112 to the values of pixels of locally decoded signals from the picture memory 120 for detecting the motion vector.
  • the motion compensation circuit 121 outputs a reference block to the subtractive node 114 based on this motion vector.
  • the subtractive node 114 outputs a difference between the input signal block and the reference block.
  • the difference output is discrete cosine transformed by the DCT circuit 115 and quantized by the quantizer 116 before being supplied to the variable length coding unit 123 such as an entropy coding unit for variable length coding.
  • the motion vector from the motion detection circuit 113 is also supplied to the variable length coding unit 123.
  • variable length coding unit 123 An output of the variable length coding unit 123 is supplied to a transmitting buffer memory 125 where the coded data to be transmitted is stored transiently. These coded data are supplied to the quantizer 116 and to the variable length coding unit 123. In this manner, the operation of quantization and variable length coding is carried out by the quantizer 116 and the variable length coding unit 123 so that the amount of transmitted data per unit time will be constant.
  • the coded data which is caused to be transmitted in a constant quantity per unit time, is transmitted over a communication network via an output terminal 126 or recorded or reproduced on or from a recording medium.
  • the frame memory is made up of a number of memory elements, such as DRAMs, and is adapted for reading out data from the memory elements by parallel reading with four bytes, as an example, as a word, at a rate of one byte from each memory element. Consequently, in decoding the signals coded in accordance with the above-described MC-DCT hybrid coding, by way of picture decoding, it is necessary to have a high-speed access to the frame memory.
  • CCK denotes clock pulses.
  • /CS denotes a logical signal to be supplied to an L-active chip select terminal and its timing.
  • /RAS denotes a logical signal to be supplied to a random access terminal for a row which is L-active and its timing.
  • /CAS denotes a logical signal to be supplied to a random access terminal for a column which is L-active.
  • /WE denotes a logical signal to be supplied to a write enable terminal which is L-active and its timing.
  • BS denotes the state of a bank switching address.
  • "Add” denotes the state of the setting line for the row and column addresses.
  • “Out” denotes a readout data output. More precisely, the logical signal of chip select (CS) is L-active, so that it is expressed as “/CS”. Similarly, the row and column addresses are also L-active, so that they are expressed as "/RAS” and “/CAS”, respectively. The logical signal of write enable is also L-active, so that it is expressed as "/WE”.
  • the bank switching address is "BS”.
  • the setting line for the row and column addresses is "Add”.
  • the readout data output is "Out”.
  • an L-level logic signal is again applied to the terminals "/CS” and “/RAS", and an H-level logic signal is applied to the terminal "/CAS”.
  • the state "Add” is set to a row address R1.
  • an L-level logic signal is applied to each of the terminals "/CS” and “/RAS”, and an H-level logic signal is applied to the terminal "/RAS”.
  • the state "Add” is set to a column address C1.
  • data D01, D11, D21, ... are outputted as "Out".
  • a moving picture decoding device for decoding a moving picture by writing or reading picture data on or from a picture memory, wherein a synchronous DRAM is employed as the picture memory.
  • the synchronous DRAM has a plurality of banks, each of which is accessed by a common column address and a common row address and designated by a bank switching address.
  • the bank switching address may be allocated between the upper most bit of the horizontal address and the lower most bit of the row address.
  • the bank switching address may be allocated between the column address and the row address.
  • the bank switching address may be allocated to the lower most bit of the vertical address.
  • the synchronous DRAM having a plurality of banks each of which is accessed by common row and column addresses and designated by the bank switching address is employed as the picture memory, and address allocation is so made that the bank switching address bit is allocated so as to be at the lower order side than at least the row address and at the higher order side than the horizontal address on the picture image.
  • Fig. 1 is a block circuit diagram showing an example of a basic arrangement of a MC-DCT hybrid encoding device.
  • Fig. 2 illustrates data readout when employing a DRAM for the picture memory.
  • Fig. 3 is a timing chart for illustrating data readout from the DRAM.
  • Fig. 4 is a block circuit diagram showing an arrangement of a moving picture decoding device according to the present invention.
  • Fig. 5 illustrates a picture image of a synchronous DRAM.
  • Fig. 6 illustrates a data block of a 8 ⁇ 8 size in terms of coordinate values on the picture image.
  • Fig. 7 is a timing chart for illustrating the basic function of the SDRAM.
  • Fig. 8 illustrates the address allocation for the SDRAM employed in the present embodiment.
  • Fig. 9 shows a concrete example of address allocation shown in Fig. 8.
  • Fig. 10 is a timing chart for the SDRAM employing the address allocation shown in Fig. 9.
  • Fig. 11 illustrates data output for the concrete example of address location shown in Fig. 9.
  • Fig. 12 illustrates a concrete example of address allocation shown in Fig. 8.
  • Fig. 13 illustrates data output for the concrete example of address location shown in Fig. 12.
  • Fig. 14 illustrates another concrete example of address allocation shown in Fig. 8.
  • Fig. 15 is a timing chart for the SDRAM employing the address allocation shown in Fig. 14.
  • Fig. 16 illustrates data output for the concrete example of address location shown in Fig. 14.
  • an input terminal 11 of the present embodiment shown in a block circuit diagram of Fig. 4, there is supplied a data string signal or so-called bit stream which has been encoded in accordance with e.g. the above-described MC-DCT encoding method.
  • the input signal is also supplied to an inverse variable length coding or decoding circuit (IVLC) 12 for inverse variable length decoding for generating compressed data and motion vector data for motion compensation.
  • IVLC inverse variable length coding or decoding circuit
  • the compressed data from the IVLC circuit 12 is transmitted to an inverse quantization circuit 13 for inverse quantization.
  • the inverse-quantized data is supplied to an inverse DCT circuit 14 for an inverse DCT operation, that is an operation which is the reverse of the DCT operation, so as to be supplied to an additive node 15.
  • the motion-compensated vector data from the IVLC circuit 12 is supplied to a motion compensation circuit 16 from which a readout address for the motion compensation block based on the motion compensation vector is supplied to a memory controller 21 of a frame memory 20 as a picture memory. Data of the motion compensation block is read from the frame memory 20 in accordance with the readout address and transmitted to the motion compensation circuit 16.
  • the motion-compensated picture data from the motion compensation circuit 16 is supplied to the additive node 15.
  • Addition output data from the additive node 15 is supplied to the frame memory 20 so as to be written in the locations designated by the addresses supplied from a write address counter 17.
  • the write address counter 17 is supplied with the output data from the additive node 15 and counts up each time the addition output data is outputted from the additive node 15.
  • the picture data written in the frame memory 20 is read out in accordance with the addresses transmitted from a display address counter 31 to the memory control unit 21, and is outputted at an output terminal 33 via a display buffer memory 32. It is noted that the present embodiment is designed to accelerate data readout of a motion compensation block from the frame memory 20 in accordance with the readout address of the motion compensation block based on the motion compensation vector transmitted from the motion compensation circuit 16 to the memory control unit 21.
  • the frame memory 20 is a synchronous DRAM having plural banks each of which is accessed by common column and row addresses and each of which is designated by a bank changeover address.
  • SDRAM The basic function of the synchronous DRAM, referred to herein as SDRAM, is explained in "NIKKEI ELECTRONICS", pages 143 to 147, No.553, issued on May 11, 1992.
  • SDRAM Secure Digital RAM
  • This SDRAM latches control signals and data in synchronism with external clocks of 66 to 100 MHz, thereby facilitating the designing of the signal timing.
  • the SDRAM may be accessed with the cycle time of 10 to 15 ns by inputting and outputting of data of contiguous addresses (burst transfer).
  • burst transfer With the SDRAM, the memory cell array in the chip is divided into plural banks. Interleaving renders it possible to achieve continuous addressing even if row addresses are different.
  • the data outputting sequence may be changed during the burst transfer. However, if different rows in the same bank are accessed, data outputting is interrupted, as explained subsequently.
  • FIG. 6 picture data readout is explained for the case in which 8 X 8 motion compensation (MC), for example, is to be performed in 1048576 words ⁇ 8 bits ⁇ 2 banks, with a 360 ⁇ 240 field, a picture image of which is shown in Fig. 5. Meanwhile, it is assumed that only one bank (bank 0) is employed.
  • MC motion compensation
  • a data length continuously accessed in advance with the burst transfer mode called a burst length or a lap length
  • data up to the column address "47" may be outputted by simply setting the row address "32" and the column address "40" without the necessity of subsequent setting of the column addresses. That is, readout data d(40, 32), d(41, 32), d(42, 32), ... d(47, 32) may be outputted by simply setting the row address "32" and the column address "40".
  • Fig. 7 illustrates the above example by a timing chart.
  • the bank employed herein is only the bank 0, as mentioned above.
  • CLK denotes clock pulses having the frequency of 100 MHz.
  • the logical signal of chip select (CS) is L-active and hence designated by "/CS”.
  • the logical signal of chip select (CS) is L-active, so that it is expressed as "/CS”.
  • the row and column addresses are also L-active, so that they are expressed as "/RAS” and “/CAS", respectively.
  • the logical signal of write enable is also L-active, so that it is expressed as "/WE”.
  • the bank changeover address is "BS”.
  • the setting line for the row and column addresses is "Add”.
  • the readout data output is "Out”.
  • L-level logical signals are supplied as "/CS” and "/RAS”
  • an H-level logical signal is supplied as "/CAS”
  • an L-level logical signal is supplied as "/WE”
  • "BS” is set to "0”
  • a command C M3 is issued which renders the next readout effective.
  • This command C M3 is called a precharge command which causes a necessary operation to be performed when accessing a row in a given bank after having accessed some different row in the same bank.
  • L-level logical signals are supplied as "/CS” and "/RAS”
  • an H-level logical signal is supplied as "/CAS” and an H-level logical signal is supplied as "/WE”
  • "BS" is set to "0”
  • a command C M4 is issued activating the bank 0 of the SDRAM of the chip selected by "/CS”.
  • the row address is set to "33" by "Add”.
  • An L-level logical signal is supplied as "/CS"
  • an H-level logical signal is supplied as "/RAS”
  • an L-level logical signal is supplied as "/CAS”
  • an H-level logical signal is supplied as "/WE”
  • "BS” is set to "0”, as in the case of the command C M2 .
  • "BS” is set to "0” and a command C M5 is issued to cause data of the bank 0 of the SDRAM of the chip selected by "/CS” to be read out.
  • the column address is set to "40" by "Add”.
  • the SDRAM outputs data of contiguous addresses at a cycle of 50 to 60 ns by a set of e.g. eight clocks in a timed relation to the clocks of e.g. 100 MHz (corresponding to the period of 10 ns) by the setting of the continuous addresses.
  • continuous accessing may be had on the clock basis by controlling the input timing of the column address, even in cases where the column addresses are not consecutive.
  • Continuous accessing may be had by changing the bank if the row addresses are changed. Consequently, high-speed data readout becomes possible if the SDRAM is applied to the picture memory.
  • the data readout speed may be improved further. That is, it suffices if the data output is not interrupted when switching is made from a given row to another row in the same bank.
  • interruption in the data outputting may be eliminated by such address allocation in which an SDRAM is employed as the frame memory 20 to take advantage of the features of the SDRAM that, when access is had to the same row, continuous accessing may be had on the clock basis even if the column addresses are not consecutive, if the inputting to the column address is controlled, and that, if the row address is changed, continuous accessing may be had by changing the banks.
  • Fig. 8 illustrates the address allocation for the SDRAM employed in the present embodiment.
  • the bank address switching bit BS is allocated within the ranges shown in Fig. 8. That is, the bank changeover address BS is located in a BS allocation range between the upper most bit of the horizontal address X and the lower most bit of the row address R.
  • the field number F shown in Fig. 5 is entered as shown in Fig. 8.
  • the bank switching address BS is positioned at the lower most order side within the range of the BS allocation.
  • the column address is divided into an upper order side address (C2) and a lower order side address (C1).
  • Fig. 8 shows address allocation in which the bank switching address BS is positioned at the upper most order side within the BS allocation range.
  • the address allocation shown is merely illustrative and any position may be selected if only the bank switching address bit BS is within the BS allocation range.
  • FIG. 9 illustrates readout of picture data in which the bank switching address bit is within the BS allocation range and the number of the column address C is coincident with that of the horizontal address X.
  • the horizontal address X and the vertical address Y on the picture image are of 9 and 8 bits, respectively
  • the field number F is 4 bits
  • the column address C, the row address R and the bank switching address BS are of 10, 11, and 1 bits, respectively.
  • FIG. 10 A timing chart for the SDRAM, corresponding to the address allocation shown in Fig. 9, is shown in Fig. 10. Banks 0 and 1 are employed, and "CLK”, “/CS”, “/RAS”, “/CAS”, “/WE”, “BS”, “Add” and “Out” are of the same meanings described in connection with Fig. 7 and hence are not explained herein. Referring to Fig.
  • an L-level logical signal is supplied as "/CS”
  • an H-level logical signal is supplied as “/RAS”
  • an L-level logical signal is supplied as "/CAS”
  • an H-level logical signal is supplied as "/WE”
  • "BS" is set to "0”
  • a command CM2 is issued causing data of the bank 0 of the SDRAM of the chip selected by the logical signal "/CS” to be read out.
  • the row address is set to "40" by the logical signal "Add”.
  • the setting to "40" of the column address is made on the bank 0 and corresponds to the horizontal address "40" on the picture image.
  • an L-level logical signal is supplied as "/CS”
  • an H- level logical signal is supplied as “/RAS”
  • an L-level logical signal is supplied as "/CAS”
  • an H-level logical signal is supplied as "/WE”
  • "BS" is set to "1”
  • a command C M4 is issued causing data of the bank 0 of the SDRAM of the chip selected by the logical signal "/CS” to be read.
  • the row address is set to "40" by the logical signal "Add”.
  • the setting to "40" of the column address is made on the bank 0 and corresponds to the horizontal address "40" on the picture image.
  • the row address is set to "17" with the command C M6
  • the column address is set to "40" with the command C M7 .
  • the setting of the row address to "17” corresponds to "34" of the vertical address on the picture image
  • the setting of the column address to "40” corresponds to "40" of the horizontal address on the picture image.
  • "Out” outputs eight readout pulse data d(40, 33) ... d(47, 33) while eight readout data are continuously outputted on the picture image corresponding to the different row of the bank 0, not shown.
  • the command C M8 is a pre-charge command of validating the readout of the different row in the bank 1.
  • Fig. 11 illustrates data being outputted in accordance with the example of data allocation shown in Fig. 9. The data outputting mode is explained by referring to Fig. 6.
  • the setting of the row and column addresses of one of the banks may be set while data are read out from the other bank to enable data to be read out continuously.
  • Fig. 12 shows an example in which the bank switching address bit BS is allocated to the lower most bit of the vertical address Y within the BS allocation range.
  • the bank changeover address bit BS separates the column address into an upper order side address C2 an a lower order side address C1.
  • the addresses on the picture image are made up of horizontal addresses X (P bits) and vertical addresses (M bits) looking from the lower order side, while the addresses on the SDRAM are made up of column addresses (M bits) and row addresses (N bits), and the bank switching address BS is allocated at the lower most bit of the vertical address Y on the picture image.
  • the column address C is divided into a lower order column address C1 (from 0 bit to (P - 1)th bit, totalling P bits) and an upper order column address C2 (from Pth bit to (M - 1)th bit, totalling (M - P) bits).
  • the row and column addresses of a line "33" of one of the banks may be set by bank switching during the time when the data for the line "32" on the picture image shown in Fig. 6 is read, so that the data on the picture image shown in Fig. 6 may be continuously read in the sequence of "32", "33", “34”, “35”, “36", "37”, “38” and "39".
  • Fig. 14 shows an example in which the bank switching address bit BS is allocated at a lower order side than the LSB of the row address R within the BS allocation range.
  • the addresses on the picture image are the horizontal address X of P bits and the vertical address Y of Q bits, looking from the lower order side, while the address on the SDRAM is the column address of M bits and the row address of N bits, looking from the lower order side.
  • Fig. 15 shows a timing chart of the SDRAM associated with the example of address allocation shown in Fig. 14. Although the banks 0 and 1 are employed herein, only the timing for the bank 0 is shown for simplicity of the explanation. The readout timing is explained by referring to Fig. 6.
  • an L-level signal is supplied as a logical signal "/CS”
  • an H-level logical signal is supplied as a logical signal "/RAS”
  • an L-level logical signal is supplied as a logical signal "/CAS”
  • an H-level logical signal is supplied as a logical signal "/WE”
  • a logical signal "BS” is set to "0”
  • a command C m2 is issued causing data of the bank 0 of the SDRAM of the chip selected with the logical signal "/CS” to be read out.
  • the column address is set at this time to "40" by the logical signal "Add”. This setting on the column address is that for the bank 0 and corresponds to the horizontal address "32" on the picture image shown in Fig. 6.
  • an L-level signal is supplied as a logical signal "/CS”
  • an H-level logical signal is supplied as a logical signal "/RAS”
  • an L-level logical signal is supplied as a logical signal "/CAS”
  • an H-level logical signal is supplied as a logical signal "/WE”
  • a logical signal "BS” is set to "0”
  • a command C m3 is issued for activating the bank 0 of the SDRAM of the chip selected with the logical signal "/CS”.
  • the column address is set at this time to "168" by the logical signal "Add”. This setting on the column address is that for the bank 0 and corresponds to the horizontal address "40" on the picture image shown in Fig. 6.
  • an L-level signal is supplied as a logical signal "/CS”
  • an H-level logical signal is supplied as a logical signal "/RAS”
  • an L-level logical signal is supplied as a logical signal "/CAS”
  • an H-level logical signal is supplied as a logical signal "/WE”
  • a logical signal "BS” is set to "0”
  • a command Cm4 is issued for activating the bank 0 of the SDRAM of the chip selected with the logical signal "/CS”.
  • the column address is set at this time to "296" by the logical signal "Add”. This setting on the column address is that for the bank 0 and corresponds to the horizontal address "40" on the picture image shown in Fig. 6.
  • Fig. 16 shows data being outputted for the example of address allocation shown in Fig. 14.
  • the transverse length of each of the subregions resulting from the division by four is set to 128, as in the case of Fig. 13.
  • the data on the picture image may be read for four lines of "32", “33”, “34” and “35” as the data for the row address "4" of the bank 0.
  • the data on the picture image may be read for four lines of the vertical addresses "36", "37", “38” and "39” as the data for the row address "4" of the bank 1.
  • interruption in the data outputting may be eliminated to realize continuous readout by taking advantage of the feature that continuous accessing may be made on the clock basis by controlling the input timing of the column addresses even though the column addresses are not continuous.
  • a synchronous DRAM in which each of two banks is accessed by the common row and column addresses and each bank is designated by the bank switching address, is employed as the frame memory 20 of the picture memory, and the bank switching address is allocated so as to be on the lower order side of at least the row address and on the higher order side of the horizontal address on the picture image, so that picture data may be read continuously at an elevated rate.
  • the moving picture decoding device is not limited to the above described embodiments.
  • the bank switching bit BS may be located at any position within the BS allocation range.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Memory System (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
EP19930120123 1992-12-15 1993-12-14 Dispositif pour le décodage d'images animées. Withdrawn EP0602588A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP334768/92 1992-12-15
JP33476892A JPH06189292A (ja) 1992-12-15 1992-12-15 動画像復号装置

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Publication Number Publication Date
EP0602588A2 true EP0602588A2 (fr) 1994-06-22
EP0602588A3 EP0602588A3 (fr) 1994-12-07

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EP19930120123 Withdrawn EP0602588A3 (fr) 1992-12-15 1993-12-14 Dispositif pour le décodage d'images animées.

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US (1) US6008850A (fr)
EP (1) EP0602588A3 (fr)
JP (1) JPH06189292A (fr)
KR (1) KR940017887A (fr)
CN (1) CN1091884A (fr)

Cited By (2)

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Publication number Priority date Publication date Assignee Title
GB2303989A (en) * 1995-07-31 1997-03-05 Samsung Electronics Co Ltd Using an SDRAM as a frame memory for motion compensation prediction
TWI806641B (zh) * 2022-01-11 2023-06-21 旺宏電子股份有限公司 記憶體裝置及其操作方法

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Publication number Priority date Publication date Assignee Title
JP3686155B2 (ja) * 1996-03-21 2005-08-24 株式会社ルネサステクノロジ 画像復号装置
US6307588B1 (en) * 1997-12-30 2001-10-23 Cognex Corporation Method and apparatus for address expansion in a parallel image processing memory
KR100282389B1 (ko) * 1997-12-31 2001-02-15 구자홍 에이치디티브이 비디오 디코더의 메모리 제어 방법
JP5147102B2 (ja) * 2005-05-30 2013-02-20 株式会社メガチップス メモリアクセス方法
KR101136900B1 (ko) * 2005-06-28 2012-04-20 엘지디스플레이 주식회사 오버 드라이빙 구동장치 및 구동방법
JP5700228B2 (ja) * 2013-03-13 2015-04-15 コニカミノルタ株式会社 メモリ制御装置および画像形成装置

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US6008850A (en) 1999-12-28
EP0602588A3 (fr) 1994-12-07

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