EP0559322B1 - Structure and method for providing a reconfigurable emulation circuit - Google Patents
Structure and method for providing a reconfigurable emulation circuit Download PDFInfo
- Publication number
- EP0559322B1 EP0559322B1 EP93300667A EP93300667A EP0559322B1 EP 0559322 B1 EP0559322 B1 EP 0559322B1 EP 93300667 A EP93300667 A EP 93300667A EP 93300667 A EP93300667 A EP 93300667A EP 0559322 B1 EP0559322 B1 EP 0559322B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- clock
- signal
- storage
- implementing
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- A—HUMAN NECESSITIES
- A21—BAKING; EDIBLE DOUGHS
- A21B—BAKERS' OVENS; MACHINES OR EQUIPMENT FOR BAKING
- A21B1/00—Bakers' ovens
- A21B1/02—Bakers' ovens characterised by the heating arrangements
- A21B1/24—Ovens heated by media flowing therethrough
- A21B1/245—Ovens heated by media flowing therethrough with a plurality of air nozzles to obtain an impingement effect on the food
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Definitions
- the present invention relates to a structure and method for providing a reconfigurable emulation circuit and is applicable to integrated circuits, and in particular relates to using programmable logic devices to emulate logic circuits.
- target logic circuit In developing an integrated circuit ("target logic circuit"), it is often necessary to provide an implementation of the design in a development system prior to committing the design to a final implementation, such as an ASIC (application specific integrated circuit) or a custom integrated circuit design. Such implementation in a development system is used not only for debugging the integrated circuit, but also for developing systems ("target systems") which will use the integrated circuit.
- Two methods for providing an implementation of the design at the development stage are software simulation and hardware emulation.
- VLSI emulators converts a logic circuit design description or representation into a temporary operating hardware form ("emulation circuit") using reprogrammable logic devices, such as an array of interconnected field programmable gate arrays. Even then, there are several limitations of today's emulation technology.
- Hold time violation artifact is an error condition arising in an emulation circuit having relatively complex clocking structure. This error condition results from the fact that clock skews in the emulation circuit are frequently different from the clock skews of the target logic circuit, because limited resources in reprogrammable logic devices are designed to support the generation and routing of clock signals. Thus, since the error condition is an artifact of the emulation circuit, hold time violation may not actually occur in the target logic circuit. Because today's designs are large and often requiring complex clocking schemes, hold time violation artifact can be expected to occur in all but very simple emulation circuits.
- a practical VLSI emulator is required to take a large design, partitions such a design to implement the circuit over hundreds of field programmable gate arrays, and then interconnects these field programmable gate array to arrive at a functional emulation circuit.
- an effective strategy is lacking in the prior art for partitioning components of the target logic circuit to minimise interconnection delays and interchip connections
- another disadvantage of the prior art is the unsatisfactory circuit performance (i.e. speed) of the emulation circuit, due to avoidable delays of both long interconnection paths within a programmable logic device and interchip interconnections.
- a third disadvantage of the prior art is the low utilisation efficiency of programmable logic devices. Such low utilisation efficiency arises because the numerous interconnections between field programmable gate arrays quickly use up the available I/O pins before a high percentage of the available gates are utilised.
- Butts et al. nor Sample et al. addresses the problems of hold time violation artifact, and utilisation and delay optimisations.
- the methods of Butts et al. and Sample et al. achieve a functional circuit only after considerable manual debugging.
- a method for implementing an emulation circuit comprised of an array of programmable logic devices from a netlist description of a design, said design receiving a plurality of clock sources, the method comprising the steps of: importing the netlist description into a data structure representing the design; characterised by analysing the data structure to identify, for each storage instance receiving a clock signal in the design, a clock path connecting the clock signal to one of the clock sources from which the clock signal is derived; and implementing a portion of each clock path in a programmable logic device dedicated for global clock generation, so as to introduce a predetermined amount of delay in a data path between two storage instances clocked by clock signals from the same clock source.
- a structure for implementing an emulation circuit comprising: a first programmable logic device for generating a clock signal of the emulation circuit; second and third programmable logic devices each receiving the clock signal for implementing first and second logic circuits in the emulation circuit receiving the clock signal; and a fourth programmable logic device for implementing a combinatorial data path between the first and second logic circuits, so as to introduce a predetermined amount of delay in the combinatorial data path between the first and second logic circuits.
- a method and a structure provides an emulation circuit without hold time violation artifact, by introducing a delay in a data path between two storage instances ("different clock storage instances") clocked by different clock signals from the same clock source. Also, in accordance with the present invention, the emulation circuit provides high circuit performance by clustering storage instances with their respective clock and data paths.
- a clock analysis module examines the clock signal of each storage instance and traces the clock path between the clock signal and the clock source from which the clock signal is derived.
- a programmable logic device (“clock generation FPGA") is then dedicated to generate a portion of the clock paths (“global clock paths") identified. The remaining clock paths (“local clock' paths”) are generated in programmable logic devices implementing the emulation circuit.
- some storage instances clocked by clock signals derived from the same clock source are implemented in separate clocked programmable logic devices.
- a portion of the data path or paths between a pair of such clock storage instances is implemented in an unclocked programmable logic device.
- a clustering module clusters each storage instance with (i) the data paths leading to a data input terminal of the storage instance and (ii) the local clock path of the clock signal to the storage instance.
- a partition module assigns the components of each cluster to be implemented by the same programmable logic device so as to minimize delay in the data path.
- "different clock” storage instances are assigned different clocked programmable logic devices ("clocked FPGAs"), and the delay of the delay constraint is provided by an unclocked programmable logic device (“unclocked FPGA”).
- a connectivity module provides a connectivity graph indicating connectivity between clusters.
- a data structure associated with a component common to multiple clusters notes the clusters in which the component is present.
- the common circuits are duplicated in each programmable device to minimize the need for interchip interconnections, and preserve circuit performance.
- FIG. 1 is a block diagram showing the functional blocks of a field programmable logic device (FPGA) suitable for use as components in a logic block module of the present invention.
- FPGA field programmable logic device
- Figure 2 shows a system comprising logic block module 201, FPGA configuration controller 202 and workstation 203, in accordance with the present invention.
- Figure 3 shows logic block module 300 having clock generator FPGA 344, clocked FPGAs 301-328, unclocked FPGAs 345-378, and I/O connectors 329-343 and 379.
- Figure 4 is a block diagram showing certain software modules required to take a target logic design to a program for configuring an emulation circuit in a logic block module, in accordance with the present invention.
- FIG. 5 is a block diagram showing the various steps in clock analysis module 402 of Figure 4, in accordance with the present invention.
- FIG 6 is a block diagram showing certain steps of clustering module 403 of Figure 4, in accordance with the present invention.
- FIG. 7 illustrates certain steps in clock analysis module 402 which identifies and marks clock signals, in accordance with the present invention.
- FIGS 8a and 8b illustrate certain steps in clock analysis module 402 for identifying automatically certain clock qualifier signals from user specified clock strobes and clock sources, in accordance with the present invention.
- Figure 9 illustrates certain steps in clock analysis module 402 for identifying clock paths for each storage instance, in accordance with the present invention.
- Figure 10 illustrates three types of data paths: external data paths, internal data paths and clock qualifier paths, in accordance with the present invention.
- FIG 11a and Figure 11b illustrate certain steps of classifying storage instances in clock analysis module 402 into “same clock” and “different clock types” respectively, in accordance with the present invention.
- Figure 12 illustrates certain steps of implementing clock paths in clock analysis module 402, for implementing "small clocks,” “global clocks” and “local clocks,” in accordance with the present invention.
- Figures 13a and 13b illustrate the effects of introducing interconnect delays by an emulation circuit implemented in programmable logic devices, such delays leading to an error condition known as "hold time violation artifact.”
- Figure 14 illustrates a delay constraint imposed on different clock storage instances to avoid hold time violation artifact, in accordance with the present invention.
- Figure 14 also illustrates why, in the present embodiment, delay constraints need not be imposed on same clock storage instances.
- Figure 15 illustrates the operation of the delay constraint of the present invention in a more complex situation than Figure 14; namely, when portions of the clock paths from a common clock source in a different clock storage instance are implemented in the clock generation FPGA.
- Figures 16a and 16b show an implementation of Figure 14's storage instances 1401 and 1402 in unclocked FPGA 1613 and separate clocked FPGAs 1601a and 1601b, in accordance with the delay constraint of Figure 14.
- FIGS 17a and 17b illustrate by a circuit 1700 how a connectivity graph is constructed by connectivity module 404, in accordance with the present invention; circuit 1700 is also used to illustrate the operation of duplication module 405.
- Figure 18 shows a configuration 1800 in which a logic block module 1802 is interfaced to a target system 1801 via pods 1803a and 1803b, in accordance with the present invention.
- Figure 19 shows the construction of a pod 1900, for use as, for example, pod 1803a of Figure 18.
- the present invention provides a method and structure to implement an emulator circuit from a netlist description.
- the emulator circuit is implemented in a "logic block module," which is a circuit comprising I/O connectors, clocked programmable logic devices, unclocked programmable devices and a clock generation programmable logic device.
- the programmable logic devices used in the embodiments of the present invention described below can be commercially available field programmable gate arrays ("FPGAs").
- FPGAs field programmable gate arrays
- Some examples of FPGAs are the Xilinx 3090 and the Xilinx 4005, both available from Xilinx Corporation of San Jose, CA. FPGAs with 1000-2000 gates and 100 I/O (input/output) pins are widely available at this time.
- FPGA provides a number of input/output (I/O) pins (e.g. IOB1-IOB3) for receiving from an external circuit input signals or providing to an external circuit output signals.
- IOB input/output
- IOB structure which contains I/O buffer circuits to allow the I/O pin to be configured as an input, output, bidirectional pin, or other input/output configurations.
- CLBs configurable logic blocks
- CLB1-CLB6 can each be programmed to provide a logic circuit.
- a routing resource can be a general switch interconnection ("switch line”) for routing data path signals, a special purpose signal line for routing clock signals ("long line”), or a special clock buffer resource providing skew control for clock signals.
- switch line a general switch interconnection
- long line a special purpose signal line for routing clock signals
- clock buffer resource providing skew control for clock signals.
- Clock buffers and long lines are designed to provide shorter interconnect delays than general switched connections.
- long lines and clock buffers are very limited resources. For example, in a Xilinx 4005 field programmable gate array, eight clock buffers are provided per integrated circuit.
- FIG. 2 illustrates a system 200 comprising a logic block module 201, an FPGA configuration controller 202, and workstation 203.
- the emulation circuit is implemented in a logic block module such as logic block module 201.
- Logic block module 201 comprises a clock generation FPGA, clocked FPGAs, unclocked FPGAs, I/O connectors, a non-volatile memory component, and a control FPGA.
- the clock generation FPGA, the clocked and unclocked FPGAs, and the I/O connectors are interconnected by metal conductive traces on the printed circuit board of logic block module 201. These metal traces provide insignificant signal delays, when compared to the delays of either the long lines, clock buffers or the switch lines inside an FPGA.
- the non-volatile memory component shown as EPROM 204, is provided for storing the software necessary to configure control FPGA 205, enable an interface with FPGA configuration controller 202.
- EPROM 204 can be implemented by any electrically erasable read-only memory (EPROM) or other suitable devices.
- Configured in control FPGA 205 is the control circuit for receiving from the FPGA configuration controller 202, through I/O connectors 206 and 207, the data for configurating the FPGAs of logic block module 201.
- control FPGA 205 communicates with FPGA configuration controller 202 over an interface conforming to the JTAG standard 1 .
- the configuration data for programming the FPGAs of logic block module 201 can be provided to FPGA configuration controller 202 by workstation 203 over a standard Ethernet local area network.
- each I/O connector has 100 signal pins, of which 48 are can be used by the emulation circuit.
- the clock generation FPGA, clocked FPGAs and unclocked FPGAs are implemented by Xilinx 4005 field programmable gate arrays, and the control FPGA is implemented by Xilinx 3090 field programmable gate arrays.
- a Xilinx 4005 FPGA has 112 I/O pins which can be configured. However, in the embodiment shown in Figure 3, only 99 I/O pins are available to the emulation circuit, when used as a clocked FPGA, 106 I/O pins are available to the emmulation circuit, when used as an unclocked FPGA, and 89 I/O pins are available to the emulation circuit, when used as a clock generation FPGA.
- the I/O pins of each clocked FPGA, the clock generation FPGA or the signal pins of each I/O connector are distributed among all unclocked FPGAs as evenly as possible.
- the 99 I/O pins of clocked FPGA 209 available to the emulation circuit are divided into 3 groups of 25 pins and 1 group of 24 pins, each group connecting to one of the unclocked FPGAs 211-214.
- the clock generation FPGA shown in Figure 2 as clock generation FPGA 208, provides the major system clock signals for the clocked FPGAs, such as clocked FPGAs 209 and 210 of Figure 2.
- the clocked FPGAs are used to implement storage instances and data paths.
- Unclocked FPGAs such as FPGAs 211-214 of Figure 2, implements interconnections and data paths having only combinatorial circuits.
- the I/O connectors can be connected to a pod to interface a target system.
- the connections between each unclocked FPGA and the clock generation FPGA are provided to route clock qualifier signals (described below) between the clock generation FPGA and each unclocked FPGA, and not for routing clock signals.
- both clocked and unclocked FPGAs are implemented by the same programmable logic devices.
- the connections between the clocked FPGAs and the unclocked FPGAs e.g. interconnection lines 391-1 391-n of Figure 3
- between the clock generation FPGA and the unclocked FPGAs e.g. interconnection line 393-1 to 393-1
- the unclocked FPGAs and the I/O connectors e.g. interconnection lines 392-1 to 392-m of Figure 3
- the logic block module such as logic block module 201 of Figure 2.
- other than interconnection functions only combinatorial circuits each having a single input signal and a single output signal are implemented in unclocked FPGAs so as to providing an additional delay in the data path.
- FIG 4 is a flow diagram showing the steps required in the embodiment ("present embodiment") of Figure 3 to transform a design into an emulator circuit implemented in the FPGAs of a logic block module. Each of the steps of Figure 4 is accomplished by a software module described below.
- block 401 represents the step of importing a netlist into the present embodiment.
- a software module (“import module") running on a workstation reads a design netlist into a data structure of conventional design.
- Import module 401 can read netlists provided in a number of formats, including electronic design intermediate format (EDIF), Toshiba network description language (TDL), and network description language (NDL). These netlist formats are well known in the art.
- EDIF electronic design intermediate format
- TDL Toshiba network description language
- NDL network description language
- Import module 401 also receives user's instructions regarding both the design and the configuration of the logic block module to be implemented. For example, the user can specify that the utilization of each FPGA in the emulation circuit should not exceed a certain percentage, so as to allow sufficient room in each FPGA for incremental modifications to the emulation circuit. Also, the user can provide to import module 401 information regarding the design helpful in subsequent steps, including the steps of clock analysis and partition described below. Such design information includes the names of "clock sources” and "clock qualifiers" (described below). The user can also specify groupings of circuit components which are desired to be implemented in the same FPGA.
- a clock analysis module (represented by block 402 in Figure 4) is invoked to perform an analysis of the clock structure of the netlist.
- Clock analysis module 402 performs the steps shown in Figure 5.
- a clock signal is a signal, other than a power signal, which is connected to a clock input terminal of a storage instance (e.g. a register) either directly or by a "singular path".
- a singular path is a signal path or net comprising combinatorial gates each having a single output signal derived from either (i) a single input signal, or (ii) multiple input signals, one of which being a signal from a singular path, and the remaining signal or signals being power signals.
- Clock analysis module 402 traces back by a breadth first search from each clock input terminal of the storage instance and mark either (i) the clock signal itself, if the clock signal is not a signal in a singular path, or (ii) the signal in the singular path furthest away from the clock input terminal of the storage instance, if the clock signal is in a singular path.
- FIG 7 To illustrate the clock signals which are marked by clock analysis module 402, two examples are provided in Figure 7.
- storage instances are exemplified by D-flip flops.
- storage instances 701-704 are clocked respectively by signals 710-713.
- none of the different signals labelled A, B, C, or D is a power signal. According to the definition of a singular path provided above, signal 713 is not in a singular path because neither one of the input signals A and B of AND gate 705 is a power signal.
- signal 713 is marked as a clock signal.
- each of signals 710-712 is in a singular path.
- signal 710 is derived from signal 714 through the data path formed by invertor 708 and buffer 709, which are each a device having a single output signal derived from a single input signal
- signal 710 is in a singular path.
- signal 711 is in a singular path consisting of NAND gate 707 and buffer 709 because, even though NAND gate 707 has two input terminals, the same input signal is provided to both input terminals of NAND gate 707.
- signal 712 is in a singular path because NAND gate 706 is connected to signal 715 and VDD, which is a power signal.
- clock analysis module will trace back, from output terminal to input terminal in each of the combinatorial gates, to mark signal 714 as a clock signal.
- clock analysis module 402 marks, in step 502, all user specified clock sources, clock qualifiers and clock strobes.
- a clock source is a primary input terminal specified by the user to be a clock source;
- a clock qualifier is any signal which is used to gate a clock signal;
- a clock strobe e.g. the I/O write signal
- a signal can be both a clock strobe and a clock source.
- clock analysis module 402 marks all identifiable clock qualifiers. Identifiable clock qualifiers are marked in the following manner.
- clock qualifiers are located in the manner illustrated by Figure 8a.
- clock analysis module 402 traces through combinational circuits to derive signal nets from each clock strobe, and marks as clock qualifiers the output signals of each storage instance which receives a clock input signal from such signal nets.
- signal A is specified as a clock strobe
- clock analysis module 402 traces through combinatorial gates 801 and 802 to the clock terminal of storage instance 803, and traces through combinatorial gates 801 and 812 to the clock terminal of storage instance 814.
- clock analysis module 402 marks as clock qualifier signals the signals at synchronous data output terminals 810 and 811 of storage instances 803 and 814, respectively.
- clock analysis module 402 traces all signal paths ("forward tracing"), using a breadth first search, to all clock signal input terminals of storage instances reachable through combinatorial circuits and storage instances. After all clock sources have been traced, clock analysis module 402 backtracks through each signal path to mark as clock qualifiers all input signals of the combinatorial gates and all data input signals of storage instances encountered, except for the signals on the signal paths found by the forward tracing.
- clock analysis module 402 traces through combinatorial gates 806 and 805 to the clock input terminal of storage instance 804, through combinatorial gate 818 to the clock input terminal 821 of storage instance 816, and through combinatorial gates 818 and 817 to clock input terminal 820 of storage instance 815. Thereafter, clock analysis module 402 backtracks to mark each of signals C, D, E and I a clock qualifier, unless the signal is in a signal path between another clock source and a clock input terminal of a storage instance.
- clock qualifiers are "propagated” by examining each logic gate receiving one or more clock qualifiers. If every input signal received by the logic gate is either a clock qualifier or a power signal, the output signal is marked clock qualifier. Each combinational logic gate receiving the new clock qualifier is then examined to see if the logic gate's output signal can be marked clock qualifier. This procedure of propagating clock qualifiers are repeated until no new clock qualifier can be marked.
- clock analysis module 402 identifies all clock paths by tracing from the clock input terminal or terminals of each storage instance to a clock source marked in the previous step 502, or a "parent" clock signal.
- a parent clock signal of a given clock signal is a clock signal in the clock path between the given clock signal and a clock source.
- a clock path cannot include a net marked clock qualifier, but includes signal paths going (i) through an input and an output of a combinatorial circuit, (ii) through a clock or asynchronous control input terminal of a storage instance (e.g.
- an asynchronous set or reset signal to a data output terminal of the storage instance, or (iii) through data input and output terminals of a storage instance, if the clock input terminal of such storage instance receives a power signal.
- Part (iii) of the above definition of a clock path is particular useful when emulating circuits having transparent latches clocked by power signals.
- a latch clocked by a power signal is treated as combinatorial logic gate by the present embodiment. Since clock qualifiers cannot be part of a clock path, significant amount of search time is saved by marking these signals in step 502.
- Figure 9 illustrates the process of identifying clock paths.
- signal C is a signal marked clock qualifier at step 502, and signal A is marked a clock source.
- a breadth first search traces to signal 904 through storage unit 905, which has a clock input terminal coupled to ground voltage.
- clock analysis module 402 first traces through the clock input terminal of storage unit 905.
- clock analysis module 402 continues tracing through signal 904 at the synchronous data input terminal of storage unit 905.
- clock analysis module 402 traces through combinatorial gate 902, but ignores the path through signal C, which is marked clock qualifier, to follow signal 903 to the synchronous data output signal of storage unit 901. From signal 903, clock analysis traces through storage instance 901 to signal A, which is a clock source.
- the clock path of storage unit 907 includes storage instances 901 and 905, and combinatorial gate 902.
- clock analysis module 402 examines, in step 504, each storage instance to determine if the storage instance can be classified into one of four types, according to data paths leading into the storage instance's synchronous data input terminal.
- a data path is defined as a signal path between the storage instance's synchronous data input terminal and either (i) a clock source or clock qualifier signal ("clock qualifier path"), (ii) a primary input terminal ("external data path”), other than a clock source or clock qualifier signal, or (iii) a data output terminal of another storage instance (“internal data path”), other than a clock source or a clock qualifier signal.
- both signal CLK and signal A are primary input signals, provided respectively at primary input pins 1004 and 1008. Further, signal CLK is a primary input signal specified as a clock source. Data path 1003 of storage instance 1001 is classified as an "external data path,” if signal 1009 is not specified as a clock qualifier, and as a "clock qualifier path,” if signal 1009 is specified as a clock qualifier. Finally, data path 1005 is classified as an "internal data path.”
- a data path goes through only (i) combinatorial circuits, (ii) a storage instance between an asynchronous control input terminal (e.g. asynchronous set or reset) of the storage instance and a data output terminal of the storage instance or (iii) a storage instance between a data input terminal of the storage instance and a data output terminal of the storage instance, if the storage instance is clocked by a power signal.
- asynchronous control input terminal e.g. asynchronous set or reset
- clock analysis module 402 classifies each such storage instance "clock generation.” If all data paths leading to a storage instance's data input terminal are clock qualifier paths, clock analysis module 402 classifies each such storage instance "clock generation.” If all of the data paths are external data paths, but not all primary input terminals of these external data paths are clock qualifiers, clock analysis module 402 classifies such storage instance "external.” However, if the data input terminal of a storage instance ("present storage instance") has at least one internal data path, and all such internal data paths originate from storage instances clocked by a the same clock signal as the present storage instance, clock analysis module 402 classifies the present storage instance "same clock".
- Figure 11b shows an example of a "same clock" storage instance 1152, having a single data path to its synchronous data input terminal originating from storage instance 1151, which is clocked by the same clock signal as storage instance 1151.
- clock analysis module 402 classifies the present storage instance "different clock”.
- Figure 11a provides an example of a different clock storage instance 1102. As shown in Figure 11a, storage instances 1101 and 1102 are clocked by clock signals 1106 and 1107, which are both derived from clock source CLK. If clock paths 1104 and 1105 are not identical and each comprise more than a singular path, then signals 1106 and signal 1107 are different clocks and thus storage instance 1102 is classified as "different clock.”
- clock analysis module 402 builds, at step 505, clock trees for each clock source to provide subsequent software modules a data structure for quickly determining the relationship between any pair of clock signals.
- Each clock tree is rooted at the clock source, and depending on whether one clock signal is derived from another, any pair of clock signals in the clock tree can have either a "parent-child” relationship, or a "sibling" relationship with each other.
- clock signal CLK has a parent-child relation with each of clock signals 1106 and 1107, since both clock signals 1106 and 1107 are derived from clock signal CLK.
- Clock signals 1106 and 1107 has a sibling relationship between them, since both clock signals 1106 and 1107 are derived from clock signal CLK, but not from each other.
- clock analysis module 402 will accordingly build a common clock tree for clock signals derived from these input clock signals.
- clock analysis module 402 analyzes the clock trees to select a predetermined number of clock signals for implementing in a clock generation FPGA.
- These clock signals generated by the clock generation FPGAs are called “global clock” signals, and are used to derive other clock signals.
- the clock paths of eight global clock signals can be implemented in a clock generation FPGA.
- Other clock signals are derived from the global clock signals, which act as “internal clock sources,” using logic in the clocked FPGAs.
- Clock signals which supplies less than a certain number of storage instances are called “small clocks.”
- Clock signals that are intended solely to generate other clock signals are called “generator clocks”.
- a clock signal which is neither a generator clock, a global clock or a small clock is called a "local clock.”
- all clock signals are distributed by clock buffers on long lines, except for small clocks.
- Small clocks are not distributed by a clock buffer, since clock buffers in each FPGA are scarce resources.
- small clocks are also routed by long lines.
- local clock signals can reach any part of an FPGA in substantially less than the interconnect delay than a switch line.
- the clock skew of the clock signal between any two points in the programmable logic device is insignificant, when compared to a data path delay.
- FIG 12 illustrates schematically the partitions between "global” and "local” clock paths.
- two clock sources A and B are roots to two clock trees generating clock signals 1204-1 to 1204-n.
- Clock analysis module 402 finds eight global signals 1203-1 to 1203-8 from which all other clock signals 1204-1 to 1204-n can be generated.
- the portions of the clock paths (“global clock paths") between the global clock signals 2and the clock sources, represented by clock paths 1201 are implemented in the clock generation FPGA.
- the remaining portions of the clock paths (“local clock paths”), represented by clock paths 1202 are implemented in clocked FPGAs.
- FIG. 13a shows a circuit 1300 of the target logic circuit.
- two storage instances 1301 and 1302 are clocked by clock signal Clk, and there exists a data path 1303 between the data output terminal of storage instance 1301 and the data input terminal of storage instance 1302.
- clock signal 1308 received by the clock input terminal of storage instance 1301 is the clock signal CLK delayed by interconnect delay elements 1304 and 1305.
- clock signal 1309 received by the clock input terminal of storage instance 1302 is clock signal Clk delayed by interconnect delay elements 1304 and 1306.
- Data path 1303 is also shown to be delayed by interconnect delay element 1307.
- emulation circuit 1350 To ensure that emulation circuit 1350 is functional, emulation circuit 1350 must satisfy the requirement that the delay introduced by interconnect delay elements 1306 cannot exceed the interconnect delay 1305 by more than the delay of interconnect delay element 1307. Otherwise, a hold time violation at storage instance 1302's data input terminal may result from the propagation of a possible change in storage element 1301's data output signal arriving too early, thereby corrupting the value at the data input terminal of storage instance 1302, prior to the time the previous value is latched by the transition of clock signal 1309.
- Figure 13a and 13b show same clock storage instances, the analysis for different clock storage instances are substantially similar.
- the different clock storage instance case is obtained by substituting a clock path for each of the direct connections 1310 and 1312 between the clock source and the respective clock input terminals of storage instances 1302 and 1301.
- hold time violation artifact can also occur when the delay introduced by interconnect delay element 1306 exceeds the delay introduced by the interconnect delay element 1305 by more than the delay introduced by interconnect delay element 1307 in the data path.
- hold time violation artifact can be worse than the same clock storage instance case because the delay elements 1305 and 1306 introduced to the different clock paths may be substantially different.
- this delay constraint provides that two storage instances having an internal data path between them and clocked by different clock signals from the same clock source (i.e parent-child or sibling clock signals) should preferably be implemented on separate clocked FPGAs, and interconnected by an unclocked FPGA, unless the storage instance at whose data input terminal the data path terminates is clocked by a parent signal of the clock signal clocking the storage instance at whose data output terminal the data path begins.
- Figure 14 shows two storage instances 1401 and 1402 having, in the target logic circuit, data path 1403 between a data output terminal of storage instance 1401 and a data input terminal of storage instance 1402.
- the interconnect delay elements introduced by emulation are shown in the data path and the clock paths respectively as interconnect delay elements 1404, 1407 and 1408.
- the case of different clock storage instances are first considered. In that situation, although both storage instances 1401 and 1402 have a common clock source CLK, clock paths 1405 and 1406, which are respectively the clock paths of storage instances 1401 and 1402 are different.
- the delay constraint of the present invention provides that the storage instances 1401 and 1402 should preferably be implemented in separate clocked FPGAs interconnected using an unclocked FPGA.
- clock paths 1406 and 1405 are implemented in the respective clocked FPGAs of storage instances 1401 and 1402 using clock buffers and long lines.
- the interconnect delay elements 1407 and 1408 introduced by the emulation circuit are each substantially less than the delay of a switch line connection.
- the delay constraint adds sufficient delay to data path 1403 to ensure that hold time violation artifact does not occur between storage instances 1401 and 1402.
- Figure 14 can also represent same clock storage instances, if clock paths 1405 and 1406 are identical. In that case, it is clear that, by implementing storage instances in separate clocked FPGAs and interconnecting the data path 1403 through an unclocked FPGA will result in overcoming hold time violation artifact in substantially the same manner as the different clock storage instance case. However, this delay constraint is not necessary in the present implementation for same clock storage instances.
- the interconnect delay elements 1407 and 1408 introduced by emulation correspond to delays in the clock buffers and long lines of the clocked FPGA, since local clock paths are implemented through clock buffers and long lines providing both clock skew controls and minimum propagation delay.
- the interconnect delay element 1404 introduced by the emulation circuit into data path between storage instances 1401 and 1402 are implemented over general switched lines.
- the delay difference in the interconnect delay elements 1407 and 1408 is always less than the interconnect delay element 1404 through general switched lines. Thus, delay constraints are not imposed on same clock instances in this embodiment.
- FIG. 15 A complex example involving delay constraints in two pairs of storage instances is illustrated by Figure 15.
- delay constraints are placed between storage instances 1502 and 1503, and between storage instances 1501 and 1502. Since the clock signals of storage instances 1501 and 1502 are derived from the same global clock signal 1512, substantially similar to the relation between clock signals of storage instances 1401 and 1402 of Figure 14, the manner in which the delay constraint between storage instances 1501 and 1502 prevents hold time violation artifact is substantially the same as described above with respect to storage instances 1401 and 1402 of Figure 14. A description of how the delay constraint operates to prevent hold time violation artifact between storage instances 1501 and 1502 is therefore omitted.
- the clock signals of storage instances 1502 and 1503 are sibling clock signals 1522 and 1523, each having a portion 1514 or 1515 of their respective clock path in clock generation FPGA 1520.
- the interconnect delay introduced to the clock signal 1522 of storage instance 1502 is the sum of (i) the interconnect delay of clock path 1515 in the clock generation FPGA 1520, and (ii) the interconnect delay of internal clock path 1505 in the clocked FPGA 1524.
- the interconnect delay introduced to the clock signal 1523 of storage instance 1503 is the sum of (i) the interconnect delay of clock path 1514 in the clock generation FPGA 1520 and (ii) the interconnect delay of clock path 1517 in the clocked FPGA 1519.
- each interconnect delay introduced into clock paths 1515, 1505, 1514 and 1517 is substantially less than the delay of general switched interconnections through an FPGA.
- the difference in interconnect delays in the total clock paths of storage instances 1502 and 1503 is less than general switched interconnections and the interchip delay through an unclocked FPGA 1518, such as required by the delay constraint between clusters 1502 and 1503.
- the delay constraint of storage instances 1502 and 1503 also prevents hold time violation artifact in data path 1516 between storage instances 1502 and 1503, even though parts of the clock paths of storage instances 1502 and 1503 are implemented in clock generation FPGA 1520.
- a clustering module (represented by block 403 of Figure 4) is invoked to collect storage instances and their clock and data paths for circuit partitioning at a subsequent step.
- the subsequent partition step implement connected clusters components in the same FPGA whenever possible, so as to minimize interconnections between clocked FPGAs, which are connected through unclocked FPGAs at the expense of interchip interconnect delays.
- Clusters of the present embodiment can be implemented by conventional data structures, such as linked lists.
- Figure 6 is a flow chart illustrating the steps performed by clustering module 403.
- clustering module 403 forms in step 601 a cluster for each clock generation storage instance. Ideally, all clock signals should be generated in the clock generation FPGA. However, in certain design, as explained above, because the present embodiment can support only the generation of eight clock signals in the clock generation FPGA, only the clock paths generating the global signals are clustered for implementation in the clock generation FPGA.
- clustering module 403 sets up in step 602 clusters according to user specified constraints.
- user specified constraints include "terminal" and "component” clusters.
- Terminal clusters are clusters of primary I/O terminals for interfacing with a target system.
- Component clusters are clusters of components which the user considers important to be implemented in the same FPGA. An example of such a component cluster can be an asynchronous portion of the target logic circuit.
- clustering module 403 forms "timing clusters" in step 603.
- each storage instance is clustered with (i) components of its external and internal data paths ("data part"), and (ii) components of local clock paths ("clock part”).
- each output terminal is clustered with its data path.
- Figure 11a can be used to illustrate a timing cluster.
- Clustering module 403 forms a timing cluster including data path 1103, clock path 1104, and storage instance 1102.
- the data and clock parts are identified using breadth first searches starting respectively from the data input terminal of the storage instance and from the clock input terminal of the storage instance. In this embodiment, during clustering of a data part, input buffers of an external data path are identified so that an external data path can be treated the same way as the an internal data path.
- each cluster should include a number of components no larger than the size which can be handled by a single FPGA. However, if a cluster is formed having more components than can be implemented in an FPGA, such a cluster is broken up into smaller clusters along non-critical nets. Critical nets are specified by the user prior to running clustering module 403. Clustering module 403 will not use critical nets to break up a large cluster. To select a non-critical net for breaking up a cluster, clustering module 403 uses heuristic algorithms known in the art. Of course, nets that are separated into different FPGAs as a result of breaking up a large cluster are reported to the user, who can then adjust the list of critical nets, if the net selection by clustering module is unsatisfactory. Clustering module 403 can then be rerun for a different result. One heuristic for selecting a non-critical net selects the net in the cluster with the most fan-out.
- the final step 604 of clustering module 403 forms clusters of the remaining components still to be clustered.
- a connectivity module 404 provides a directed connectivity graph among the clusters. Because circuits implemented in separate clocked FPGAs are interconnected through an unclocked FPGA, it is desirable that clusters with high connectivity between them be implemented in the same FPGA whenever possible. The connectivity graph provided by connectivity module 404 guides the subsequent partition step to minimize interchip interconnections.
- a connectivity graph of the clusters created by connectivity module 401 contains two types of nodes.
- Connectivity module 404 first creates "cluster nodes" in the connectivity graph to represent the clusters being formed in the previous step. Then, each signal in the target logic circuit is examined. If a signal is either an input signal or an output signal in each of the data paths of two or more clusters, a "signal node" is created with a directed edge connecting the signal node to each such cluster.
- Figures 17a and 17b illustrate the connectivity graph of the present invention.
- four storage instances 1701-1704 are clocked by a clock signal Ck, which is derived by gating a clock qualifier signal f with global clock CLK.
- signal f is a data output signal of storage instance, such that signal f is an input signal to each of the clusters of storage instances 1701-1704.
- An output signal b of storage instance 1701 and a signal a are input signals to NAND gate 1705, which output signal d is latched by storage instance 1702.
- Signal a which is an output signal of storage instance 1702, is inverted by inverter 1706 to provide signal e at a data input terminal of storage instance 1703.
- Signal d is inverted by inverter 1708 at a data input terminal of storage instance 1704.
- connectivity module 404 described above identifies in storage instance 1702's cluster data part signals a, b and d, and clock part signals f and Ck.
- signals a, b, and f are input and output signals of the cluster.
- clock signal CLK is a global clock signal
- clock signal CLK is not included in the clock part of storage instance 1702's cluster.
- Further clock signal Ck is an internal signal an internal signal to each of the clusters of storage instances 1701-1704.
- connectivity module 404 identifies data part signals a and e in storage instance 1703's cluster, in which signal a is an input signal of storage instance 1703's cluster.
- data part signals d and g are internal signals of storage instance 1704's cluster and signal b is an input signal of storage instance 1704's cluster.
- each of the clusters of storage instances 1701-1704 has input signal f in their respective clock part.
- Figure 17b shows the portion of connectivity module 404's connectivity graph involving the clusters of storage instances 1701-1704. In Figure 17b, cluster nodes are shown as circles, and signal nodes are shown as solid dots.
- connectivity module 404 identifies clock part signal f in each of the clusters of storage instances 1701-1704, the connectivity graph shows a directed edge pointing from signal f to each of cluster nodes 1701-1704.
- signal b which is an input signal to both storage instance 1702's cluster and storage instance 1704's cluster, is shown in the connectivity graph of Figure 17b as having a directed edge pointing to each of cluster nodes 1702 and 1704. Since signal b is also an output signal of storage 1701's cluster, a directed edge pointing from cluster node 1701 is provided.
- signal a which is an input signal of the clusters of storage instances 1703 and 1704 and an output signal of storage instance 1702, has a directed edge pointing to each of the cluster node 1703 and 1704 and a directed edge originating from clusters 1702. Since both signals e and g are signals internal to their respective clusters, neither signals e nor g are represented in the connectivity module 404's connectivity graph.
- a duplication module 405 ( Figure 4) stores with each component a list of the one or more clusters to which the component belongs. To allow such a list to be associated with each component, each component in the target logic circuit is associated with a conventional data structure, such as a linked list. For example, referring back to Figure 17a, since NAND gate 1707 is in the clock part of the cluster of each of storage instances 1701-1704, NAND gate 1707 is provided a data structure indicating that NAND gate 1707 is common to the clusters of each of storage instances 1701-1704.
- NAND gate 1705 is common to both the cluster including storage instance 1702 and the cluster including storage instance 1704
- NAND gate 1705 is associated with a data structure indicating that NAND gate 1705 is common to both the cluster of storage instance 1702 and the cluster of storage instance 1704.
- Inverters 1706 and 1708 are each associated with a data structure indicating to their respective clusters.
- the connectivity graph created by connectivity module 404 and the duplication list associated with each component provided by duplication module 405 are used by partition module 406 in the next step to determine the partitioning of target logic circuit among the available programmable logic devices of the logic block module.
- Partition module 406 partitions the target design according to the connectivity amongst the clusters. Partition module 406 seeks to minimize interconnection through unclocked FPGA by assigning clusters with substantial common signals to the same FPGA. A conventional metric weighted by both connectivity and any delay constraint between two clusters are used to determine if the two clusters are to be implemented in the same FPGA. When two clusters are implemented in separate clocked FPGAs, signals connecting the two clusters are routed through an unclocked FPGA to provide the interconnection. Because an entire cluster is assigned to an FPGA, interconnections between FPGAs are necessary only at the common signals which are input and output signals of the two clusters. It is believed that such common signals are few in number because of prevailing design methodologies.
- the present invention minimizes interchip connections. Because interchip connections are minimized, a larger number of components than previously possible can be implemented in an FPGA before the I/O pins of an FPGA become limiting. Consequently, the present invention provides a much higher utilization of the logic gates in an FPGA than the utilization of logic gates achieved by the prior art.
- partition module 406 The algorithm for implementing partition module 406 is substantially similar to other partition algorithms well known in integrated circuit design, and can be implemented by modifying one such algorithm using techniques possessed by one of ordinary skill.
- Figures 16a and 16b illustrate an implementation of Figure 14's delay constraint by partition module 406.
- Figure 16a shows the cluster including storage instance 1401 implemented in clocked FPGA 1601a.
- storage instance 1401 is implemented in one or more configurable logic blocks in FPGA 1601a.
- the global clock signal 1603 is provided by clock generation FPGA 1602 to I/O buffer 1604 and routed through a long line 1614 to the clock path 1405 implemented in one or more configurable logic blocks in clocked FPGA 1601a, which is configured to generate the clock signal at the clock input terminal 1609 of storage instance 1401.
- the clock signal generated by clock path 1405 is routed by long line 1605 to a clock buffer 1606 prior to reaching clock input terminal 1609 of clock instance 1401 over long lines 1607 and 1610.
- the portion of data path 1403 between clock instances 1401 and 1402 implemented in clocked FPGA 1601a is shown as the general switched signal path through general switch 1611 and I/O buffer 1612 to unclocked FPGA 1613.
- Figure 16b shows the cluster including storage instance 1402 implemented in the FPGA 1601b.
- storage instance 1402 is implemented in one or more configurable logic blocks in clocked FPGA 1601b.
- the global clock signal 1603 is provided to I/O buffer 1651 and is routed through a long line 1652 to one or more configurable logic blocks of FPGA 1601b configured to implement clock path 1406, which generates the clock signal at the clock input terminal 1653 of storage instance 1402.
- the clock signal generated by clock path 1406 is routed over long line 1660 to clock buffer 1654 prior to reaching the clock input terminal 1653 of clock instance 1402 over long lines 1655 and 1656.
- FIG. 16b The portion of data path 1403 between storage instances 1401 and 1402 implemented in clocked FPGA 1601b is shown in Figure 16b as the signal path between input signal 1657 from unclocked FPGA 1613, and the data input terminal 1622 of storage instance 1402.
- Signal 1657 is routed through I/O buffer 1658, and the general switched signal path comprising switches 1659 and 1620, and switch lines 1621 and 1622, through one or more configurable logic blocks of clocked FPGA 1601b. These configuration logic blocks are configured to provide data path 1403.
- Figure 18 illustrates how a logic block module 1802, e.g. logic block module 200 of Figure 2, can be interfaced to a target system 1801, where the target logic circuit emulated by logic block module 1802 is expected to be deployed.
- a target system 1801 such as a printed circuit board, is connected to logic block module 1802 using two "pods" 1803a and 1803b. Each pod is connected to a corresponding one of I/O connectors 1804a and 1804b on the side of logic block module 1802, and a corresponding one of primary I/O terminals 1805a and 1805b on the side of target system 1801.
- Each primary terminal can be, for example, a socket arranged to received the pins of the target integrated circuit emulated by logic module 1801.
- pod 1900 comprises a clocked FPGA 1901 connected to I/O connector 1902 clock I/O connector 1904 and probe or logic analyzer connector 1905 and primary I/O terminal connector 1903.
- I/O connector 1902 is connected to an I/O connector of a logic block module 1802, and the primary I/O terminal connector 1903 is connected to another primary I/O terminal connector in a target system.
- FPGA 1901 is provided to route the signals of I/O connector 1902 according to the expected pin-out of primary I/O connector 1902.
- Tristate nets involving primary input and output pins in the target design are implemented in a pod between the logic block module and the target system.
- partition module 406 After partition module 406 completes partitioning the design and assigns the partitions into the FPGAs and I/O connectors of a logic block module, the delay constraints between clusters are again revisited to ensure that hold time violation artifacts properly guarded against. Where a delay constraint is imposed on two clusters, but the two clusters are nevertheless assigned for implementation in the same FPGA due to strong connectivity between the clusters, delay elements are introduced into the data path to ensure that hold time violation artifacts are prevented. A system routing module then provides the interconnection for connecting the clocked and unclocked FPGAs of the emulation circuit.
- configuration module 407 is invoked to translate the data output of partition module 406 into programs for configurating the FPGAs and I/O connectors of the logic block module into the emulation circuit.
- configuration module 407 is interfaced with a software supplied by Xilinx Corporation to generate the configuration programs.
- the present invention is not so limited.
- the present invention is applicable to any array of programmable logic devices, including an array of programmable gate arrays, an array of one time programmable gate arrays, or an array of mask programmable gate arrays.
- the present invention is also applicable to an array of any programmable logic elements, including a semiconductor devices, as described above, a programmable printed circuit board assembly, or a programmable circuit block as part of a larger semiconductor device.
- the delay constraint in the above described embodiment can be achieved within the scope of the present invention by, instead of requiring different clock storage instances be implemented in separate FPGAs, configuring suitable interconnect delay elements in the data paths between the different clock storage instances in the same FPGA, thereby achieving sufficient delays to avoid the hold time violation artifact.
- Another variation within the scope of the present invention avoids hold time violation artifact due to data received from a primary I/O terminal over a data pod arriving at the data input terminal of a storage instance earlier than the clock signal clocking the storage instance.
- the present embodiment inserts delay elements to slow down the data path.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Food Science & Technology (AREA)
- Life Sciences & Earth Sciences (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/829,181 US5475830A (en) | 1992-01-31 | 1992-01-31 | Structure and method for providing a reconfigurable emulation circuit without hold time violations |
US829181 | 1992-01-31 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0559322A2 EP0559322A2 (en) | 1993-09-08 |
EP0559322A3 EP0559322A3 (sv) | 1995-06-14 |
EP0559322B1 true EP0559322B1 (en) | 2002-10-16 |
Family
ID=25253762
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP93300667A Expired - Lifetime EP0559322B1 (en) | 1992-01-31 | 1993-01-29 | Structure and method for providing a reconfigurable emulation circuit |
Country Status (4)
Country | Link |
---|---|
US (3) | US5475830A (sv) |
EP (1) | EP0559322B1 (sv) |
JP (1) | JPH06295319A (sv) |
DE (1) | DE69332391T2 (sv) |
Families Citing this family (146)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5596742A (en) * | 1993-04-02 | 1997-01-21 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
IL109921A (en) * | 1993-06-24 | 1997-09-30 | Quickturn Design Systems | Method and apparatus for configuring memory circuits |
US5680583A (en) * | 1994-02-16 | 1997-10-21 | Arkos Design, Inc. | Method and apparatus for a trace buffer in an emulation system |
US5761484A (en) * | 1994-04-01 | 1998-06-02 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
US5920712A (en) * | 1994-05-13 | 1999-07-06 | Quickturn Design Systems, Inc. | Emulation system having multiple emulator clock cycles per emulated clock cycle |
GB2292823B (en) * | 1994-08-26 | 1998-12-02 | Quickturn Design Systems Inc | Method for automatic clock qualifier selection in reprogrammable hardware emulation systems |
US5787299A (en) * | 1994-09-16 | 1998-07-28 | Philips Electronics North American Corporation | Pin selection system for microcontroller having multiplexer selects between address/data signals and special signals produced by special function device |
US5644498A (en) * | 1995-01-25 | 1997-07-01 | Lsi Logic Corporation | Timing shell generation through netlist reduction |
US5819065A (en) * | 1995-06-28 | 1998-10-06 | Quickturn Design Systems, Inc. | System and method for emulating memory |
US5923865A (en) * | 1995-06-28 | 1999-07-13 | Quickturn Design Systems, Inc. | Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing |
US6539509B1 (en) | 1996-05-22 | 2003-03-25 | Lsi Logic Corporation | Clock skew insensitive scan chain reordering |
US6212668B1 (en) | 1996-05-28 | 2001-04-03 | Altera Corporation | Gain matrix for hierarchical circuit partitioning |
US5822564A (en) * | 1996-06-03 | 1998-10-13 | Quickturn Design Systems, Inc. | Checkpointing in an emulation system |
US5886904A (en) * | 1996-09-23 | 1999-03-23 | Quickturn Design Systems, Inc. | Latch optimization in hardware logic emulation systems |
US6301694B1 (en) | 1996-09-25 | 2001-10-09 | Altera Corporation | Hierarchical circuit partitioning using sliding windows |
US5841967A (en) | 1996-10-17 | 1998-11-24 | Quickturn Design Systems, Inc. | Method and apparatus for design verification using emulation and simulation |
US6006022A (en) * | 1996-11-15 | 1999-12-21 | Microsystem Synthesis, Inc. | Cross-linked development and deployment apparatus and method |
US5761097A (en) * | 1996-12-16 | 1998-06-02 | Unisys Corporation | Logic timing analysis for multiple-clock designs |
US6141636A (en) * | 1997-03-31 | 2000-10-31 | Quickturn Design Systems, Inc. | Logic analysis subsystem in a time-sliced emulator |
US6185725B1 (en) * | 1997-04-11 | 2001-02-06 | Altera Corporation | Apparatus and method for partitioning logic into a programmable logic device |
US6421251B1 (en) | 1997-05-02 | 2002-07-16 | Axis Systems Inc | Array board interconnect system and method |
US6009256A (en) | 1997-05-02 | 1999-12-28 | Axis Systems, Inc. | Simulation/emulation system and method |
US6321366B1 (en) | 1997-05-02 | 2001-11-20 | Axis Systems, Inc. | Timing-insensitive glitch-free logic system and method |
US6026230A (en) | 1997-05-02 | 2000-02-15 | Axis Systems, Inc. | Memory simulation system and method |
US6134516A (en) | 1997-05-02 | 2000-10-17 | Axis Systems, Inc. | Simulation server system and method |
US6389379B1 (en) | 1997-05-02 | 2002-05-14 | Axis Systems, Inc. | Converification system and method |
US5787092A (en) * | 1997-05-27 | 1998-07-28 | Hewlett-Packard Co. | Test chip circuit for on-chip timing characterization |
US5960191A (en) | 1997-05-30 | 1999-09-28 | Quickturn Design Systems, Inc. | Emulation system with time-multiplexed interconnect |
TW371758B (en) | 1997-06-04 | 1999-10-11 | Siemens Ag | Method to optimize the signal-propagation-time in a reprogrammable switching circuit and reprogrammable switching circuit with program-code optimized in said signal-propagation time |
US5970240A (en) | 1997-06-25 | 1999-10-19 | Quickturn Design Systems, Inc. | Method and apparatus for configurable memory emulation |
US6120551A (en) * | 1997-09-29 | 2000-09-19 | Xilinx, Inc. | Hardwire logic device emulating an FPGA |
US6086629A (en) * | 1997-12-04 | 2000-07-11 | Xilinx, Inc. | Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers |
US6035117A (en) * | 1998-03-31 | 2000-03-07 | International Business Machines Corporation | Tightly coupled emulation processors |
US6353906B1 (en) | 1998-04-01 | 2002-03-05 | Lsi Logic Corporation | Testing synchronization circuitry using digital simulation |
US7389487B1 (en) | 1998-04-28 | 2008-06-17 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
US6502221B1 (en) | 1998-07-14 | 2002-12-31 | Nvidia Corporation | Prototype development system |
US6523155B1 (en) * | 1998-11-17 | 2003-02-18 | Jeffrey Joseph Ruedinger | Method for partitioning a netlist into multiple clock domains |
US6279146B1 (en) | 1999-01-06 | 2001-08-21 | Simutech Corporation | Apparatus and method for verifying a multi-component electronic design |
US6604230B1 (en) | 1999-02-09 | 2003-08-05 | The Governing Counsel Of The University Of Toronto | Multi-logic device systems having partial crossbar and direct interconnection architectures |
JP2000285144A (ja) * | 1999-03-29 | 2000-10-13 | Agency Of Ind Science & Technol | デジタル回路およびそのクロック信号調整方法 |
US6658581B1 (en) * | 1999-03-29 | 2003-12-02 | Agency Of Industrial Science & Technology | Timing adjustment of clock signals in a digital circuit |
US6446242B1 (en) * | 1999-04-02 | 2002-09-03 | Actel Corporation | Method and apparatus for storing a validation number in a field-programmable gate array |
US6519754B1 (en) * | 1999-05-17 | 2003-02-11 | Synplicity, Inc. | Methods and apparatuses for designing integrated circuits |
US6598191B1 (en) | 1999-11-23 | 2003-07-22 | Hewlett-Packard Development Companay, L.P. | Verification of asynchronous boundary behavior |
US7379859B2 (en) * | 2001-04-24 | 2008-05-27 | Mentor Graphics Corporation | Emulator with switching network connections |
US20030036895A1 (en) * | 2000-07-20 | 2003-02-20 | John Appleby-Alis | System, method and article of manufacture for software-designed internet reconfigurable hardware |
US6542844B1 (en) | 2000-08-02 | 2003-04-01 | International Business Machines Corporation | Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits |
US6937063B1 (en) * | 2000-09-02 | 2005-08-30 | Actel Corporation | Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array |
US6865527B2 (en) * | 2000-12-18 | 2005-03-08 | Hewlett-Packard Development Company, L.P. | Method and apparatus for computing data storage assignments |
US6842728B2 (en) * | 2001-03-12 | 2005-01-11 | International Business Machines Corporation | Time-multiplexing data between asynchronous clock domains within cycle simulation and emulation environments |
US6892174B1 (en) * | 2001-05-03 | 2005-05-10 | Advanced Micro Devices, Inc. | Arrangement for testing a network device by interfacing a low speed emulation system with high speed CPU |
US20020178427A1 (en) * | 2001-05-25 | 2002-11-28 | Cheng-Liang Ding | Method for improving timing behavior in a hardware logic emulation system |
US6658636B2 (en) * | 2001-07-09 | 2003-12-02 | Eric G. F. Hochapfel | Cross function block partitioning and placement of a circuit design onto reconfigurable logic devices |
US6556043B2 (en) | 2001-07-17 | 2003-04-29 | International Business Machines Corporation | Asynchronous latch design for field programmable gate arrays |
US6681377B2 (en) | 2001-09-18 | 2004-01-20 | Quickturn Design Systems, Inc. | Timing resynthesis in a multi-clock emulation system |
US6647540B2 (en) | 2001-11-08 | 2003-11-11 | Telefonaktiebolaget Lm Ericsson(Publ) | Method for reducing EMI and IR-drop in digital synchronous circuits |
US7328195B2 (en) | 2001-11-21 | 2008-02-05 | Ftl Systems, Inc. | Semi-automatic generation of behavior models continuous value using iterative probing of a device or existing component model |
US20030149962A1 (en) * | 2001-11-21 | 2003-08-07 | Willis John Christopher | Simulation of designs using programmable processors and electronically re-configurable logic arrays |
US6957358B1 (en) | 2002-01-28 | 2005-10-18 | Cisco Systems, Inc. | Scaling dynamic clock distribution for large service provider networks |
US6698005B2 (en) * | 2002-02-19 | 2004-02-24 | Telefonaktiebolaget L M Ericsson (Publ) | Min-time / race margins in digital circuits |
US6738961B2 (en) * | 2002-02-28 | 2004-05-18 | Hewlett-Packard Development Company, L.P. | Computer readable medium and a method for representing an electronic circuit as a routing-resource graph |
US20030188278A1 (en) * | 2002-03-26 | 2003-10-02 | Carrie Susan Elizabeth | Method and apparatus for accelerating digital logic simulations |
US7158925B2 (en) * | 2002-04-18 | 2007-01-02 | International Business Machines Corporation | Facilitating simulation of a model within a distributed environment |
US7124071B2 (en) * | 2002-04-18 | 2006-10-17 | International Business Machines Corporation | Partitioning a model into a plurality of independent partitions to be processed within a distributed environment |
GB2388501A (en) * | 2002-05-09 | 2003-11-12 | Sony Uk Ltd | Data packet and clock signal transmission via different paths |
US6745374B2 (en) * | 2002-06-10 | 2004-06-01 | Sun Microsystems, Inc. | Algorithms for determining path coverages and activity |
US6789244B1 (en) * | 2002-08-08 | 2004-09-07 | Xilinx, Inc. | Placement of clock objects under constraints |
US20040115995A1 (en) * | 2002-11-25 | 2004-06-17 | Sanders Samuel Sidney | Circuit array module |
US7260794B2 (en) * | 2002-12-20 | 2007-08-21 | Quickturn Design Systems, Inc. | Logic multiprocessor for FPGA implementation |
US7440884B2 (en) * | 2003-01-23 | 2008-10-21 | Quickturn Design Systems, Inc. | Memory rewind and reconstruction for hardware emulator |
EP1450278B1 (en) | 2003-01-23 | 2013-04-24 | Cadence Design Systems, Inc. | Methods and apparatus for verifying the operation of a circuit design |
US7096442B2 (en) * | 2003-07-10 | 2006-08-22 | Lsi Logic Corporation | Optimizing IC clock structures by minimizing clock uncertainty |
US7257800B1 (en) * | 2003-07-11 | 2007-08-14 | Altera Corporation | Method and apparatus for performing logic replication in field programmable gate arrays |
US6952813B1 (en) | 2003-07-30 | 2005-10-04 | Xilinx, Inc. | Method and apparatus for selecting programmable interconnects to reduce clock skew |
JP2005093563A (ja) * | 2003-09-12 | 2005-04-07 | Matsushita Electric Ind Co Ltd | 半導体集積回路およびその設計方法 |
US7111262B1 (en) | 2003-09-30 | 2006-09-19 | Xilinx, Inc. | Circuit clustering during placement |
US7003746B2 (en) * | 2003-10-14 | 2006-02-21 | Hyduke Stanley M | Method and apparatus for accelerating the verification of application specific integrated circuit designs |
US20050091622A1 (en) * | 2003-10-28 | 2005-04-28 | Pappu Krishna K. | Method of grouping scan flops based on clock domains for scan testing |
US20050097485A1 (en) * | 2003-10-29 | 2005-05-05 | Guenthner Russell W. | Method for improving performance of critical path in field programmable gate arrays |
US7310728B2 (en) * | 2003-11-24 | 2007-12-18 | Itt Manufacturing Enterprises, Inc. | Method of implementing a high-speed header bypass function |
US7020864B1 (en) * | 2003-11-24 | 2006-03-28 | Altera Corporation | Optimized technology mapping techniques for programmable circuits |
US7308664B1 (en) | 2004-02-09 | 2007-12-11 | Altera Corporation | Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing |
EP1742365A4 (en) * | 2004-03-30 | 2007-10-10 | Nec Corp | CIRCUIT CHECK DEVICE, CIRCUIT PROCEDURE AND SIGNAL DISTRIBUTION METHOD THEREFOR |
US7180324B2 (en) | 2004-05-28 | 2007-02-20 | Altera Corporation | Redundancy structures and methods in a programmable logic device |
US7738399B2 (en) * | 2004-06-01 | 2010-06-15 | Quickturn Design Systems Inc. | System and method for identifying target systems |
US7738398B2 (en) * | 2004-06-01 | 2010-06-15 | Quickturn Design Systems, Inc. | System and method for configuring communication systems |
US7739093B2 (en) * | 2004-06-01 | 2010-06-15 | Quickturn Design System, Inc. | Method of visualization in processor based emulation system |
US7440866B2 (en) * | 2004-06-01 | 2008-10-21 | Quickturn Design Systems Inc. | System and method for validating an input/output voltage of a target system |
US7606697B2 (en) * | 2004-06-01 | 2009-10-20 | Quickturn Design Systems, Inc. | System and method for resolving artifacts in differential signals |
US7721036B2 (en) * | 2004-06-01 | 2010-05-18 | Quickturn Design Systems Inc. | System and method for providing flexible signal routing and timing |
US7640155B2 (en) * | 2004-06-01 | 2009-12-29 | Quickturn Design Systems, Inc. | Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications |
US7342415B2 (en) | 2004-11-08 | 2008-03-11 | Tabula, Inc. | Configurable IC with interconnect circuits that also perform storage operations |
US7428721B2 (en) | 2004-12-01 | 2008-09-23 | Tabula, Inc. | Operational cycle assignment in a configurable IC |
US7236009B1 (en) | 2004-12-01 | 2007-06-26 | Andre Rohe | Operational time extension |
US7496879B2 (en) * | 2004-12-01 | 2009-02-24 | Tabula, Inc. | Concurrent optimization of physical design and operational cycle assignment |
US7353162B2 (en) * | 2005-02-11 | 2008-04-01 | S2C, Inc. | Scalable reconfigurable prototyping system and method |
US8145469B2 (en) * | 2005-04-06 | 2012-03-27 | Quickturn Design Systems, Inc. | System and method for providing compact mapping between dissimilar memory systems |
US7577558B2 (en) * | 2005-04-06 | 2009-08-18 | Quickturn Design Systems, Inc. | System and method for providing compact mapping between dissimilar memory systems |
US7818705B1 (en) | 2005-04-08 | 2010-10-19 | Altera Corporation | Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew |
US20060247909A1 (en) * | 2005-04-27 | 2006-11-02 | Desai Madhav P | System and method for emulating a logic circuit design using programmable logic devices |
WO2006133149A2 (en) | 2005-06-03 | 2006-12-14 | Quickturn Design Systems, Inc. | Method for analyzing power consumption of circuit design using hardware emulation |
US7367007B1 (en) | 2005-06-29 | 2008-04-29 | Xilinx, Inc. | Method of routing a design to increase the quality of the design |
US7512850B2 (en) | 2005-07-15 | 2009-03-31 | Tabula, Inc. | Checkpointing user design states in a configurable IC |
US7992121B2 (en) * | 2005-09-30 | 2011-08-02 | Cadence Design Systems, Inc. | System and method for I/O synthesis and for assigning I/O to programmable devices |
EP1933463A1 (en) * | 2005-10-05 | 2008-06-18 | Matsushita Electric Industrial Co., Ltd. | Reconfigurable semiconductor integrated circuit and its processing allocation method |
US7372297B1 (en) | 2005-11-07 | 2008-05-13 | Tabula Inc. | Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources |
US7679401B1 (en) | 2005-12-01 | 2010-03-16 | Tabula, Inc. | User registers implemented with routing circuits in a configurable IC |
US7739552B2 (en) * | 2006-02-17 | 2010-06-15 | Lanning Eric J | Tapping a memory card |
US7555424B2 (en) | 2006-03-16 | 2009-06-30 | Quickturn Design Systems, Inc. | Method and apparatus for rewinding emulated memory circuits |
US7590957B2 (en) * | 2006-08-24 | 2009-09-15 | Lsi Corporation | Method and apparatus for fixing best case hold time violations in an integrated circuit design |
EP2597776A3 (en) | 2007-03-20 | 2014-08-20 | Tabula, Inc. | Configurable IC having a routing fabric with storage elements |
US7895026B1 (en) * | 2007-08-16 | 2011-02-22 | Xilinx, Inc. | Multi-rate simulation scheduler for synchronous digital circuits in a high level modeling system |
US8205182B1 (en) * | 2007-08-22 | 2012-06-19 | Cadence Design Systems, Inc. | Automatic synthesis of clock distribution networks |
US7825685B2 (en) | 2007-09-06 | 2010-11-02 | Tabula, Inc. | Configuration context switcher with a clocked storage element |
US8990651B2 (en) * | 2007-09-19 | 2015-03-24 | Tabula, Inc. | Integrated circuit (IC) with primary and secondary networks and device containing such an IC |
US8352235B1 (en) | 2007-10-31 | 2013-01-08 | Cadence Design Systems, Inc. | Emulation of power shutoff behavior for integrated circuits |
US8863067B1 (en) | 2008-02-06 | 2014-10-14 | Tabula, Inc. | Sequential delay analysis by placement engines |
US8108194B2 (en) | 2008-04-25 | 2012-01-31 | Cadence Design Systems, Inc. | Peak power detection in digital designs using emulation systems |
US8166435B2 (en) | 2008-06-26 | 2012-04-24 | Tabula, Inc. | Timing operations in an IC with configurable circuits |
US8525548B2 (en) | 2008-08-04 | 2013-09-03 | Tabula, Inc. | Trigger circuits and event counters for an IC |
JP4706738B2 (ja) * | 2008-08-20 | 2011-06-22 | 日本電気株式会社 | 遅延解析装置、遅延解析方法、及びプログラム |
US9015026B2 (en) * | 2009-06-12 | 2015-04-21 | Cadence Design Systems, Inc. | System and method incorporating an arithmetic logic unit for emulation |
US9429983B1 (en) | 2013-09-12 | 2016-08-30 | Advanced Processor Architectures, Llc | System clock distribution in a distributed computing environment |
US11042211B2 (en) | 2009-08-07 | 2021-06-22 | Advanced Processor Architectures, Llc | Serially connected computing nodes in a distributed computing system |
US9645603B1 (en) | 2013-09-12 | 2017-05-09 | Advanced Processor Architectures, Llc | System clock distribution in a distributed computing environment |
US8675371B2 (en) | 2009-08-07 | 2014-03-18 | Advanced Processor Architectures, Llc | Distributed computing |
US8473661B2 (en) * | 2009-08-14 | 2013-06-25 | Cadence Design Systems, Inc. | System and method for providing multi-process protection using direct memory mapped control registers |
US20120296623A1 (en) * | 2011-05-20 | 2012-11-22 | Grayskytech Llc | Machine transport and execution of logic simulation |
US8959010B1 (en) | 2011-12-08 | 2015-02-17 | Cadence Design Systems, Inc. | Emulation system with improved reliability of interconnect and a method for programming such interconnect |
US8743735B1 (en) | 2012-01-18 | 2014-06-03 | Cadence Design Systems, Inc. | Emulation system for verifying a network device |
US8595683B1 (en) | 2012-04-12 | 2013-11-26 | Cadence Design Systems, Inc. | Generating user clocks for a prototyping environment |
US9058070B2 (en) * | 2012-05-30 | 2015-06-16 | Utah State University | Predicting timing violations |
US8549454B1 (en) * | 2012-07-20 | 2013-10-01 | Xilinx, Inc. | System and method for automated configuration of design constraints |
US9330220B1 (en) * | 2014-08-25 | 2016-05-03 | Xilinx, Inc. | Clock region partitioning and clock routing |
US9292639B1 (en) | 2014-10-30 | 2016-03-22 | Cadence Design Systems Inc. | Method and system for providing additional look-up tables |
US9379846B1 (en) | 2014-12-19 | 2016-06-28 | Cadence Design Systems, Inc. | System and method of encoding in a serializer/deserializer |
US9647688B1 (en) | 2014-12-19 | 2017-05-09 | Cadence Design Systems, Inc. | System and method of encoding in a serializer/deserializer |
US9405877B1 (en) | 2014-12-22 | 2016-08-02 | Cadence Design Systems, Inc. | System and method of fast phase aligned local generation of clocks on multiple FPGA system |
US9495492B1 (en) | 2015-01-05 | 2016-11-15 | Cadence Design Systems, Inc. | Implementing synchronous triggers for waveform capture in an FPGA prototyping system |
US9294094B1 (en) | 2015-01-08 | 2016-03-22 | Cadence Design Systems, Inc. | Method and apparatus for fast low skew phase generation for multiplexing signals on a multi-FPGA prototyping system |
US9702933B1 (en) | 2015-10-22 | 2017-07-11 | Cadence Design Systems, Inc. | System and method for concurrent interconnection diagnostics field |
US9697324B1 (en) | 2015-11-05 | 2017-07-04 | Cadence Design Systems, Inc. | System for concurrent target diagnostics field |
US10176100B1 (en) | 2015-12-21 | 2019-01-08 | Cadence Design Systems, Inc. | Cache coherency process |
US10169120B2 (en) * | 2016-06-24 | 2019-01-01 | International Business Machines Corporation | Redundant software stack |
US10963001B1 (en) | 2017-04-18 | 2021-03-30 | Amazon Technologies, Inc. | Client configurable hardware logic and corresponding hardware clock metadata |
CN116052531B (zh) * | 2022-05-27 | 2023-10-20 | 荣耀终端有限公司 | 显示基板及显示装置 |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4020469A (en) * | 1975-04-09 | 1977-04-26 | Frank Manning | Programmable arrays |
US4306286A (en) * | 1979-06-29 | 1981-12-15 | International Business Machines Corporation | Logic simulation machine |
US4488354A (en) * | 1981-11-16 | 1984-12-18 | Ncr Corporation | Method for simulating and testing an integrated circuit chip |
JPS58147236A (ja) * | 1982-02-26 | 1983-09-02 | Nec Corp | ダイナミックpla |
JPS58147237A (ja) * | 1982-02-26 | 1983-09-02 | Nec Corp | ダイナミツクpla |
US4503386A (en) * | 1982-04-20 | 1985-03-05 | International Business Machines Corporation | Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks |
JPS58205870A (ja) * | 1982-05-26 | 1983-11-30 | Nippon Telegr & Teleph Corp <Ntt> | 論理回路シミユレ−シヨン装置 |
US4577276A (en) * | 1983-09-12 | 1986-03-18 | At&T Bell Laboratories | Placement of components on circuit substrates |
US4642487A (en) * | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
JPS61154251A (ja) * | 1984-12-26 | 1986-07-12 | Nec Corp | モ−ニングコ−ル設定方式 |
US4697241A (en) * | 1985-03-01 | 1987-09-29 | Simulog, Inc. | Hardware logic simulator |
US4937827A (en) * | 1985-03-01 | 1990-06-26 | Mentor Graphics Corporation | Circuit verification accessory |
JPS61199166A (ja) * | 1985-03-01 | 1986-09-03 | Nec Corp | 配線経路探索装置 |
JPH0668756B2 (ja) * | 1985-04-19 | 1994-08-31 | 株式会社日立製作所 | 回路自動変換方法 |
JP2565497B2 (ja) * | 1985-09-11 | 1996-12-18 | ピルキントン マイクロ−エレクトロニクス リミテツド | 半導体集積回路 |
JPS6274158A (ja) * | 1985-09-27 | 1987-04-04 | Hitachi Ltd | 回路変換方式 |
US4744084A (en) * | 1986-02-27 | 1988-05-10 | Mentor Graphics Corporation | Hardware modeling system and method for simulating portions of electrical circuits |
JPH0770598B2 (ja) * | 1986-03-20 | 1995-07-31 | 株式会社東芝 | 半導体集積回路装置の配線方法 |
US4777606A (en) * | 1986-06-05 | 1988-10-11 | Northern Telecom Limited | Method for deriving an interconnection route between elements in an interconnection medium |
US4758745B1 (en) * | 1986-09-19 | 1994-11-15 | Actel Corp | User programmable integrated circuit interconnect architecture and test method |
US4965739A (en) * | 1987-03-26 | 1990-10-23 | Vlsi Technology, Inc. | Machine process for routing interconnections from one module to another module and for positioning said two modules after said modules are interconnected |
US4908772A (en) * | 1987-03-30 | 1990-03-13 | Bell Telephone Laboratories | Integrated circuits with component placement by rectilinear partitioning |
US5093920A (en) * | 1987-06-25 | 1992-03-03 | At&T Bell Laboratories | Programmable processing elements interconnected by a communication network including field operation unit for performing field operations |
JPH01154251A (ja) * | 1987-12-10 | 1989-06-16 | Fujitsu Ltd | 諭理回路シュミレータ |
US4914612A (en) * | 1988-03-31 | 1990-04-03 | International Business Machines Corporation | Massively distributed simulation engine |
US4811364A (en) * | 1988-04-01 | 1989-03-07 | Digital Equipment Corporation | Method and apparatus for stabilized data transmission |
US5003487A (en) * | 1988-06-28 | 1991-03-26 | International Business Machines Corporation | Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis |
US5036473A (en) * | 1988-10-05 | 1991-07-30 | Mentor Graphics Corporation | Method of using electronically reconfigurable logic circuits |
US5109353A (en) * | 1988-12-02 | 1992-04-28 | Quickturn Systems, Incorporated | Apparatus for emulation of electronic hardware system |
US5140526A (en) * | 1989-01-06 | 1992-08-18 | Minc Incorporated | Partitioning of Boolean logic equations into physical logic devices |
US5172011A (en) * | 1989-06-30 | 1992-12-15 | Digital Equipment Corporation | Latch circuit and method with complementary clocking and level sensitive scan capability |
US5259006A (en) * | 1990-04-18 | 1993-11-02 | Quickturn Systems, Incorporated | Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like |
EP0453171A3 (en) * | 1990-04-18 | 1992-11-19 | Quickturn Systems Inc | Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like |
GB2292823B (en) * | 1994-08-26 | 1998-12-02 | Quickturn Design Systems Inc | Method for automatic clock qualifier selection in reprogrammable hardware emulation systems |
-
1992
- 1992-01-31 US US07/829,181 patent/US5475830A/en not_active Expired - Lifetime
-
1993
- 1993-01-29 EP EP93300667A patent/EP0559322B1/en not_active Expired - Lifetime
- 1993-01-29 DE DE69332391T patent/DE69332391T2/de not_active Expired - Lifetime
- 1993-02-01 JP JP5036118A patent/JPH06295319A/ja active Pending
-
1995
- 1995-06-07 US US08/472,531 patent/US5649167A/en not_active Expired - Lifetime
-
1997
- 1997-07-11 US US08/893,412 patent/US5835751A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69332391T2 (de) | 2003-06-18 |
US5835751A (en) | 1998-11-10 |
EP0559322A3 (sv) | 1995-06-14 |
US5649167A (en) | 1997-07-15 |
JPH06295319A (ja) | 1994-10-21 |
US5475830A (en) | 1995-12-12 |
DE69332391D1 (de) | 2002-11-21 |
EP0559322A2 (en) | 1993-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0559322B1 (en) | Structure and method for providing a reconfigurable emulation circuit | |
US6009256A (en) | Simulation/emulation system and method | |
US6058492A (en) | Method and apparatus for design verification using emulation and simulation | |
Walters | Computer-aided prototyping for ASIC-based systems | |
US6810442B1 (en) | Memory mapping system and method | |
JP3162681B2 (ja) | 電気的に再構成可能なゲートアレイロジックを用いる方法及び、これによって構成される装置 | |
US5734581A (en) | Method for implementing tri-state nets in a logic emulation system | |
US6389379B1 (en) | Converification system and method | |
JP4125675B2 (ja) | タイミングに鈍感なグリッチのない論理システムおよび方法 | |
EP0985175B1 (en) | Distributed logic analyzer for use in a hardware logic emulation system | |
US5854752A (en) | Circuit partitioning technique for use with multiplexed inter-connections | |
US7512728B2 (en) | Inter-chip communication system | |
WO2003077078A2 (en) | Hub array system and method | |
CA2291738A1 (en) | Emulation system with time-multiplexed interconnect | |
JP2731021B2 (ja) | Asic開発方法とasicエミュレータと集積回路の設計開発方法と単一集積回路の部分開発方法 | |
KR100928134B1 (ko) | 주문형 vcd 시스템 및 방법 | |
US20030188278A1 (en) | Method and apparatus for accelerating digital logic simulations | |
US20050091621A1 (en) | Methods for designing a circuit | |
JP3182244B2 (ja) | 半導体集積回路における信号伝播遅延時間の最適化方法 | |
KR20000038391A (ko) | 에프피쥐에이 애뮬레이터를 이용한 멀티 에프피쥐에이 검증방법 | |
KR20040046284A (ko) | 클럭트리 합성방법 및 클럭트리 합성효과의 예측방법 | |
Seals et al. | Field programmable gate arrays (FPGAs) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IT NL SE |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB IT NL SE |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: QUICKTURN DESIGN SYSTEMS, INC. |
|
17P | Request for examination filed |
Effective date: 19950918 |
|
17Q | First examination report despatched |
Effective date: 19990714 |
|
GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
RIC1 | Information provided on ipc code assigned before grant |
Free format text: 7G 06F 17/50 A, 7G 06F 1/10 B |
|
GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IT NL SE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRE;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.SCRIBED TIME-LIMIT Effective date: 20021016 Ref country code: FR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20021016 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REF | Corresponds to: |
Ref document number: 69332391 Country of ref document: DE Date of ref document: 20021121 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: SE Payment date: 20030107 Year of fee payment: 11 Ref country code: FR Payment date: 20030107 Year of fee payment: 11 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20030116 |
|
EN | Fr: translation not filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20030717 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20120127 Year of fee payment: 20 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20120126 Year of fee payment: 20 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: NL Payment date: 20120130 Year of fee payment: 20 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R071 Ref document number: 69332391 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: V4 Effective date: 20130129 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: PE20 Expiry date: 20130128 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION Effective date: 20130128 Ref country code: DE Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION Effective date: 20130130 |