EP0534030B1 - Dispositif du transfert de trâme pour un réseau de transmission utilisant des trâmes de format determiné - Google Patents

Dispositif du transfert de trâme pour un réseau de transmission utilisant des trâmes de format determiné Download PDF

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Publication number
EP0534030B1
EP0534030B1 EP91480152A EP91480152A EP0534030B1 EP 0534030 B1 EP0534030 B1 EP 0534030B1 EP 91480152 A EP91480152 A EP 91480152A EP 91480152 A EP91480152 A EP 91480152A EP 0534030 B1 EP0534030 B1 EP 0534030B1
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EP
European Patent Office
Prior art keywords
fifo
bit
synchronization
network
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP91480152A
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German (de)
English (en)
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EP0534030A1 (fr
Inventor
Philippe Borgnis
Jacques Cresp
Robert Moreau
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International Business Machines Corp
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International Business Machines Corp
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Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to DE69120816T priority Critical patent/DE69120816D1/de
Priority to EP91480152A priority patent/EP0534030B1/fr
Priority to US07/826,336 priority patent/US5263028A/en
Priority to JP4198581A priority patent/JPH05219046A/ja
Publication of EP0534030A1 publication Critical patent/EP0534030A1/fr
Application granted granted Critical
Publication of EP0534030B1 publication Critical patent/EP0534030B1/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/12—Arrangements providing for calling or supervisory signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
    • H04Q11/0414—Details

Definitions

  • This invention deals with digital transmission networks and more particularly with a mechanism for monitoring and synchronizing fixed format frame transfers within a network node.
  • TDM Time Division Multiplex
  • the deserializing and correlative serializing operations are performed into a network interface, and then the data transfers to and from memory are micro-processor controlled. Obviously those data transfers have to be properly synchronized.
  • a synchronization or clock information is derived from a slot content within each node incoming frame. Said clock is, in turn, used to synchronize outgoing frames.
  • data transfers between network interface adapter and memory are not fully monitored. Should a failure occur in the transfer flow, the system may not be aware of it. Consequently, for instance, same byte may be sent repetitively without any error indication being provided by the network interface.
  • One object of this invention is to provide a mechanism with the capability of continuously monitoring network node frame synchronization .
  • Another object of this invention is to provide frame data transfer synchronizing mechanism enabling monitoring data transfers in both directions within a network node as well as providing means for on-line diagnostic.
  • an object of this invention is to provide a frame transfer mechanism for a processor controlled network node connected to network link, wherein fixed length data frames including a fixed number of slots are received as input frames including individual slot contents to be transferred and stored into a memory for later transmission within output frames over the network link, said frame transfer mechanism including :
  • Figure 1 shows a schematic representation of the transfer mechanism.
  • Figure 2 is an architecture of the device of this invention.
  • Figure 3 is a schematic representation of a sequence of data frames to be used in this invention.
  • Figure 4 is a logic device for the invention.
  • FIGS 5-7 are time diagrams for the invention.
  • Figure 1 shows a schematic representation of the transfer mechanism to be considered herein.
  • the mechanism is meant for the transfer of fixed format frames contents vehiculated over the network lines to and from memory 10.
  • a trunk interface facility 12 is connected to the communication line for deserializing each input frame slot contents (eight bits) and serializing data by inserting into output frames.
  • the transfer mechanism 14 cooperates with a microprocessor and with the trunk interface facility to control data transfers to and from the memory wherein said data are temporarily stored.
  • the ultimate goal of the transfer mechanism is to assure a correct synchronism, in term of received slot assigned numbers, storage of the input data flow into the memory, as well as a correct transmission to the line of the output data taken from the memory.
  • FIG. 2 Represented in figure 2 is a detailed architecture of the frame transfer mechanism including this invention.
  • Two data flows have to be considered.
  • a deserializer within the network adapter (20) transforms the received data into eight-bit words. Said words are forwarded through an eight-bit data bus (BUS R), to a shift register FIFO IN 22.
  • the FIFO IN register is made to include a 9th bit position to be used for a synchronization bit.
  • the data bits are forwarded to memory 10 under the control of microprocessor 23.
  • the synchronization bit line is also connected from FIFO IN 22 to the microprocessor 23.
  • the synchronization logic device 25 is also provided a timing command from a timing device 26, which also provides a write command to register 22. Both, write command to register 24 and read command to register 22 are provided via the microprocessor 23.
  • a network synchronization (NET synchronization)command is provided, via network adapter 20, to both synchronization logic device 25 and microprocessor 23. It should be already noted that, in fact, the synchronization bit (9th bit) is provided to FIFO-OUT and fedback therefrom to FIFO-IN.
  • both FIFO's organization reflect the image of the frames in that they both include thirty two words positions, each word including eight bits code.
  • the word positions are numbered zero to thirty one, as are the received and transmitted frames slots.
  • the network synchronization time information is conventionally derived from detecting the occurrence of a received frame slot zero.
  • a flag bit is written by the microprocessor into the 9th bit position of slot zero of FIFO-OUT register. As represented in figure 2, this flag bit position is looped-back into FIFO-IN 9th bit position. The flag is therefore fedback into FIFO-IN shift register.
  • a detailed description of synchronization logic device is shown in figure 4.
  • a first flip-flop 40 acting as 9th bit detect is connected to the 9th bit output position of FIFO-OUT, and to an inverter, connected in turn to the synchronization logic device output.
  • One output of 9th bit detect circuit 40 is fed into a so-called "lock" flip-flop 42.
  • the output of device 42 is ANDed in 44 with the clock data provided by the tuning device 26.
  • the other output of 9th bit detect device 40 is fed into a so-called search flip-flop 46.
  • the output of 46 i.e. out of synchronization
  • the outputs of both AND devices 44 and 48 are ORed in 49 to provide the Advance Clock indication used to read FIFO-OUT.
  • the overall synchronization process shall include a start-up process initializing the FIFO at power-on. This is achieved to clear any current random content of FIFO's at power-on time, and to correctly position and mark the first slot before any data reception or transmission starts. To that end, a series of reading and writing operations are executed. It is more convenient to start with the synchronization of the transmit section. The memory and the microprocessor system shall then be ready and locked to store the received data at the right place.
  • a search process starts with an accelerated clock (see CLKOUT signal) acting as "advance clock” data , four times faster than the basic clock used to control the FIFO' s (see CLKIN at 250KHz every 4ms). This enables speeding-up the 9th bit (flag) search within FIFO-OUT.
  • the system enters into WAIT STATE, the advance clock (CLOCK OUT) is stopped.
  • a DETECT signal is set-up (3), waiting for the network synchronization signal trailing edge occurrence (5).
  • WAIT STATE is started when the flag has been detected and stays as long as the trailing edge (5) of the synchronization signal is not present.
  • the maximum time the WAIT STATE can last is 125 microseconds, that is in the case the 9th bit flag was detected just after occurrence of a synchronization-signal trailing edge.
  • the represented WAIT STATE is very short due to a quite immediate apparition of the synchronization signal trailing edge (5).
  • the WAIT STATE is only valid during the synchronization phase. Should a WAIT STATE situation occur during normal operation, an error or "out of synchronization" data will be reported to the micro-processor 23.
  • FIG. 6 Represented in figure 6 is a time diagram of said NORMAL SYNCHRONIZED PROCESS.
  • the occurrence of this state of operation means that the synchronization is fully acquired and the FIFO's are in synchronism with the network.
  • the system has, now, only to check the just in time repetition of the 9th bit (flag) detection, in coincidence with the network synchronization trailing edge signal. Should this be lost during normal operation, an error (“out of synchronization”) indication is reported to the microprocessor.
  • the error denoting "out of synchronization" alerts the microprocessor in two different occasions. In normal operation, while the synchronization signal is not in time with the flag bit. But also during the initial synchronization process, in which case the error indication will not be active to avoid disturbing the synchronizing process in synchronization research process step.
  • the system of this invention suits particularly well to on-line diagnostics of no failure, through a wrap-test operated over the 9th bit flag.
  • the time space between two consecutive flags is iddle in the FIFO's operation.
  • the microprocessor controlled system may then use the 9th bit flags. Every 20 ms, a random data pattern is inserted in place of the 9th bit.
  • This pattern is propagated during normal synchronized process throughout FIFO-OUT and fed back into FIFO-IN 9th bit position via the on-line diagnostic link (see figure 2 ON LINE DIAG).
  • the test pattern is read out of FIFO-IN by the micro-processor and checked for matching with expected pattern.
  • the tested path may also include the memory by reading the test pattern in and out of memory 20. This enables not only checking the complete path operation but also checking memory operation to some extent.
  • the on-line diagnostics or wrap test may fail to operate if FIFO's are frozen while the pointers are running. This drawback is taken care off herein without any increase in complexity being required.
  • the test pattern is made to vary between consecutive 9th bit flags, while being monitored and controlled by the processor 23.
  • FIFO FIFO-like shift register means

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Claims (6)

  1. Mécanisme de transfert de trame destiné à un noeud de réseau commandé par un processeur relié à une liaison de réseau, dans lequel des trames de données de longueur fixe comprenant un nombre fixe de tranches sont reçues en tant que trames d'entrée comprenant un contenu de tranches individuelles à transférer et à mémoriser dans une mémoire pour une transmission ultérieure à l'intérieur de trames de sortie sur la liaison de réseau, ledit mécanisme de transfert de trame comprenant :
    - un adaptateur de réseau (20) comprenant un moyen de désérialisation/sérialisation relié à ladite liaison afin de désérialiser le contenu des tranches de trame reçues à transférer dans la mémoire, ou afin de sérialiser les données procurées à la mémoire qui doivent être transmises sur la liaison,
    - des moyens de registres à décalage du type FIFO (premier entré premier sorti) reliés entre ladite mémoire et ledit moyen de sérialisation/désérialisation en tant que moyen FIFO-OUT (24) et FIFO-IN (22), respectivement, lesdits FIFO comprenant une position de bit supplémentaire par comparaison à la longueur définie de tranche de trame,
    - des moyens de décalage destinés à décaler le contenu des FIFO, les moyens répondant à une trame reçue sur la liaison afin d'obtenir un signal de synchronisation de réseau à partir de celle-ci, ledit mécanisme étant caractérisé en ce qu'il comprend :
    - des moyens (23) destinés à insérer un bit d'indicateur de synchronisation dans une position de bit supplémentaire prédéfinie de FIFO-OUT,
    - un moyen de logique de synchronisation (25) répondant à la simultanéité de ladite détection de bit d'indicateur FIFO-OUT et dudit signal de synchronisation de réseau afin d'obtenir à partir de celle-ci une indication d'une opération de mécanisme de transfert synchronisé normale.
  2. Mécanisme de transfert de trame selon la revendication 1, dans lequel lesdites fonctions des FIFO sont obtenues par l'intermédiaire de positions en mémoire vive sur lesquelles pointent des pointeurs de décalage.
  3. Mécanisme de transfert de trame selon la revendication 1 ou la revendication 2, comprenant en outre des moyens destinés à accélérer les opérations de décalage de FIFO-OUT à l'instant de la mise sous tension du noeud jusqu'à ce que ledit moyen de logique de synchronisation détecte ledit bit d'indicateur de FIFO-OUT.
  4. Mécanisme de transfert de trame selon la revendication 3, dans lequel ledit moyen de logique de synchronisation comprend un moyen d'établissement de signal WAIT STATE répondant, lors de la mise sous tension, à ladite détection d'indicateur FIFO-OUT afin de surveiller l'apparition du signal de synchronisation de réseau et d'engendrer un signal d'erreur de sortie de synchronisation si ladite synchronisation de réseau ne se produisait pas après un retard de temps prédéfini.
  5. Mécanisme de transfert de trame selon la revendication 4, comprenant en outre un moyen destiné à envoyer en retour la position de sortie du bit supplémentaire de FIFO-OUT dans la position d'entrée de bit supplémentaire de FIFO-IN afin de permettre la surveillance et la commande de la synchronisation adéquate complète des FIFO vers et depuis la mémoire, par l'intermédiaire de la détection d'indicateur.
  6. Mécanisme de transfert de trame selon la revendication 5, comprenant en outre un moyen destiné à insérer une séquence de test entre des indicateurs dans lesdites positions de bits supplémentaires de FIFO-OUT pour effectuer des opérations de test de rebouclage des FIFO vers et depuis la mémoire.
EP91480152A 1991-09-26 1991-09-26 Dispositif du transfert de trâme pour un réseau de transmission utilisant des trâmes de format determiné Expired - Lifetime EP0534030B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE69120816T DE69120816D1 (de) 1991-09-26 1991-09-26 Rahmenübertragungsanordnung in einem mit vorgegebenem Rahmenformat arbeitenden Übertragungsnetz
EP91480152A EP0534030B1 (fr) 1991-09-26 1991-09-26 Dispositif du transfert de trâme pour un réseau de transmission utilisant des trâmes de format determiné
US07/826,336 US5263028A (en) 1991-09-26 1992-01-27 Frame transfer device for a fixed format frame transmission network
JP4198581A JPH05219046A (ja) 1991-09-26 1992-07-24 固定フォーマットフレーム伝送ネットワークのためのフレーム伝送デバイス

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP91480152A EP0534030B1 (fr) 1991-09-26 1991-09-26 Dispositif du transfert de trâme pour un réseau de transmission utilisant des trâmes de format determiné

Publications (2)

Publication Number Publication Date
EP0534030A1 EP0534030A1 (fr) 1993-03-31
EP0534030B1 true EP0534030B1 (fr) 1996-07-10

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EP91480152A Expired - Lifetime EP0534030B1 (fr) 1991-09-26 1991-09-26 Dispositif du transfert de trâme pour un réseau de transmission utilisant des trâmes de format determiné

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US (1) US5263028A (fr)
EP (1) EP0534030B1 (fr)
JP (1) JPH05219046A (fr)
DE (1) DE69120816D1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2266979A (en) * 1992-05-12 1993-11-17 Apple Computer Phase register for synchronization of multiple signal processors.
US5586332A (en) * 1993-03-24 1996-12-17 Intel Corporation Power management for low power processors through the use of auto clock-throttling
US5528579A (en) * 1993-06-11 1996-06-18 Adc Telecommunications, Inc. Added bit signalling in a telecommunications system
DE69522595T2 (de) * 1994-02-04 2002-07-11 Intel Corp Verfahren und Vorrichtung zur Stromverbrauchssteuerung in einem Rechnersystem
DE19545675A1 (de) * 1995-12-07 1997-06-12 Sel Alcatel Ag Synchrones digitales Übertragungssystem
US5892768A (en) * 1996-09-12 1999-04-06 Etherwan System, Inc. 10/100-base ethernet to T1/E1 HDSL converter and method of operation
US7046625B1 (en) * 1998-09-30 2006-05-16 Stmicroelectronics, Inc. Method and system for routing network-based data using frame address notification
US6801539B1 (en) 2000-06-26 2004-10-05 Adtran, Inc. Serialized HDSL multiplexer - demultiplexer protocol
US7480840B2 (en) * 2004-10-12 2009-01-20 International Business Machines Corporation Apparatus, system, and method for facilitating port testing of a multi-port host adapter

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
IT1118570B (it) * 1979-04-19 1986-03-03 Cselt Centro Studi Lab Telecom Sistema per lo scambio di messaggi tra microilaboratori collegati da un mezzo trasmissivo sincrono
US4653085A (en) * 1984-09-27 1987-03-24 At&T Company Telephone switching system adjunct call processing arrangement
NZ220548A (en) * 1986-06-18 1990-05-28 Fujitsu Ltd Tdm frame synchronising circuit
JPS63169840A (ja) * 1987-01-08 1988-07-13 Ricoh Co Ltd フレ−ム同期装置
ATE96599T1 (de) * 1987-04-02 1993-11-15 Advanced Micro Devices Inc Asynchroner und universeller sender/empfaenger.
JPH02305247A (ja) * 1989-05-19 1990-12-18 Nec Eng Ltd 通信制御装置
JPH0313147A (ja) * 1989-06-12 1991-01-22 Nec Corp 非同期同期インタフェースのフレーム変換回路
US4974225A (en) * 1989-09-14 1990-11-27 Northern Telecom Limited Data receiver interface circuit

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Publication number Publication date
EP0534030A1 (fr) 1993-03-31
US5263028A (en) 1993-11-16
DE69120816D1 (de) 1996-08-14
JPH05219046A (ja) 1993-08-27

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