EP0519743A2 - Bildinformationssteuergerät und Anzeigesystem - Google Patents

Bildinformationssteuergerät und Anzeigesystem Download PDF

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Publication number
EP0519743A2
EP0519743A2 EP92305662A EP92305662A EP0519743A2 EP 0519743 A2 EP0519743 A2 EP 0519743A2 EP 92305662 A EP92305662 A EP 92305662A EP 92305662 A EP92305662 A EP 92305662A EP 0519743 A2 EP0519743 A2 EP 0519743A2
Authority
EP
European Patent Office
Prior art keywords
image information
signal
timing signal
transfer timing
controlling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP92305662A
Other languages
English (en)
French (fr)
Other versions
EP0519743A3 (en
EP0519743B1 (de
Inventor
Katsuhiro C/O Canon Kabushiki Kaisha Miyamoto
Hiroshi C/O Canon Kabushiki Kaisha Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of EP0519743A2 publication Critical patent/EP0519743A2/de
Publication of EP0519743A3 publication Critical patent/EP0519743A3/en
Application granted granted Critical
Publication of EP0519743B1 publication Critical patent/EP0519743B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G09G2310/0227—Details of interlacing related to multiple interlacing, i.e. involving more fields than just one odd field and one even field
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas

Definitions

  • the present invention relates to an image information control apparatus in a display system and particularly a display system using a ferroelectric liquid crystal having a memory property.
  • a recent liquid crystal display system used in a personal computer (PC) or a workstation (WS) has a larger screen size and a higher resolution and is required to have compatibility with an existing PC or WS.
  • IBM CGA Color Graphics Array
  • IBM EGA Enhanced Graphics Array
  • IBM VGA Video Graphics Array
  • IBM 8514/A image adapter specifications are available as popular display modes used in the display system. These adapter specifications have different resolutions and different number of colors to be displayed.
  • a CRT (Cathode Ray Tube) display system is known as a system capable of selectively setting the above display modes.
  • Examples of the CRT display system are "Multisync II., “Multisync 3D", “Multisync 4D”, and “Multisync 5D” available from NEC CORP.
  • NEC CORP NEC CORP
  • a display system using a ferroelectric liquid crystal having a memory property suitable for a large screen size and a high resolution performs scan at a low frame frequency (5 to 20 Hz) so as to display information with a high resolution, as described in U.S.P. 5,058,994.
  • This driving at the low frame frequency is achieved in synchronism with communication of image information.
  • the drive frequency is changed in accordance with a change in environmental temperature to compensate for temperature dependency for threshold characteristics inherent to the ferroelectric liquid crystal, and a period required to write in one-line information is changed accordingly.
  • the end of write access of one-line information is signaled by an HSYNC signal (horizontal sync signal) to a graphic controller for managing transfer and communication of image information (information written in a VRAM under the control of a host CPU) when write access of one-line information is completed.
  • the graphic controller Upon reception of the information representing the end of write access of one-line information, the graphic controller transfers one-line image information to the display system.
  • BIOS Basic Input Output System
  • This change may result in a loss of compatibility with CRT application software.
  • a palette i.e., an element having a function of converting image information to color information
  • a CPU instruction For example, a palette (i.e., an element having a function of converting image information to color information) present in the graphic controller is accessed during a vertical blanking period of the CRT and changes color information in accordance with a CPU instruction.
  • color conversion timing errors occur because the vertical blanking period (every frame period) depends on the frame period of the ferroelectric liquid crystal panel, as compared with the case in which information is displayed in the CRT display system. This indicates that the color conversion speed becomes different from that in the CRT display system when application software for frequently performing screen color conversion is executed.
  • the output procedures of image information from the VRAM are determined.
  • the output procedures must be changed in accordance with a change in drive temperature, and information associated with this change is signaled to the graphic controller.
  • the graphic controller Upon reception of this information, the graphic controller must interrupt VRAM access for a predetermined period of time so as to change the procedures for accessing the VRAM. This also makes it difficult to establish compatibility with the CRT display system.
  • the drive waveform width (time required to perform write access) 1H or drive voltage must be controlled in accordance with the environmental temperature.
  • control of 1H requires a special implementation due to the following reason.
  • the one-line image information write time (period for receiving image information) of the ferroelectric liquid crystal is changed in accordance with a change in environmental temperature and is delayed to twice to eight times the transfer period of the CRT display system (e.g., VGA).
  • the 1H time change width in accordance with the environmental temperature is increased with an increase in 1H scan period of the CRT display system.
  • the drive voltage amplitude value becomes too high. This indicates that the breakdown voltage of a driver circuit for driving the ferroelectric liquid crystal must be increased, thus posing another problem.
  • Fig. 5 shows 1H and the drive voltage as a function of the environmental temperature.
  • the drive voltage must be abruptly changed at a point where the 1H is changed in accordance with the environmental temperature.
  • a voltage source for abruptly changing the drive voltage requires a long period of time to obtain a predetermined voltage value because the ferroelectric liquid crystal has a large capacitance. As a result, write access is not started until the drive voltage reaches a rated value.
  • an image information control apparatus comprising:
  • Fig. 1 is a block diagram showing a display system according to the present invention.
  • the display system includes a ferroelectric liquid crystal (FLC) panel 101, a common (scan line) driver circuit 102, a segment (information line) driver circuit 103, a control circuit 104, a host CPU (Central Processing Unit) 105 of, e.g., an IBM PC/AT machine, a graphic controller 106, an operation procedure control unit 107, an image information in one line unit thinning control unit 108, an image information transfer timing conversion control unit 109, an image information control unit 110, a transfer clock generation unit 111, a drive control unit (for controlling a write in timing for one line of the FLC panel 101) 112, a reference clock generation unit 113, and a thermo-sensor 114.
  • FLC ferroelectric liquid crystal
  • the common driver circuit 102 designates a scan address to access an arbitrary line represented by the scan address.
  • the segment driver circuit 103 accesses an information signal corresponding to image information to a predetermined line.
  • the graphic controller 106 comprises a VGA controller serving as a display control section of the host CPU 105.
  • the operation procedure control unit 107 controls operation procedures of the control circuit 104.
  • the control unit 108 thins image information from the graphic controller 106 in units of lines.
  • the image information transfer timing conversion control unit 109 converts image information transferred from the graphic controller 106 to a transfer speed and a timing which are suitable for the segment driver circuit 103.
  • the image information control unit 110 converts image information into pieces of image information ID1, ID2,... transferrable every predetermined period.
  • the transfer clock generation unit 111 generates a clock signal for the segment driver circuit 103.
  • the drive control circuit 112 outputs a control signal for forming a drive waveform suitable for the common driver circuit 102 and the segment driver circuit 103.
  • the reference clock generation unit 113 generates a reference clock for detecting the period of an HSYNC signal (horizontal sync signal) and generating a reference signal for a drive waveform period.
  • the thermo-sensor 114 detects the environmental temperature of the FLC panel 101.
  • Fig. 2 is a flow chart showing the basic operation of the control circuit 104.
  • Fig. 3 is a block diagram of the image information in one line unit thinning control unit 108 used in the present invention, and
  • Fig. 4 is a timing chart of the control unit 108.
  • Fig. 2 The basic operation in Fig. 2 will be described in detail below with reference to Figs. 1, 3, and 4. Numbers in circles in Figs. 2 and 4 represent the same operation periods. Assume that the graphic controller 106 outputs the above signals at the same timings and procedures as in the CRT display system in accordance with VRAM management software called a BIOS present in the graphic controller 106 under the control of the host CPU 105 for generating image information.
  • VRAM management software VRAM management software
  • the 1H is determined in accordance with the environmental temperature to be an 1H period optimal for the FLC panel 101 (basic operation 2 ). At this time, the drive voltage (maximum value of the common-segment drive waveform) is given as a fixed value.
  • the image information and the SYNC signal period are thinned, and the resultant values are respectively input to the segment driver circuit 103 and the drive control circuit 112.
  • the thinning is performed by the thinning control unit 108.
  • This time interval is changed from 0 to a maximum of the SYNC signal period in accordance with a change in environmental temperature.
  • the terminal potentials of the segment and common electrodes of the FLC panel 101 are controlled to be zero. Then, even if any time interval is formed, the image information will not be changed.
  • the 1H period is shortened with an increase in environmental temperature, the time for fixing the terminal potentials to be zero is prolonged. With this control, a waveform to be driven in synchronism with reception of the image information can be output even if the environmental temperature is changed and hence the 1H period is changed.
  • Fig. 6 shows the relationship between 1H, the constant voltage time and the drive voltage as a function of the environmental temperature.
  • Fig. 7 is a block diagram showing part of the drive control circuit 112, and Fig. 8 is a timing chart thereof. A description will be made with reference to Figs. 7 and 8.
  • the IRQ1 signal has the same timing as that obtained when the HSYNC signal is thinned by the number of lines calculated by the 1H and the HSYNC signal. For this reason, image information is input at the period of this IRQ signal, and driving is started at this period.
  • the operation procedure control unit 107 sets a count value in a programmable counter in accordance with information from the thermo-sensor 114.
  • the programmable counter starts counting the reference clocks when the IRQ1 signal goes to "L" level.
  • the counter outputs a ripple carry signal (RCO).
  • the counter is reset again and outputs the RCO signal at a predetermined period.
  • the RCO signal is used to generate a TIMR signal through a toggle F-F (Fig. 8).
  • the TIMR signal is input to the drive waveform control signal generation circuit, so that the drive control signal is switched at every leading edge of the TIMR signal.
  • the drive control signal generation circuit is reset every time the IRQ1 signal goes to "L" level. The same drive control signal is repeatedly output.
  • the timing generation circuit sets a DACT signal to "H” level at the leading edge of the TIMR signal after the IRQ1 signal goes to “L” level. Thereafter, the timing generation circuit counts the leading edges of the TIMR signal. If the IRQ1 signal does not go to "L” level during counting of a predetermined count, the DACT signal is reset to "L” level.
  • Fig. 8 shows a case in which the count value is 5.
  • the DACT signal is input to the drive waveform control change circuit.
  • a signal from the drive waveform control signal generation circuit is forcibly changed to a given value (i.e., a value for nullifying the terminal potential of the FLC panel 101) and is output to the segment and common driver circuits. This part is the important characteristic feature of the present invention.
  • the 1H period has the same duration as the "H" level duration of the DACT signal. This duration has a value obtained by multiplying 4 (in this embodiment) with the period of the TIMR signal.
  • the TIMR signal period is controlled (i.e, the counter value of the programmable counter is controlled) by the operation procedure control unit in accordance with a change in environmental temperature
  • the 1H period can be changed in accordance with the change in environmental temperature. Since the difference between the IRQ1 signal period and the 1H period corresponds to the "L" level duration of the DACT signal, the drive waveform control signal is forcibly changed so that the terminal potential of the panel becomes zero. As a result, the FLC panel can be maintained in a state wherein the information has been written during this duration.
  • Outputs SWFD0 and SWFD1 and outputs CWFD0 and CWFD1 from the drive waveform control signal generation circuit are waveform control signals for the segment and common driver circuits, respectively.
  • Values in Fig. 8 represent hexadecimal values of 2-bit signals as the signals SWFD0, SWFD1, CWFD0, and CWFD1, respectively.
  • the timing generation circuit resets a CSCLKCLR signal at the trailing edge of the DACT signal and sets it to "H" level again upon a lapse of the same pulse width (i.e., the period A in Fig. 8) as that of the TIMR signal.
  • a CSCLK signal is generated from the CSCLKCLR signal and an inverted signal of the TIMR signal.
  • the HT signal goes to "L” level at the leading edge of the first TIMR signal after the IRQ1 signal goes to "L” level.
  • the HT signal is set to "H” level again at the leading edge of the next TIMR signal.
  • the segment and common driver circuits can be controlled in accordance with the above signals, i.e., SWFD0, SWFD1, CWFD0, CWFD1, CSCLK, and HT signals.
  • the output waveform of the driver circuit is started at the leading edge of the CSCLK signal when the HT signal goes to "L" level.
  • the level of the drive waveform is determined by the values of the SWFD0, SWFD1, CWFD0, and CWFD1 signals at the leading edge of the CSCLK signal.
  • the drive waveforms of the segment and common electrodes are determined in accordance with the values of the SWFD0, SWFD1, CWFD0, and CWFD1 signals at the leading edge of the CSCLK signal.
  • a CRT display system output signal output from a graphic controller is received, and appropriate image information is transferred to the FLC panel 101.
  • the terminal potential of the FLC panel 101 is forcibly set to zero (constant potential) in accordance with a change in environmental temperature, thereby performing temperature compensation without changing the drive voltage.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Selective Calling Equipment (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Burglar Alarm Systems (AREA)
  • Alarm Systems (AREA)
EP92305662A 1991-06-21 1992-06-19 Bildinformationssteuergerät und Anzeigesystem Expired - Lifetime EP0519743B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3150320A JPH04371998A (ja) 1991-06-21 1991-06-21 駆動装置
JP150320/91 1991-06-21

Publications (3)

Publication Number Publication Date
EP0519743A2 true EP0519743A2 (de) 1992-12-23
EP0519743A3 EP0519743A3 (en) 1993-08-11
EP0519743B1 EP0519743B1 (de) 1997-11-26

Family

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Application Number Title Priority Date Filing Date
EP92305662A Expired - Lifetime EP0519743B1 (de) 1991-06-21 1992-06-19 Bildinformationssteuergerät und Anzeigesystem

Country Status (4)

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EP (1) EP0519743B1 (de)
JP (1) JPH04371998A (de)
AT (1) ATE160641T1 (de)
DE (1) DE69223283T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0691639A3 (de) * 1994-07-04 1997-06-04 Sharp Kk Verfahren und Einrichtung zur Steuerung einer ferroelektrischen Flüssigkristallanzeigetafel

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007013989B4 (de) * 2007-03-23 2009-01-02 Siemens Ag Treiberschaltung zur zeilen- und spaltenweisen Ansteuerung einer Passiv-Matrix-Flüssigkristallanzeige

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0335693A2 (de) * 1988-03-31 1989-10-04 Lynxvale Limited Kapazitiver Gewichtssensor
EP0355693A2 (de) * 1988-08-17 1990-02-28 Canon Kabushiki Kaisha Anzeigevorrichtung
EP0366153A2 (de) * 1988-10-28 1990-05-02 Canon Kabushiki Kaisha Flüssigkristallvorrichtung
EP0462541A2 (de) * 1990-06-18 1991-12-27 Canon Kabushiki Kaisha Bildinformationssteuergerät und Anzeigesystem

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0335693A2 (de) * 1988-03-31 1989-10-04 Lynxvale Limited Kapazitiver Gewichtssensor
EP0355693A2 (de) * 1988-08-17 1990-02-28 Canon Kabushiki Kaisha Anzeigevorrichtung
EP0366153A2 (de) * 1988-10-28 1990-05-02 Canon Kabushiki Kaisha Flüssigkristallvorrichtung
EP0462541A2 (de) * 1990-06-18 1991-12-27 Canon Kabushiki Kaisha Bildinformationssteuergerät und Anzeigesystem

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0691639A3 (de) * 1994-07-04 1997-06-04 Sharp Kk Verfahren und Einrichtung zur Steuerung einer ferroelektrischen Flüssigkristallanzeigetafel
US6115021A (en) * 1994-07-04 2000-09-05 Sharp Kabushiki Kaisha Method and apparatus for driving a liquid crystal panel using a ferroelectric liquid crystal material having a negative dielectric anisotropy

Also Published As

Publication number Publication date
ATE160641T1 (de) 1997-12-15
DE69223283D1 (de) 1998-01-08
JPH04371998A (ja) 1992-12-24
EP0519743A3 (en) 1993-08-11
EP0519743B1 (de) 1997-11-26
DE69223283T2 (de) 1998-04-02

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