EP0484360B1 - Elektrischer schaltkreis - Google Patents

Elektrischer schaltkreis Download PDF

Info

Publication number
EP0484360B1
EP0484360B1 EP90910728A EP90910728A EP0484360B1 EP 0484360 B1 EP0484360 B1 EP 0484360B1 EP 90910728 A EP90910728 A EP 90910728A EP 90910728 A EP90910728 A EP 90910728A EP 0484360 B1 EP0484360 B1 EP 0484360B1
Authority
EP
European Patent Office
Prior art keywords
current
transistor
input
output
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP90910728A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0484360A1 (de
Inventor
Heinz Rinderle
Rolf Böhme
Günter Gleim
Elke Rösch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefunken Electronic GmbH
Deutsche Thomson Brandt GmbH
Original Assignee
Telefunken Electronic GmbH
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefunken Electronic GmbH, Deutsche Thomson Brandt GmbH filed Critical Telefunken Electronic GmbH
Publication of EP0484360A1 publication Critical patent/EP0484360A1/de
Application granted granted Critical
Publication of EP0484360B1 publication Critical patent/EP0484360B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/59—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Definitions

  • the invention relates to an electrical circuit with a plurality of current-voltage converters, the parameters of which depend in approximately the same way on external factors.
  • Several current sources are connected in parallel to create a highly variable load resistance, e.g. a data processing system to provide electricity.
  • the voltage drop across the load resistor is tapped and added to a reference voltage in a summer.
  • the output voltage of the summer is amplified in an amplifier, the output of which is connected to the control inputs of all current sources; the output voltage of the amplifier therefore serves to regulate all current sources. Because the voltage drop across the load is added to a reference voltage, the load also serves as a measuring resistor.
  • the transmission resistance of a current-voltage converter depends on the temperature and other influencing variables.
  • the temperature dependency in integrated circuits is particularly pronounced because of the large changes in diffused or implanted resistors.
  • the invention solves this problem in that one of the current voltage transformers is provided as a reference current voltage transformer for regulating the transmission resistance of the current voltage transformers, the transmission resistance of which is compared with a reference resistor in a comparator, that a reference voltage to the reference resistor is proportional to the transmission resistance of the current voltage transformers is, and is applied to the comparator and that the output signal of the comparator is supplied to each current-voltage converter in such a way that the transmission resistance of the current-voltage converter is regulated to the constant value.
  • an integrated circuit contains several, but at least two, IU converters Wr, W1, ..., Wn.
  • Each IU converter has a current-sensitive, preferably low-impedance input, a live output and a control input.
  • One of the IU converters is provided as a reference IU converter Wr.
  • a reference current Iref is generated by means of a reference voltage source Uref and a reference resistor Rref, which is supplied to the input of the reference IU converter Wr.
  • the first input of a comparator V1 is connected to the output of the reference IU converter Wr and the second input is connected to the reference voltage source Uref.
  • the control inputs of all IU converters Wr, Wl, ..., Wn are connected to the output of the comparator V1.
  • FIG. 2 shows how the reference current Iref can be generated in a simple manner.
  • the reference resistor Rref lies between the reference voltage source Uref and the input of the reference IU converter Wr. With this arrangement, the potential at the input of the reference IU converter Wr must be equal to the potential of the ground terminal. If the reference resistor Rref is connected externally, two connections are required on the integrated circuit.
  • a differential amplifier Vd controls two current sources Iq1 and Iq2, which are shown here in the form of two transistors T1 and T2 with emitter resistors R1 and R2.
  • the output of the differential amplifier Vd is connected to the bases of the transistors T1 and T2.
  • the emitter resistors R1 and R2 lead to a common supply voltage source Ub1.
  • the collector of the first transistor T1, which corresponds to the output of the first current source Iq1 is connected to the reference resistor Rref and the first input terminal of the differential amplifier Vd.
  • the collector of the second transistor T2, which corresponds to the output of the second current source Iq2 is connected to the input of the reference IU converter Wr.
  • the voltage drop across the reference resistor Rref must be equal to the reference voltage Uref.
  • the current required for this is supplied by the first current source Iq1.
  • the current Iref to the input of the reference IU converter Wr is supplied by the second current source Iq2.
  • the current sources Iq1 and Iq2 can be dimensioned such that their currents are equal to one another or that, which is advantageous in the case of sensitive IU converters, the current Iref is a fraction K1 of the current through the reference resistor Rref.
  • stabilization can be much better than with an internal chip Resistance can be achieved. It is also possible to compensate for sample variations in the signal sources feeding the IU converters by adapting the reference resistance.
  • the reference IU converter Wr supplies the output signal Ur to two connection terminals with opposite polarity, the common-mode voltage of both output terminals being dependent on the temperature or other influencing factors.
  • a comparison of the symmetrical output signal Ur of the reference IU converter Wr with the asymmetrical reference voltage Uref must therefore be carried out.
  • this can be done by a differential stage consisting of two transistors T3 and T4, which is fed by a current source Iv, the current source Iv being dependent on the reference voltage Uref.
  • An emitter resistor R3 is connected upstream of one of the two transistors.
  • the bases of the transistors T3 and T4 are connected to the output terminals of the reference IU converter Wr.
  • the collectors of transistors T3 and T4 are connected to a current mirror Ssp.
  • a signal Uv is taken from the output A of the current mirror Ssp, which e.g. is converted into a control signal Sr by an output amplifier.
  • the function of this part of the comparator V1 results from the fact that with a mirror factor one of the current mirror Ssp and in the balanced state of the control loop, the same currents Iv / 2 flow through the two branches with the transistors T1 and T2, and thus the voltage Ur is equal to that Voltage drop Ur3 must be across resistor R3.
  • the current Iv is formed according to FIG. 5 by means of the reference voltage Uref. 5a, a differential amplifier V2 is provided, the first input of which is connected to one pole of the reference voltage source Uref, the second input of which is connected to the one terminal of a reference resistor Rref2 and the output of which is connected to the base of a current source transistor T5.
  • the emitter of the current source transistor T5 is connected to the second input of the Differential amplifier V2 connected.
  • the other pole of the reference voltage source Uref and the other connection of the reference resistor Rref2 are grounded or at a reference point.
  • the voltage drop across the reference resistor Rref2 becomes equal to the reference voltage Uref.
  • the current that can be drawn from the collector of the current source transistor T5 then corresponds to the current through the reference resistor Rref2 except for the low base current.
  • the circuit from FIG. 5b differs from the circuit from FIG. 5a in the arrangement of the current source transistor T5, the collector of which is connected here to the second input of the differential amplifier V2, while the emitter represents the current source output Ai. While in Figure 5a the second input of differential amplifier V2 is of the inverting type, in Figure 5b it must be non-inverting.
  • FIG. 5b also shows how a current source can be formed in the opposite direction.
  • a resistor R5 is connected between the output Ai and a supply voltage source Ub2.
  • the base of a further transistor T6 is connected to the output of the differential amplifier V2.
  • a resistor R6 is located between the supply voltage source Ub2 and the emitter of the transistor T6.
  • the reverse direction output current Iv is taken from the collector of transistor T6, which is designated as output Aj.
  • the task of stabilizing several IU converters while maintaining different transmission resistances can also be carried out with the means according to the invention.
  • a differential stage with bipolar transistors T7 and T8 which acts as a controllable organ within the IU converter.
  • the i-th IU converter is composed of an input stage Wai, a differential stage Wbi and an output stage Wci.
  • the input stage Wai converts the input current Ii into a voltage Uai.
  • the differential stage Wbi lying between the input stage Wai and the output stage Wci is constructed from bipolar transistors T7 and T8, the bases of which are connected to the output of the input stage Wai, the emitters of which are connected to a current source Ibi and the collectors of which are connected to the inputs of the output stage Wci .
  • the output stage Wci forms the output voltage Ui from the collector currents of the differential stage Wbi.
  • the mode of operation is based on the fact that the slope of the differential stage and thus its amplification is proportional to the current of the current source Ibi.
  • the current Ibi In order to ensure that the i-th converter Wi has K times the transmission resistance compared to the reference IU converter Wr, the current Ibi must assume the K times the value of the current Ibr of the reference IU converter Wr.
  • the circuitry means for this are known and therefore do not need to be explained here.
  • the possibility of making the factor K variable and thus controllable is included.
  • FIG. 7 One possibility of making the transmission resistance discretely controllable and thus programmable is shown in FIG. 7.
  • Several differential stages from bipolar transistors T71, T81; T72, T82; T73, T83; ... are connected on the input side to the Wai input section and on the output side to the Wci output section. They are fed by current sources Ib1, Ib2, Ib3 ..., which can be switched on and off by controllable switches S1, S2, S3 ... If for the transistors T71, T81; T72, T82; T73, T83; ... the differential stages emitter resistors R71, R81; R72, R82; R73, R83; ... are provided, the linearity and other properties are improved.
  • the steepness of the middle part Wbi results from the sum of the steepness of the differential stages switched on.
  • the slope can be changed in stages via the controllable switches K1, K2, K3, ...
  • the areas of the transistors T71, T81; T72, T82; ... also staggered in the ratio of the currents, because this enables maximum accuracy and stability to be achieved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Networks Using Active Elements (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Paper (AREA)
  • Manufacture And Refinement Of Metals (AREA)
  • Analogue/Digital Conversion (AREA)
EP90910728A 1989-07-27 1990-07-04 Elektrischer schaltkreis Expired - Lifetime EP0484360B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE3924804A DE3924804A1 (de) 1989-07-27 1989-07-27 Elektrischer schaltkreis
DE3924804 1989-07-27
PCT/EP1990/001067 WO1991002301A1 (de) 1989-07-27 1990-07-04 Elektrischer schaltkreis

Publications (2)

Publication Number Publication Date
EP0484360A1 EP0484360A1 (de) 1992-05-13
EP0484360B1 true EP0484360B1 (de) 1995-01-04

Family

ID=6385923

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90910728A Expired - Lifetime EP0484360B1 (de) 1989-07-27 1990-07-04 Elektrischer schaltkreis

Country Status (15)

Country Link
US (1) US5245218A (zh)
EP (1) EP0484360B1 (zh)
JP (1) JP2871850B2 (zh)
KR (1) KR0135629B1 (zh)
CN (1) CN1043272C (zh)
AT (1) ATE116750T1 (zh)
AU (1) AU6073890A (zh)
DD (1) DD295441A5 (zh)
DE (2) DE3924804A1 (zh)
FI (1) FI920357A0 (zh)
HK (1) HK106397A (zh)
HU (1) HU218058B (zh)
MY (1) MY107257A (zh)
TR (1) TR25653A (zh)
WO (1) WO1991002301A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930010834A (ko) * 1991-11-25 1993-06-23 프레데릭 얀 스미트 기준 전류 루프
JP3102396B2 (ja) 1997-12-03 2000-10-23 日本電気株式会社 電圧制御発振回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3956638A (en) * 1974-12-20 1976-05-11 Hughes Aircraft Company Battery paralleling system
US3986101A (en) * 1975-03-10 1976-10-12 Ncr Corporation Automatic V-I crossover regulator
US4032830A (en) * 1975-07-03 1977-06-28 Burroughs Corporation Modular constant current power supply
CH659156A5 (en) * 1982-11-30 1986-12-31 Hasler Ag Method for the protected supply of a load with a rectified DC voltage
US4618779A (en) * 1984-06-22 1986-10-21 Storage Technology Partners System for parallel power supplies

Also Published As

Publication number Publication date
CN1049065A (zh) 1991-02-06
KR920704210A (ko) 1992-12-19
CN1043272C (zh) 1999-05-05
HU218058B (hu) 2000-05-28
HK106397A (en) 1997-08-22
HU9200206D0 (en) 1992-04-28
WO1991002301A1 (de) 1991-02-21
DD295441A5 (de) 1991-10-31
JPH05501180A (ja) 1993-03-04
KR0135629B1 (ko) 1998-05-15
FI920357A0 (fi) 1992-01-27
ATE116750T1 (de) 1995-01-15
EP0484360A1 (de) 1992-05-13
JP2871850B2 (ja) 1999-03-17
DE3924804A1 (de) 1991-01-31
US5245218A (en) 1993-09-14
HUT60046A (en) 1992-07-28
MY107257A (en) 1995-10-31
AU6073890A (en) 1991-03-11
TR25653A (tr) 1993-07-01
DE59008203D1 (de) 1995-02-16

Similar Documents

Publication Publication Date Title
DE69933160T2 (de) Hochfrequenzverstärker
DE60102486T2 (de) Verstärker mit mehreren spannungsversorgungen und dynamischer spannungssteuerung
DE1901804C3 (de) Stabilisierter Differentialverstärker
EP0721269A2 (de) Verfahren und Schaltungsanordnung für den Abschluss einer zu einer integrierten CMOS-Schaltung führenden Leitung
DE3725339A1 (de) Automatische justierschaltung zum justieren der zeitkonstanten einer filterschaltung
EP0365085B1 (de) Schaltungsanordnung zum Einstellen der Amplitude eines Signals
EP0581835B3 (de) Schaltung für einen regelbaren verstärker
DE2216409C2 (de) Differenzverstärkerschaltung
DE3832448A1 (de) Messverstaerker mit programmierbarer verstaerkung
EP0499657B1 (de) Integrierbarer Shunt-Regler
DE2250625C3 (de) Schaltungsanordnung zur Konstanthaltung eines an eine Last gelieferten Stromes
EP0484360B1 (de) Elektrischer schaltkreis
DE2924171C2 (zh)
EP0506174B1 (de) Integrierte Schaltungsanordnung mit einem Differenzverstärker
DE3545392A1 (de) Stromspiegelschaltung
DE3206779C2 (zh)
DE4210215C2 (de) Differenzverstärkeranordnung
DE60019511T2 (de) Gleichrichterstromkreis
EP0044047B1 (de) Schaltungsanordnung zur Erhöhung des auswertbaren Hall-Signals eines Hall-Sensors
DE3816140A1 (de) Videosignalumschalter
DE19743205C2 (de) Bipolare Impedanzwandlerschaltung
DE2418455A1 (de) Schaltungsanordnung zur signalbeeinflussung, insbesondere lautstaerkeeinstellung
WO2003079544A1 (de) Transistoranordnung
EP0217147A1 (de) Schaltungsanordnung zur Ansteuerung eines Drehmagnetmessgeräts
DE2142719A1 (de) Schaltung fuer transistorgleichspannungsmesser

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19920121

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB IT LI LU NL SE

17Q First examination report despatched

Effective date: 19940407

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

ITF It: translation for a ep patent filed

Owner name: BARZANO' E ZANARDO MILANO S.P.A.

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH DE DK ES FR GB IT LI LU NL SE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: THE PATENT HAS BEEN ANNULLED BY A DECISION OF A NATIONAL AUTHORITY

Effective date: 19950104

Ref country code: NL

Effective date: 19950104

Ref country code: DK

Effective date: 19950104

Ref country code: BE

Effective date: 19950104

REF Corresponds to:

Ref document number: 116750

Country of ref document: AT

Date of ref document: 19950115

Kind code of ref document: T

REF Corresponds to:

Ref document number: 59008203

Country of ref document: DE

Date of ref document: 19950216

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19950120

ET Fr: translation filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19950404

NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Effective date: 19950704

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Effective date: 19950731

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19950731

Ref country code: LI

Effective date: 19950731

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

REG Reference to a national code

Ref country code: GB

Ref legal event code: 746

Effective date: 20010802

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20070730

Year of fee payment: 18

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080704

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20090722

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20090721

Year of fee payment: 20

Ref country code: GB

Payment date: 20090629

Year of fee payment: 20

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Expiry date: 20100703

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20100703

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20100704