EP0479915A1 - Ordinateur portatif a faible consommation de courant - Google Patents

Ordinateur portatif a faible consommation de courant

Info

Publication number
EP0479915A1
EP0479915A1 EP19900911349 EP90911349A EP0479915A1 EP 0479915 A1 EP0479915 A1 EP 0479915A1 EP 19900911349 EP19900911349 EP 19900911349 EP 90911349 A EP90911349 A EP 90911349A EP 0479915 A1 EP0479915 A1 EP 0479915A1
Authority
EP
European Patent Office
Prior art keywords
computer
display
keyboard
asic
traces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19900911349
Other languages
German (de)
English (en)
Other versions
EP0479915A4 (en
EP0479915B1 (fr
Inventor
John P. Fairbanks
Leroy D. Harper
Stavro E. Prodmou
Ian H. S. Cullimore
Noah L. Anglin
Shinpei Ichikawa
Roy J. Machamer
Gary R. Miracle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Personal Systems Inc
Original Assignee
Fujitsu Personal Systems Inc
Poqet Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Personal Systems Inc, Poqet Computer Corp filed Critical Fujitsu Personal Systems Inc
Publication of EP0479915A1 publication Critical patent/EP0479915A1/fr
Publication of EP0479915A4 publication Critical patent/EP0479915A4/en
Application granted granted Critical
Publication of EP0479915B1 publication Critical patent/EP0479915B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/02—Digital computers in general; Data processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators

Definitions

  • This invention relates to small low power computers, in particular battery operated computers using liquid crystal displays.
  • BIOS basic input/output system
  • These computers include an internal clock which operates continuously when the machine is turned on and controls the central processor to access memory, load registers, read and write to disk, detect keyboard use, and control a display, all operations synchronized with cycles of the internal clock.
  • the external communications may be controlled by an asynchronous clock through a UART
  • lap top computers are battery operated, portable, and may run a broad range of commercial software. However, these lap top computers are powered by bulky rechargeable batteries and can only operate for a few hours before requiring the batteries to be recharged.
  • the present invention provides a computer combining many features which allow the computer to occupy a small space and allow for operation of the computer using considerably lower power than that of the lap top computers presently available, and yet which has the computing power of a desk-top IBM XT or AT and a display monitor which can display 80 characters by 25 lines.
  • a test of one XT compatible computer shows a battery life of about 100 hours of operation with two AA alkaline batteries.
  • a preferred embodiment uses standard, batteries widely available, so that this computer can continuously serve a user travelling to remote parts of the world. That is, spare batteries can be easily carried (a single AA size battery, for example, is less than two inches long and one inch thick) and may be purchased widely just as are batteries used in most flashlights and portable radios.
  • the preferred embodiment could use any battery which met the form factor of the compartment and had the same approximate electrical specifications.
  • Another embodiment could use a battery other than AA size batteries.
  • the computer operates effectively on inexpensive batteries that, as in the example of AA batteries, initially provide about 1.6 volts, and as they are drained later provide only about .8 volts.
  • Prior art computers require batteries that provide a level amount of voltage during their useful lives.
  • the computer is housed in a two-part low profile rectangular case hinged along one long edge and latched at an opposite edge.
  • the hinge extends along a back edge of the case and rotatably joins upper and lower portions of the case.
  • This hinge is described in commonly assigned U.S. application serial no. 07/373,769 invented by Arthur L. Anglin entitled "HINGE FOR HAND HELD COMPUTER", incorporated herein by reference.
  • the case is preferably of a plastic such as polycarbonate and/or ABS plastic or both.
  • the case is of molded construction.
  • a lower portion of the case includes a keyboard, one or two memory cards, batteries, and most of the integrated circuit components of the computer.
  • the integrated circuit components in this lower portion are attached to the lower side of a printed circuit board which occupies most of the rectangular area encompassed by the case. Included in these integrated circuit components are two ASIC (application specific integrated circuit) chips. In order to conserve space, particularly vertical space, these ASIC chips are put on the board without the usual packaging.
  • Such packaging (which is omitted) would include a plastic or ceramic protective cover surrounding a lead frame which connects interior pin-outs to exterior pins.
  • the unpackaged chip is bonded directly to the lower printed circuit board, thereby saving both horizontal and vertical space in the present very compact structure.
  • the microprocessor chip is also attached directly to the printed circuit board without intervening packaging, which reduces connection points and cost.
  • connectors for receiving removable memory cards preferably at least two connectors for two cards. These connectors are the same thickness as the card itself.
  • No circuit components are located on that part of the printed circuit board adjacent to where the memory cards are placed, so that the memory cards fit within the existing envelope of the computer housing.
  • a tray for holding a memory card which forms part of the lower case is described in detail in commonly assigned U.S. application serial no. 07/374,409 invented by Arthur L. Anglin and Peter F. Cadwell entitled "MEMORY CARD TRAY FOR PORTABLE COMPUTER", incorporated herein by reference.
  • At one or several edges of the printed circuit board are pads to which traces extend from pins of the integrated circuit chips to which test signals are applied during manufacturing.
  • the keyboard occupies most of the inner surface of the lower case, occupying more than half, and preferably 70% or more of the surface area of the inner surface of the lower case.
  • the upper side of this printed circuit board also includes traces for detecting a machine reset.
  • reset is activated by inserting a pointed object such as a pencil point through an opening in the keyboard and pressing an electrically conductive pad rather than by pressing a key or combination of keys.
  • one of the keyboard keys is an on/off toggle key. The computer never turns completely off, but in the off state operates only a low frequency clock which keeps time-of- day. After testing of the lower printed circuit board and installation of the membrane during assembly of the computer, the keyplate which holds the keys in position is welded to the lower portion of the case in order to achieve accurate registration of the keys, the membrane, and the traces.
  • a compartment including batteries and a capacitor. This capacitor is sufficient to maintain volatile memory with the computer in the off state while batteries are being changed.
  • the batteries are covered by a plate which is imprinted with descriptions of a top row of keyboard function keys, these function keys being located just adjacent to the battery cover plate. In one embodiment, four notations in four different colors are imprinted on the cover plate adjacent each function key. Keys for "shift”, “alt”, “ctrl”, and a special logo key are correspondingly colored to indicate to a user that combining the "shift”, “alt”, “ctrl”, or the logo key with the adjacent function key produces the function noted in color adjacent the function key. . Alternate cover plates, tapes for attaching to the cover plate, or cards for placing adjacent this cover plate may be provided for use with different software packages.
  • An upper portion of the case houses a liquid crystal display plus a separate power supply for the liquid crystal display.
  • a space is provided between the display and the outside of the upper case for insertion of a display back light powered by separate batteries or other power source.
  • This back light is described in detail in commonly assigned U.S. application serial no. 07/276,167, the contents of which is incorporated herein by reference.
  • the power supply for the liquid crystal display is described in detail in commonly assigned U.S. application serial no. 07/374,340 invented by John. P. Fairbanks, Andy. C. Yuan, and Lance T. Klinger, entitled "POWER SYSTEM AND SCAN TECHNIQUE FOR A LIQUID CRYSTAL DISPLAY", attorney docket no. M-806, incorporated herein by reference.
  • the liquid crystal display occupies most of the entire area enclosed by the upper portion of the case, with a narrow frame surrounding the liquid crystal display and its cover.
  • the display when displaying characters shows 25 lines of 80 characters per line.
  • a line of characters is typically 8 pixels tall so that the standard 25 lines of text are displayed using 200 rows of pixels.
  • a status line using one or more rows of pixels at the top, bottom or both, of the display are provided for showing status of various software programs and hardware conditions. Coordinating with these displayed status lines are imprinted legends along the top, bottom, or both margins of the display frame for indicating to the user the meanings represented by these status lines. As with the keyboard, different legends can be provided for different software packages.
  • a cable including these lines extends from the lower to the upper portion of the case and is located toward the interior of the computer from the hinge axis.
  • the cable has sufficient length to span from its lower point of connection to its upper point of connection when the computer case is fully open.
  • the spiral design of the cable acts as a spring so that when the computer is closed, the excess cable slack is taken up in a cable cover located in the upper or lower portion of the case, preferably lower. This cable cover protects the cable from excess flexure, assuring long life.
  • This arrangement of the components allows for the computer to fold to a very compact size for being carried and to open to a convenient size in which the two components which interface with the user, namely the keyboard and the display, are large enough to be convenient.
  • the keys are made so that some keys are pressed by the display upon closing the computer case. Preferably, these are the front (lower) row of keys.
  • the keyboard is controlled such that a multiplicity of key presses does not cause an executing program to cease operation.
  • the on/off key is a key not depressed when the case is closed.
  • other keys are deactivated such that pressing the other keys upon closing the case is not detected by the computer.
  • the processor does not lose its place in the program which was running. All memory remains static but execution is halted until the machine is moved out of the off state. While in this off state, timer interrupts are processed allowing time of day updating, and allowing software which uses the time of day interrupt to process the interrupt.
  • the computer of the present invention includes a power management system which maintains as many components of the computer in an off state for as much time as possible even when the computer is on. Individual components can be turned off while other components remain on. Components of the machine which can be turned off while the machine appears to a user to be on include the oscillator and clock which cycle the central processor, another oscillator and clock which control the display, a direct memory access (DMA) clock tied to the central processor oscillator which controls direct memory access circuits, and an oscillator and clock for communication to an external port. While the machine is turned on, that is, while the display is on and the machine is responding to user input, the hardware detects activities for which some parts of the machine can be turned off. These clocks can actually be turned off while the user is in the midst of executing a program. For example, when a user is executing a word processing program, the clock which controls the central processor is turned off for most of the time between one keystroke and the next.
  • DMA direct memory access
  • FIG. 1 Perspective view of the computer.
  • Figure 2. Exploded view of keyboard.
  • FIG. 1 System diagram showing interconnections of the integrated circuit chips.
  • Figure 4. A circuit board, front side.
  • Figure 5. Circuit board of Figure 4, rear side.
  • Figure 7. A test structure.
  • Figures 8A, 8B. A computer reset structure.
  • Figure 9. A border plate, display and keyboard.
  • Figures 11A to llAd Schematics of a system ASIC. Appendix A is an I/O map.
  • Fig. 1 shows a perspective view of the computer showing upper case 110a, lower case 110b, display 112, display frame 113, keyboard 118, key plate 118a, battery cover 123, hinge 111, latch 114, memory card tray 125, and display indicator graphics 130.
  • Fig. 2 shows an exploded view of the computer keyboard 118 showing keyplate 118a with keys such as 181, 5 182, and 183, membrane 128 with cones such as 281, 282, and 283 each holding a conductive pad (not shown) , and printed circuit board 138.
  • Membrane 138 is elastomeric,- and protrudes upward in a plurality of locations to form a plurality of 0 elastomeric cones, one beneath each key, for example cones 281, 282, and 283 beneath keys 181, 182, and 183 respectively.
  • Each cone is truncated at a flat (or relatively flat) upper surface which is contacted by an underside of its corresponding key. Extending downward 5 from the flat upper surface of each of the elastomeric cones into the interior of the respective cone is an elastomeric conductive pill. When a key is pressed, its corresponding cone is compressed, moving its corresponding pill into position to span conductive traces (not shown)
  • Figure 4 shows a first side of the printed circuit board 138 including IC chip mounting areas 302, 304, 306.
  • Figure 5 shows the rear (i.e., second) side of the printed circuit board 138 including key contacts such as
  • Figure 6A shows in a side view how one IC chip 340 is electrically connected to printed circuit board 138 by bond wires 342, 344, etc. from pins 346, 348, etc. on chip
  • Figure 6B shows a top view of Figure 6A.
  • Figure 7 shows a test structure as provided on
  • test interconnect areas 360, 362, 364, 366, 368, each consisting of several pads such as 370, 372 to which - li ⁇ test signals are provided by test cables such as 380.
  • Test cable 380 is connected to printed circuit board 138 only when testing is to be performed.
  • Card edge test connector 382 connects test cable 380 to the pads 370, 372, etc.
  • indicating locator such as 390, 392 are provided as cut outs in the edge of printed circuit board 138 to locate the card edge test connectors such as 382. Note that as shown in Figures 4 and 5, such a test structure is provided on both sides of printed circuit board 138.
  • Figure 8A shows a top view including dimensions of a portion of the keyboard 118 of the computer showing key 181 in keyplate 118a. Key 181 is partly cut away to expose cone 281.
  • Figure 8B shows a cross-sectional view along line B-B in Figure 8A. As shown in Figure 8B (key 181 not shown) a corresponding gap 400 has been left in keyplate 118a exposing cone 281. Thus it is possible to press down on cone 281 with an object (such as a pencil point) through gap 400. Preferably this is done to reset the computer, by compressing conductive pill 402 against traces 404, 406 on printed circuit board 138.
  • Fig. 3 shows a chip architecture computer system diagram showing interconnections of the integrated circuit chips physically shown in Fig. 2b plus the LCD driver chips located in the upper case and not shown in Fig. 2b.
  • the system of Fig. 3 includes an 80C88 microprocessor 16, a Peripheral ASIC chip 17, a System ASIC chip 18, and an LCD RAM 15, all physically located on a PCB board.
  • This small combination of integrated circuit chips models in one embodiment an IBM XT computer. It may model other computers in other embodiments. They are physically located in the lower portion of the computer casing beneath the keyboard. Also physically located in the lower portion of the case is 512K of system RAM 19, a BIOS ROM chip 20, an application ROM chip 21, one or two memory cards 22a and 22b, and expansion port 23, and UART driver chip 24.
  • VCO and other oscillators 11, and system power supply 13 (which in a preferred embodiment includes two AA batteries) are also located in the lower portion of the case in addition to keyboard 12.
  • the LCD display Located in the upper portion of the case is the LCD display, an optional audio transducer, and a separate power supply.
  • Display driver 14 includes row and column drivers and the analog power supply plus a unique display scan technique which lowers power. The entire system was designed to lower power. In particular, oscillators 11 require low power because they can be turned off when not actively used, a unique feature. The majority of the digital logic is CMOS, including memory 19, BIOS 20, application ROM 21. These draw microamps in the standby state and up to 100 milliamps in operation.
  • VCO/OSCILLATORS This block contains all of the frequency oscillators used in the system. They include a display clock oscillator running at about 800 KHz, a communications clock oscillator running at 1.8432 MHz, a low frequency oscillator running at 32,768 Hz, and a voltage controlled oscillator (VCO) which operates between 1 and 8 MHz.
  • VCO voltage controlled oscillator
  • the oscillator which drives the Processor 16 is voltage controlled, so if there is a sag in the supplied voltage, the frequency will drop to compensate for the lower performance of the CMOS circuits. This also allows the processor speed to be automatically adjusted when the system power supply changes output voltages. At 5 volts all components will run at 8 mHz. At 3 volts they would not run at 8 mHz but at 2 mHz the system will run. There is a power advantage to running at 3 volts because
  • KEYBOARD This is a standard matrix keyboard arranged in a 6x11 matrix of columns and rows. When a key is pressed, it completes the circuit between a selected row and column. The rows and columns are scanned by the keyboard control circuits within the Peripheral ASIC 17.
  • the novel feature of Keyboard 12 is that fewer lines are needed between keyboard 12 and ASIC 17. Controller 17 uses only 7 return lines and 11 scan lines for a total of 18 lines to keyboard 12. Conventional keyboards use about 26 lines. Also unlike typical personal computers of today, no chip is dedicated as a keyboard controller. All keyboard control occurs in ASIC 17. Saving a chip saves power and board space. KBSCAN ⁇ Q..IOI These are the keyboard matrix 12 scan lines. The keyboard control circuits within the Peripheral ASIC 17 send out a scan signal on each of these lines individually and monitor the KBCOL[0..5] lines for a signal return.
  • ONOFFN This is a line from keyboard 12 which is associated with a special key used to turn the computer on and off. When this key is pressed, it provides a path to ground causing a low signal on this line. Otherwise the line is pulled up to VDD to assure that its default state is high. This signal is monitored by the Peripheral ASIC 17 and may interact with software running on the processor 16.
  • BLOCK 13 SYSTEM POWER SUPPLY This is the power supply for the majority of the circuits within the computer. One notable exception is the display which has its own power supply located within block 14 as described above. This power supply includes the power source, namely two AA-size batteries, and necessary circuits to provide needed voltages and current for the computer. SELVDD
  • a low level output on this line forces the power supply into a low voltage mode.
  • low voltage is three volts
  • high voltage is five volts.
  • automatic mode current demand is sensed, and when it passes a predetermined threshold, approximately 20 milliamperes in the current invention, it moves the voltage output from low to high voltage after a programmed delay.
  • This signal is controlled by a bit within the Peripheral ASIC 17 allowing software to select between the high voltage and automatic modes of power supply operation.
  • This signal from block 13 to the Peripheral ASIC is used to monitor the voltage of the system batteries. It is low to indicate that batteries are above a predetermined threshold (see discussion of BATMON) , and goes high when these batteries fall below the threshold.
  • This signal is monitored by the Peripheral ASIC 17 and may interact with software running on the processor 16. Since software running on the processor is able to monitor the real time condition of the batteries and determine when the batteries are about to expire, the BIOS will refuse to move from the off state when it is determined that doing so would jeopardize the integrity of the system memory and processor states.
  • BATMON This signal is used by the battery voltage monitor circuits in 13. The signal can be manipulated by the processor 16 to set the threshold at which LOWBAT will change states. When BATMON is high, the threshold is 1.8 volts. When it is low, the threshold is 1.6 volts. This is used to sense low and dead battery conditions.
  • This signal controls the LCD power supply within 14. When it is low, the power supply is enabled and running. When it is high, the power supply is disabled and producing no output. This signal is controlled by a bit within the Peripheral ASIC 17 which can be manipulated by the processor.
  • VIDEO DISPLAY This block contains the LCD display driver circuits, the display power supply, the LCD screen, an audio transducer, and drive circuits for the audio transducer.
  • LCD driver 14 and LCD RAM 15 control a liquid crystal display screen which is used in the present invention.
  • LCD driver 14 is described in commonly assigned U.S. patent application serial no. 07/374,340 invented by John P. Fairbanks, Andy C. Yuan, and Lance T. Klinger entitled "POWER SYSTEM AND SCAN METHOD FOR LIQUID CRYSTAL DISPLAY", and incorporated herein by reference.
  • BLOCK 15
  • LCD RAM 15 receives information about characters or graphic images to be displayed on the LCD screen.
  • LCD RAM 15 includes a character memory which stores an ASCII representation and display attribute for each display character position, bit map images of each character in the character set currently in use, and a bit map memory where each display pixel on the LCD display is represented.
  • a look-up table is also stored which is used by the display controller located within the Peripheral ASIC 17. Additional memory is provided which can be used as nonvolatile data storage.
  • LCD RAM 15 includes two 32K x 8 static RAM chips. These chips store character and attribute data, LCD bit map data, character bit map data, and character translation data.
  • This signal line from the display control circuits within Peripheral ASIC 17 is used to chip select one of the two RAM chips within LCD RAM 15. Specifically, this line selects the RAM used to store character, attribute, and LCD bit map data. This line is connected to the chip select pin on the RAM chips in LCD RAM 15. VRAMOEN
  • This signal line from the display control circuits within Peripheral ASIC 17 is used to enable the currently selected RAM chip within LCD RAM 15 (see discussion of VRAMCSN and VROMCSN) to drive data from the memory location specified by LCDADDR[0..14] onto the data bus LCDDATA[0..7] .
  • VMEMWN This signal line from the display control circuits within Peripheral ASIC 17 causes the currently selected RAM chip within LCD RAM 15 (see discussion of VRAMCSN and VROMCSN) to latch the data on LCDDATA[0..7] into the address specified by LCDADDR[0..14] .
  • This signal line from the display control circuits within Peripheral ASIC 17 is used to chip select one of the two RAM chips within LCD RAM 15. Specifically, this line selects the RAM used to store character bit maps and translation address data. It is connected to the chip select pin on the RAM chips within LCD RAM 15.
  • 80C88 CPU This is the processor on which the architecture of the computer is based. It may be purchased from Intel Corporation, Harris Semiconductor, or OKI Semiconductor.
  • processor status pins of microprocessor 16 are connected to the 8288 compatible Bus Controller cell located with the System ASIC 18. Their function is detailed in the data sheet of both the 80C88 and 8288 components available from Intel Corporation. LOCKN
  • This signal line is connected to the NMI (non maskable interrupt) pin of the processor 16.
  • a signal on this line is generated by the System ASIC 18 and is the processor 16 non-maskable interrupt.
  • the term nonmaskable interrupt indicates the interrupt cannot be masked by the microprocessor 16. This interrupt can be masked by circuits external to microprocessor 16. AAD ⁇ O..71
  • Processor 16 address data bus lines. These lines are the multiplexed address and data bus of the processor and connect to the peripheral ASIC 17 and the 8288 compatible Bus Controller cell located with the System ASIC 18. Their function is detailed in the data sheet of both the 80C88 and 8288 components available from Intel Corporation. AAT8 . . 191
  • the system clock signal is generated within the Peripheral ASIC 17 (where it is also used) and is derived either from the VCO oscillator located in block 11 or from an external source provided on line EXTSYSCLK. 5 CPURDY
  • the signal on this line comes from the Peripheral 0 ASIC 17. Circuits within the Peripheral ASIC 17, the
  • PERIPHERAL ASIC 17 is the interface between the processor and peripheral devices, including keyboard 12, system power supply 13, LCD display driver 30 14, and LCD RAM 15. It also interfaces to oscillators 11 and turns them on and off under software control.
  • a schematic of Block 17 is shown in Figures 10A to lOCe.
  • Each figure 35 includes, in addition to the blocks, a list of signals entering and exiting the block, each signal name surrounded by an arrow. Signals on buses more than one bit wide have names specifying the number of lines in the bus.
  • Figures 10 and 11 show in detail a presently preferred embodiment of the invention.
  • the circuits of Figures 10 and 11 are each respectively an application specific integrated circuit chip as implemented by LSI Logic Corporation. Names of lines, buses, and gates meet the specifications of LSI Logic Corporation and can be used to generate a net list of gates to be connected in an ASIC chip.
  • the PERIPHERAL ASIC 17 (application specific integrated circuit) is one chip of a two chip implementation of an IBM PC/XT compatible computer. A complete PC/XT compatible system may be implemented with this chip, a SYSTEM ASIC 18 (described below) , an Intel 8088 compatible CPU, and memory devices.
  • the PERIPHERAL ASIC 17 supports a 640 x 200 pixel LCD display, a 11 x 7 key keyboard matrix, RS-232 communications, time keeping, and power management functions.
  • the PERIPHERAL ASIC chip performs peripheral functions including RS-232 serial communications, LCD display control, keyboard control, time keeping, and power management.
  • the PERIPHERAL ASIC contains a National Semiconductor 16C450 compatible circuit for serial communications, as well as display controller, keyboard controller, timer, and power management circuits unique to the PQ-XT.
  • the PERIPHERAL ASIC chip supports serial communication through the use of a National Semiconductor 16C450 compatible UART.
  • the 16C450 compatible registers are located at ports 03F8 - 03FFh, compatible with the COM1 definition for the IBM PC/XT, along with the use of interrupt request IRQ4.
  • the PERIPHERAL ASIC supports enabling/disabling the UART by writing a zero/one to bit 4 of port F6Elh. Disabling the UART causes its registers to disappear from the port map.
  • the UART is enabled upon reset of the PERIPHERAL ASIC.
  • the PERIPHERAL ASIC supports the time keeping functions used in an IBM PC/XT compatible machine. The circuit utilizes a 32.768 KHz clock reference and divides this to the normal 18.2 Hz(54.9 s) interrupt request IRQO used by the BIOS to keep time.
  • the PERIPHERAL ASIC can also generate interrupts at a much lower frequency, specifically, once every 56.2 seconds. This interrupt frequency, is to be used when the machine is idle in order to allow the machine to wake up to update time less frequently and therefore burn less power.
  • a set of registers, port F6E5h(LSB) and port F6E6h(MSB) hold the number of 54.9 ms increments. This provides the BIOS a way to insure that no time is lost if the computer wakes up and returns to the 54.9 ms timer interrupt frequency somewhere in the middle of the 56.2 second cycle. Since the value in ports F6E5 - F6E6h is free-running, it should be cleared before initiating a 56.2 second cycle. This may be accomplished by writing a one to bit 6 of port F6E4h. Returning bit 6 of port F6E4h to zero will allow incrementing to occur.
  • the PERIPHERAL ASIC is designed to interface to a 11 row by 7 column matrix keyboard.
  • the keyboard controller scans the keys by driving a single row low (to 0) and sampling the column inputs. If a key is down, the controller determines whether it is a new push or the key is just being held down. If it is a new push, the controller will generate the appropriate scan code and interrupt the processor via interrupt request, IRQ1. The controller will then suspend sampling until the interrupt is cleared by writing a one followed by a zero to bit 7 of port 0061h. Scan codes are read from port 0060h. Table 1 lists the scan code returned for each key in the 11 x 7 matrix. If no key is pushed the controller will continuously scan the keyboard until a key is detected.
  • the controller will repeatedly interrupt the processor. Keyboard repeat times are broken into two classifications, the time before the first repeat interrupt, and the time for subsequent repeat interrupts. Repeat times may be programmed by writing to bits 4 - 7 of port F6E0h. Table 2 shows the corresponding repeat times for values written to port F6E0h.
  • the keyboard controller runs off a 32.768 Khz clock, with each row being scanned approximately 256 times a second. Keyboard scanning may be. halted by writing a one to bit 6 of port 0061h. Writing a zero back to bit 6 of port 0061h will resume scanning where the controller left off.
  • the keyboard controller modifies the scan codes of certain keys depending upon the level of the PQKEYN input. This input, which is grounded when its corresponding key is pushed, will cause certain keys to return an alternate scan code. Table 1 lists the scan codes of those keys affected by the PQKEYN input. Table 2 lists keyboard repeat speeds.
  • Initial repeat time 625 ms. Initial repeat time of 375 ms. Initial repeat time of 281 ms. Initial repeat time of 187 ms. Subsequent repeat interval of 281 ms. Subsequent repeat interval of 187 ms. Subsequent repeat interval of 94 ms. Subsequent repeat interval of 47 ms.
  • the PERIPHERAL ASIC includes a MDA and CGA compatible display controller. It generates all needed signals, as well as refresh data to drive a 640 x 200 pixel LCD (liquid crystal display) .
  • the display controller in the PERIPHERAL ASIC may be disabled, allowing for an external controller by writing a one to bit 1 of port F6Elh.
  • the PERIPHERAL ASIC's display controller is enabled upon reset.
  • the PERIPHERAL ASIC's display controller may respond as either an MDA or a CGA video adapter. Writing a 0/1 to port F6E1 will select MDA/CGA compatibility.
  • the display controller is in MDA mode upon reset. Table 3 defines all the display modes supported by the display controller, including exceptions in compatibility, but functionally the controller has two primary modes of operation, graphics mode and text mode.
  • CGA graphics mode the screen is mapped into the processor memory space at addresses B8000 - BBFFFh in an interlaced fashion.
  • Each bit in the CGA memory space that is written high (i.e., 1) will appear black in its corre ⁇ sponding location on the screen, while each bit written low (i.e., 0) will appear white.
  • the CGA graphics mode standard calls for interlacing scan rows.
  • the first row of the screen resides at addresses B8000 - B804Fh, the second row at BA000 - BA04Fh, the third row at B8050 - B809F, and so on.
  • text mode the screen is broken into character locations, with a two byte address for each location.
  • the CPU writes ASCII codes for the character (even byte) and its corresponding attributes (odd byte) , and requires the controller to manage putting the character bit-map on the screen.
  • the display controller in the PERIPHERAL ASIC does this by mapping the screen into unused CPU memory space, BC000 - BFFFF, in a similar non-interlaced fashion to the graphics mode, and then copying each character's bit-map to the appropriate position in this "Bit-map" memory.
  • This approach allows the controller to refresh the screen using 1/4 the memory cycles needed by generating the characters "on the fly". This approach requires an extra 16 Kbytes of additional memory for display purposes.
  • the process of writing the character bit-maps to bit-map memory may be disabled by a write of a one to bit 3 of port F6Elh.
  • the PERIPHERAL ASIC enables automatic updating of bit-map memory upon reset.
  • Character bit maps are stored in ROM, along with a translation address, address of the character position in bit-map memory.
  • the memory map of video memory as well as the character ROM is included in Appendix A.
  • Character attributes with bit 7 high (1) indicate that the character should be blinking.
  • the controller recognizes when a blinking attribute is written to normal video memory and initiates a scan, or search, for characters with blinking attributes.
  • the CGA standard defines four 4 Kbyte pages of video memory in 80 x 25 text mode, and eight 2 Kbyte pages in 40 x 25 text mode. Only one page may be displayed on the screen at a time, however, the displayed page may be changed by a write to a CGA compatible I/O register.
  • the display controller on the PERIPHERAL ASIC preferably does not handle automatic page changes. Instead it accomplishes page changes by generating a nonmaskable interrupt (NMI) .
  • NMI nonmaskable interrupt
  • the CPU must then rewrite the newly selected memory page causing the bit-map memory to be updated.
  • Three bits indicating the current page may be read from port F6E7 bits 2-4. These bits denote the starting address in 2 Kbyte increments from the beginning of video memory.
  • the PERIPHERAL ASIC drives the display with the normal column, row, and frame clock signals.
  • the column clocks are signals used to shift data into the column drivers on the LCD.
  • the column clock outputs are at the same frequency as the display input clock, approximately 700 - 900 KHz and alternate activity every 40 clocks.
  • the row clock output is active once every 80 column clocks indicating a change in the row to be refreshed.
  • the frame clock is active once every 201 row clocks indicating the beginning of a new frame.
  • the frame clock is every 201 rows, because the controller can support refreshing an extra row of pixels, which may be used a status line, or not used at all.
  • the phase output signals (both polarities) toggle a programmable multiple of row clocks. This is to control problematic parasitic bleeding phenomena on the LCD display.
  • the number of row clocks per phase clock change is changed by writing bits 0-1 of port F6EDh.
  • a contrast signal is also generated by the PERIPHERAL ASIC for use in the LCD. This output is a variable duty-cycle 1 KHz signal. By writing to bits 0-3 of port F6E0h, the duty-cycle may be changed from 1/16, corresponding to Oh, up to 15/16, corresponding to both Eh and Fh.
  • the PERIPHERAL ASIC includes many features for managing power consumption including the ability to power down and disable parts of the machine and stop clocks. Included is the ability to determine when to disable features. To do this, four special NMI's are generated. The first NMI interrupts the processor when timer interrupt requests, IRQ0, have occurred. This give the BIOS the capability of timing events even when the normal timer interrupt vector has been stolen. The second NMI is generated on keyboard interrupt requests, IRQ1. These are used to monitor keyboard input and to allow support for special function keys not supported in the hardware. The third NMI is an interrupt when memory address 00058h has been read. This is an indication that the INT16h software interrupt has been called. This is used to determine if the system is idle.
  • the software may disable certain computer functions using special I/O ports,- thus lowering power consumption.
  • the final and most powerful NMI is the On/off key input. This comes from a key on the keyboard that notifies the BIOS that the user wishes to turn the system off. Lower power techniques using these features are disclosed in commonly assigned U.S. application serial no. 07/373,440, invented by Leroy D. Harper, et al., entitled COMPUTER POWER MANAGEMENT SYSTEM, attorney docket no. M-924, incorporated herein by reference.
  • the processor clock may be disabled with a write to port F6ECh bit 6 with a zero followed by a one.
  • the clock will stop low in the middle of the last I/O write cycle and remain low until an interrupt wakes it.
  • IRQ0, IRQ1, IRQ4, or NMI may wake the system, if enabled.
  • Each NMI has a mask bit in a special register and the IRQ's have a separate clock mask bit that will mask it from waking the processor, but not mask the interrupt request line from becoming active.
  • the UART clock may be stopped by writing a one to bit 7 of port F6ECh.
  • the charge pump on the RS-232 compatible drivers may be disabled by writing a one to bit 5 of port F6ECh.
  • the LCD display can be turned off by writing a one to bit 3 of port F6ECh. This also stops the display clock, refreshing, contrast and all associated signals.
  • the power supply voltage may be set to 5 Volts with a write of a zero to bit 2 of port F6ECh. This output will go to high impedance with a write of a one to bit 4 of port F6ECh forcing the power supply into automatic mode. In this mode, the power supply voltage will be set based on current consumption.
  • the PERIPHERAL ASIC performs various support functions that contribute to the functioning of the system, such as battery alarm, memory card detection, setting configuration dip switches, and the protection of a 32 Kbyte memory space as an internal disk drive.
  • a NMI is generated when a LOWBAT signal is active. This signal indicates that the system battery is either low or very low depending upon the value in bit 5 of port F6E4h.
  • the PERIPHERAL ASIC supports two memory cards to be used as either disk drives or executable memory. This support includes NMI's that notify software when they are being removed or inserted, or if the internal RAM card battery is low.
  • the prior art IBM PC/XT contained dip switches that were read to determine the system's configuration. These switches axe implemented in the present invention as latches that may be set by software to return the required value. This switch register is located at port F6E2h.
  • the PERIPHERAL ASIC includes the ability to replace the video character ROM with a 32 K x 8 SRAM. This enables the RAM to contain the bit-maps and translation addresses and still have 24 Kbytes free for an internal disk drive.
  • This memory is not normally present in the CPU memory space, but may be enabled by writing a one to bit 4 of port F6E4h. The memory will appear from A8000 - AFFFFh.
  • RS[0..15] LOW 71,72,37 Chip select signals for memory 73-85 residing at addresses from 00000h(RS0) - 7FFFFh(RS15) .
  • SMEMRN LOW 125 Signal that enables memory devices to drive data onto their corresponding data bus.
  • SIOWN LOW 128 Signal that indicates to I/O devices that data is available on the data bus.
  • IRQ[0..7] HIGH 8-10,12 Asynchronous interrupt request 13-15,34 signals to the interrupt controller. They should be held high until acknowledged.
  • DREQ[1..3] LOW 46-48 Asynchronous DMA request signals to the DMA controller. DREQ's should be held until they are acknowledged by the corresponding DACK.
  • SYSTEM ASIC chip 18 is the system manager. It comprises four major units, a bus controller, an interrupt controller, a memory manager and a direct memory access (DMA) controller.
  • the bus controller generates input/output and memory control signals.
  • the interrupt controller of SYSTEM ASIC 18 responds to interrupts from the PERIPHERAL ASIC 17, and interrupts from expansion port 23.
  • the direct memory access (DMA) controller in SYSTEM ASIC chip 18 controls access between memory 19 and input/output devices.
  • a schematic of block 18 is shown in Figures 11A to llAd.
  • the SYSTEM ASIC (application specific integrated circuit) is the second chip of a two chip implementation of an IBM PC/XT compatible. A complete PC/XT compatible system may be implemented with this chip, a PERIPHERAL ASIC 17 as described above, an Intel 8088 compatible CPU, and memory devices.
  • the SYSTEM ASIC supports 512 Kbytes of static RAM, and up to 8 Mbytes of memory in each of four additional devices.
  • the SYSTEM ASIC chip performs CPU and peripheral support functions including DMA control, interrupt control, bus control, and memory mapping.
  • the SYSTEM ASIC contains Intel 8237, 8259, and 8288, compatible circuits for support of DMA, interrupts, and bus control, respectively, as well as memory mapping circuitry unique to the PQ-XT.
  • the SYSTEM ASIC chip supports DMA through the use of an Intel 8237 compatible DMA controller and additional support circuitry.
  • the 8237 supports 4 independent DMA channels, three of which are available on the SYSTEM ASIC. Channel 0, normally used for DRAM refresh in the IBM PC/XT, is preferably not supported.
  • the 8237 registers are redundantly located at ports 0000 - OOOFh and 0010 - 001F, consistent with the IBM PC/XT implementation.
  • the SYSTEM ASIC chip supports two types of interrupts, normal system interrupts and NMI's (nonmaskable interrupts) .
  • Normal system interrupts are supported by an Intel 8259 compatible circuit. These system interrupts are supported in a hardware compatible manner to the IBM PC/XT, with the 8259 residing at ports 0020 - 0021h and redundantly up to port 003Fh.
  • NMI's may be generated by the assertion of the PERINTR pin coming from the PERIPHERAL ASIC, or from mapping two different physical pages into the same logical page with the memory mapping circuitry. All NMI's may be disabled using the IBM PC/XT compatible mask register at port OOAOh and redundantly to OOBFh.
  • the SYSTEM ASIC generates the memory and I/O control signals with the use of an Intel 8288 compatible circuit. This circuit decodes the processor status lines and generates the bus control signals ALE, MEMWRN, MEMRDN, IOWRN, and IORDN.
  • SYSTEM ASIC Also included in the SYSTEM ASIC is a 2-bit register that controls the automatic insertion of wait states.
  • the binary value of bits 0-1 written to port F6C3h causes the insertion of the corresponding number of wait states. Upon reset, no extra wait states are inserted. However, a single wait state is inserted on all I/O operations to remain consistent with the IBM PC/XT.
  • the SYSTEM ASIC interfaces to two external data buses , the EXPP[0..7] which is intended for use as an external I/O and expanded memory bus, and the RB1P[0..7], which is intended to interface to main memory. There are times when either or both of these data buses will not be actively driven.
  • the SYSTEM ASIC supports up to 512 Kbytes of 32K x 8 SRAM's at addresses 00000 - 7FFFFh, and 8 Mbytes of memory in each of four additional devices.
  • the SYSTEM ASIC supplies 16 chip select signals, RSO - RS15, for use with 32K x 8 SRAM's. RSO selects the lowest 32 Kbytes, followed by RSI and the other chip select signals.
  • the SYSTEM ASIC also supports mapping 64 Kbyte pages from any of four devices into the any of the four 64 Kbyte pages at addresses C0000 - CFFFFh, D0000 - DFFFFh, E0000 - EFFFFh, F0000 - FFFFFh.
  • the paging for each memory segment is accomplished with the use of two registers. The first is a four bit register used to select which of the four possible devices is to be mapped into the corresponding segment. Table 1 defines the function of each bit in the device mapping registers. The second is a seven bit register used to select which 64 Kbyte page within the selected device is to be mapped into the corresponding segment. This second register contains the top seven bits of a 23 bit address used when accessing the selected device.
  • each device may contain up to 8 Mbytes of memory.
  • Table 2 defines the function and port address of the device page registers.
  • the memory mapping circuit also generates a signal, DISEXPP, that is asserted on any bus cycle where memory mapping occurs. This signal is to be used to disable peripherals that respond to memory in the COO00 - FFFFFh memory space when a mapping operation is occurring. This signal is also asserted when bit 4 is set in the register at port F6E4h and an access to a memory location from A8000 - AFFFFh is in process. This is to disable peripherals that respond to A8000 - AFFFFh when accessing the protected memory supported by the PERIPHERAL ASIC. TABLE 5
  • the signal line is used to reset circuits within the System ASIC 18, and the processor 16.
  • a signal on this line is generated within the Peripheral ASIC 17 (where it is also used) and is a logical inversion of the signal on line MRESETN.
  • PERINTR Generated from the Peripheral Interrupt Control circuits within the Peripheral ASIC 17, the signal on this line is used to alert programs running on the processor 16 of various hardware and software conditions.
  • the signal connects to the System ASIC 18 where, if enabled within system ASIC 18, it can reach the processor 16 on the SNMI signal.
  • the System ASIC 18 is the gateway for all data to and from the processor 16. IRO ⁇ O..I.41
  • Interrupt request signals on line IRQO, IRQ1, and IRQ4 are all generated within the Peripheral ASIC 17 and corresponding to timer tick interrupt, keyboard interrupt, and UART interrupt, respectively.
  • the signals on these lines are connected to the pins IRO, IR1, and IR4 respectively of the 8259 compatible Programmable Interrupt Controller cell located within the System ASIC 18.
  • This line is used by the System ASIC 18 to synchronize slow data transfer with the processor 16. This line may reflect the condition of circuits within the System ASIC 18 itself, or the condition of the signal IOCHRDY from the Expansion Port 23. The signal on this line is routed through the Peripheral ASIC 17 before reaching the processor 16 on signal line CPURDY. SALE
  • the signal on this line is used internally by circuits within the System ASIC 18, those located within the Peripheral ASIC 17, and peripherals connected to the Expansion Port 23. This signal is used to strobe the address into the address latches and indicates that AAD[0..7] and AA[8..19] contain a valid address.
  • AEN Address latch enable
  • the Address Enable signal line from the 8237 compatible Programmable DMA controller cell within the System ASIC 18. When the signal on this line is high, it indicates that a DMA cycle is taking place. It is used internally by circuits within the System ASIC 18, those located within the Peripheral ASIC 17, and peripherals connected to the Expansion Port 23. SIORN
  • I/O read strobe signal is generated on this line by the 8288 Bus Controller compatible cell within the System ASIC 18. It is used internally by circuits within the System ASIC 18, those located with the Peripheral ASIC 17, and peripherals connected to the Expansion Port 23. When this line is low, it indicates that the processor 16 is requesting data from an I/O device. SIOWN
  • An I/O write strobe signal on this line generated by the 8288 Bus Controller compatible cell within the System ASIC 18. It is used internally by circuits within the System ASIC 18, those located with the Peripheral ASIC 17, and peripherals connected to the Expansion Port 23. When this line is low, it indicates that the processor 16 is writing data to an I/O device.
  • SMEMRN A memory read strobe signal on this line is generated by both the 8237 Programmable DMA Controller and the 8288 Bus Controller compatible cells within the System ASIC 18. When this line is low, it indicates a data Read Request from a memory device. It is used by circuits within the Peripheral ASIC 17, 512k System RAM 19, Memory Cards 22a and 22b, BIOS ROM 20, APPS ROM 21, and peripherals connected to the Expansion Port 23.
  • SMEMWN 512k System RAM 19
  • a memory write strobe signal is generated on this line by both the 8237 Programmable DMA Controller and the 8288 Bus Controller compatible cells within the System ASIC 18. It is used by circuits within the Peripheral ASIC 17, 512k System RAM 19, Memory Cards 22a and 22b, and peripherals connected to the Expansion Port 23. When this line is low, it indicates that data is to be written to a memory device.
  • RSPWRN Read Only Memory
  • This line carries a signal from the Peripheral ASIC 17 used to enable the power supply within the RS232/TTL Level Shifter 24. This signal is controlled by a bit within the Peripheral ASIC 17 which can be manipulated by the processor 16. When it is high, the power supply circuits are enabled. TTL OUT
  • These signal lines are SOUT, RTSN, and DTRN.
  • the signals on these lines are generated by the 16450 compatible UART within the Peripheral ASIC 17 and connect to TTL level inputs on the level shifter circuits in 24. The function of these signals is discussed in the data sheet for the 16450 UART available from National Semiconductor. TTL IN
  • signal lines are SIN, CTSN, DSRN, and DCDN.
  • the signals on these lines are translated from RS232 levels to TTL by the level shifter in 24 and presented to input pins of the 16450 compatible UART within the Peripheral ASIC 17. The function of these signals is discussed in the data sheet for the 16450 UART available from National Semiconductor. IQCHKN
  • the I/O channel line checks the signal from the Expansion Port 23 which is used to indicate a problem with a peripheral. This signal is monitored by the Peripheral ASIC 17 and may interact with software running on the processor 16. PERCLKN
  • This line indicates to the Peripheral ASIC 17 which source is to be used as the system clock, SYSCLK. When low, the VCO oscillator is used. When high, EXTSYSCLK is used. This signal is provided by the Expansion Port 23. EXTSYSCLK
  • This line carries the external input clock signal which may be used to derive the system clock SYSCLK if selected using signal PERCLKN from the Expansion Port 23. This signal is an input to the Peripheral ASIC 17.
  • BIOS ROM A ROM (read only memory) used to hold software which is nonvolatile and shipped with the computer. This ROM may contain BIOS control code, appli ⁇ cation programs, operating system files, and miscellaneous other data.
  • BIOS ROM 20 (or alternatively in other ROM in the computer) for a system serial number unique to each individual computer. This serial number is programmed into the read only memory at the time of manufacture and cannot be changed by the user. Access to the serial number is provided by means which are known to the user only by means of information provided by the manufacturer as described below.
  • serial number is useful for data entry and tracking at a repair center, for providing an additional level of security for the computer user for entry into an external secure local or remote network, for deterring theft and for allowing software vendors to serialize applications programs for individual computers.
  • the serial number is used by matching it with an external list of serial numbers.
  • indicator graphics 130 include legends 500, 502, etc. imprinted along the margin of the display 112. These legends such as 500, 502, are used in conjunction with an adjacent status line (not shown) located on the display 112 for indicating to the user the status of software programs and hardware conditions such as a low battery, caps lock, scroll lock, shift lock, or similar data.
  • an audio sound such as from a piezoelectric transducer (not shown) , is also used to direct the user's attention to the display indicators.
  • the computer also includes a second set of symbols such as 516, 518, 520, 524 as shown in Figure 9 imprinted on a margin of the keyboard 118a.
  • These symbols such as 516, 518, 520, 524 describe the functions of an adjacent row of keyboard function keys (not shown) .
  • four symbols in four different colors are provided adjacent each function key.
  • Keys for "shift”, “alt”, “ctrl”, and a special logo key are correspondingly colored to indicate that simultaneously pressing the "shift”, “alt”, “ctrl”, or the special logo key with the adjacent function key produces the functions noted in color by the symbol 502, 504, etc., adjacent to the function key.
  • Map device connected toEMCSO to EOOOO - FFFFFh 5 Map device connected toEMCS1 to EOOOO - FFFFFh 6 Map device connected toEMCS2 to EOOOO - FFFFFh
  • R W Oh corresponds to 1/16 duty cycle
  • OOh at Reset 1 h corresponds to 2/16 duty cycle,... Eh corresponds to 15/16 duty cycle, Fh corresponds to 15/16 duty cycle.
  • EXTRA input signal is active (high). ' LOWBAT input signal is active (high). PQKEYN input signal is active (low). ONOFFN input signal is active (low). PERCLKN input signal is active (low). EXTSYSCLK is in use. CALMAN input is active (low). CALMBN input is active (low). Display controller is in a state to which the system clock may be stopped.
  • CDET1 AN input is active (low).
  • CDET2AN input is active (low).
  • CDET1BN input is active low).
  • CDET2BN input is active (low).
  • LOWBAT signal indicates a dead battery
  • LOWBAT signal indicates a low battery Clear 54.9 ms increment counter. INT16h has been called since the last time NMI's were cleared.
  • IRQ1 keyboard interrupt has occurred since the last time NMI's were cleared.
  • Enable the video controller to generate an NMI when video display pages are changed.
  • Enable the PQKEYN signal to generate an NMI.
  • Enable the ONOFFN signal to generate an NMI.
  • Enable the IOCHKN signal to generate an NMI.
  • Enable both CALMAN and CALMBN to generate an NMI.
  • the display page register has been written since the last time NMI's were cleared.
  • the PERIPHERAL ASIC generated an NMI.
  • Signal CDET1 AN has made a 0-1 transition since the last time NMI's were cleared. Card a extended pin out-going NMI. Signal CDET1 AN has made a 1-0 transition since the last time NMI's were cleared. Card a extended pin in-coming NMI. Signal CDET2AN has made a 0-1 transition since the last time NMI's were cleared. Card a micro switch out-going NMI. Signal CDET2AN has made a 1-0 transition since the last time NMI's were cleared. Card a micro switch in-coming NMI. Signal CDET1BN has made a 0-1 transition since the last time NMI's were cleared. Card a extended pin out-going NMI.
  • Signal CDET1BN has made a 1-0 transition since the last time NMI's were cleared. Card a extended pin in-coming NMI. Signal CDET2BN has made a 0-1 transition since the last time NMI's were cleared. Card a micro switch out-going NMI. Signal CDET2BN has made a 1-0 transition since the last time NMI's were cleared. Card a micro switch in-coming NMI.
  • Timer generates IRQO's every 54.9 ms.
  • Timer generates IRQO's every 56.2 s.
  • LCDPWRN signal low (display power and clocks active).
  • LCDPWRN signal high (display power and clocks disabled).
  • SELVDD signal follows the polarity of
  • SELVDD signal is disabled to high impedance.
  • RWPWRN signal is low (RS-232 driver's charge pump is enabled).
  • RSPWRN signal is high (RS-232 driver's charge pump is disabled).
  • PHCLK/PHCLKN will change every 1 ROWCLK's.
  • PHCLK/PHCLKN will change every 2 ROWCLK's.
  • PHCLK/PHCLKN will change every 4 ROWCLK's.
  • PHCLK/PHCLKN will change every 8 ROWCLK's.
  • Value will be read from 0062h bit 4.
  • Value will be read from 0062h bit 6.
  • Value will be read from 0062h bit 7.

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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

L'invention se rapporte à un ordinateur (110a et 110b) portatif alimenté par batterie, qui comporte plusieurs caractéristiques permettant de concevoir l'ordinateur avec une petite taille et une faible consommation de courant, tout en lui conférant la fonctionnalité d'un ordinateur de taille normale.
EP90911349A 1989-06-30 1990-06-28 Ordinateur portatif compact Expired - Lifetime EP0479915B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US37572189A 1989-06-30 1989-06-30
US375721 1989-06-30
PCT/US1990/003639 WO1991000523A1 (fr) 1989-06-30 1990-06-28 Ordinateur portatif a faible consommation de courant

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JP (1) JPH05502124A (fr)
KR (1) KR970004081B1 (fr)
AU (1) AU6050790A (fr)
CA (1) CA2063558C (fr)
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US5752011A (en) * 1994-06-20 1998-05-12 Thomas; C. Douglas Method and system for controlling a processor's clock frequency in accordance with the processor's temperature
EP1016951A1 (fr) * 1998-11-12 2000-07-05 NTS Computer Systems R & D (Ireland) Limited Ordinateur portable
IE981043A1 (en) * 1998-11-12 2000-05-17 Nts Comp Systems R & D Ireland A Portable Computer
KR100829102B1 (ko) * 2001-08-30 2008-05-16 삼성전자주식회사 디스플레이패널 전원 공급용 배터리를 갖는 휴대용컴퓨터
DE102009046692A1 (de) * 2009-11-13 2011-05-19 Endress + Hauser Gmbh + Co. Kg Druck-Messeinrichtung

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Publication number Publication date
AU6050790A (en) 1991-01-17
CA2063558C (fr) 2000-08-15
CA2063558A1 (fr) 1990-12-31
EP0479915A4 (en) 1993-09-22
WO1991000523A1 (fr) 1991-01-10
EP0479915B1 (fr) 1999-08-18
KR970004081B1 (ko) 1997-03-25
DE69033254T2 (de) 2000-03-16
JPH05502124A (ja) 1993-04-15
KR920702775A (ko) 1992-10-06
DE69033254D1 (de) 1999-09-23

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