EP0466935A1 - Gerät zur anzeige von standbildern und dafür verwendete externe speicherkassette - Google Patents

Gerät zur anzeige von standbildern und dafür verwendete externe speicherkassette Download PDF

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Publication number
EP0466935A1
EP0466935A1 EP91903626A EP91903626A EP0466935A1 EP 0466935 A1 EP0466935 A1 EP 0466935A1 EP 91903626 A EP91903626 A EP 91903626A EP 91903626 A EP91903626 A EP 91903626A EP 0466935 A1 EP0466935 A1 EP 0466935A1
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EP
European Patent Office
Prior art keywords
character
storing means
data
writable
character code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91903626A
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English (en)
French (fr)
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EP0466935B1 (de
EP0466935A4 (en
Inventor
Katsuya Nintendo Co. Ltd. Nakagawa
Satoshi Nintendo Co. Ltd. Yamato
Hideki Nintendo Co. Ltd. Tanaka
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Nintendo Co Ltd
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Nintendo Co Ltd
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Publication of EP0466935A1 publication Critical patent/EP0466935A1/de
Publication of EP0466935A4 publication Critical patent/EP0466935A4/en
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Publication of EP0466935B1 publication Critical patent/EP0466935B1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/222—Control of the character-code memory

Definitions

  • the present invention relates to a still picture display apparatus and an external memory cartridge used therefor. More particularly, the present invention relates to a still picture display apparatus for combining a moving picture and a still picture and displaying an image on a laster scan type display, for example, a television game set, which is improved so as to remove the restriction in displaying a still picture in a text system and an external memory cartridge.
  • a character code of a character is written into a coordinate address of the VRAM corresponding to a position on the screen on which the character is to be displayed, and the character code is read out of the VRAM in synchronization with the scanning of the scan type display.
  • the character ROM is addressed by the character code, thereby to read the dot (font) data of the character out of the character ROM.
  • the dot data read out is converted into a video signal and the video signal is applied to the laster scan type display, thereby to display a still picture constituted by a desired character on a desired position on the screen.
  • the number of bits of a data bus of a CPU for image processing is increased to, for example, 16 and the number of bits of an address bus thereof is also increased, the number of characters which can be displayed on one screen can be increased to 2 16 . In this case, however, compatibility with the type of television game set being already put on the market is lost.
  • an object of the present invention is to provide a still picture display apparatus using a text system but capable of significantly relaxing the restriction of the representation of a still picture and improving the capability to represent an image.
  • Another object of the present invention is to provide an external memory cartridge used for a still picture display apparatus capable of significantly relaxing the restriction of the representation of a still picture and improving the capability to represent an image while maintaining compatibility with at least the existing image processing unit for displaying a still picture.
  • a still picture display apparatus comprises character storing means (which corresponds to a character memory 22 in an embodiment shown in Fig. 1), first writable/readable storing means (a VRAM 13), second writable/readable storing means (an EXRAM
  • An external memory cartridge according to the present invention is detachably mounted on a still picture display apparatus comprising first writable/readable storing means (a VRAM 13), write processing means (a CPU 11 and a PPU 12) and output processing means (a PPU 12), and comprises second writable/readable storing means (an EXRAM 25), program storing means (a program memory 21), writing means (an EXRAM write control circuit 23), reading means (an EXRAM read control circuit 24), and temporary storing means (a register 26).
  • first writable/readable storing means a VRAM 13
  • write processing means a CPU 11 and a PPU 12
  • output processing means a PPU 12
  • second writable/readable storing means an EXRAM 25
  • program storing means a program memory 21
  • writing means an EXRAM write control circuit 23
  • reading means an EXRAM read control circuit 24
  • temporary storing means a register 26
  • the above described character storing means is divided into a plurality of storage areas, and dot data (or font data or graphic data) of a character is stored in an address designated by a character code (or a character number) in each of the storage areas. Any one of the plurality of storage areas is designated by a higher order address of addresses applied to the character storing means, and a character code is applied as a lower order address.
  • the first writable/readable storing means is allocated first coordinate addresses corresponding to the above described sells on the screen of the scan type display. Into and out of each of the first coordinate addresses, a character code of a character to be displayed in the position is written by the first writing means and read out by the second reading means.
  • the second writable/readable storing means is also allocated second coordinate addresses corresponding to the cells on the screen of the scan type display, similarly to the first writable/readable storing means. Modifying data is written into the second coordinate address. The modifying data is read out by the first reading means and is temporarily stored in the temporary storing means.
  • the character code read out of the first writable/readable storing means and the modifying data temporarily stored in the temporary storing means are respectively applied as a lower order address and a higher order address to the character storing means. Consequently, dot data of a character designated by the character code is read out of the storage area designated by the modifying data in the character storing means and is applied to the output means. In the output means, the dot data is converted into a video signal and is applied to the scan type display.
  • the modifying data includes character modifying data and/or color modifying data.
  • the character modifying data is added as higher order bits of the character code to increase the number of characters which can be simultaneously displayed on one screen, and the color modifying data of, for example, two bits is applied for each character to allow a color to be designated for each dot.
  • the restriction of the representation of a still image can be significantly relaxed, and the capability to represent an image can be significantly improved.
  • a still picture display apparatus comprises a central processing unit (referred to as "CPU” hereinafter) 11, an image processing unit (referred to as “PPU” hereinafter) 12, and a VRAM 13 which is one example of first writable/readable storing means.
  • a program memory 21 which is one example of program storing means is connected to the CPU 11 through a CPU address bus 14 and a CPU data bus 15.
  • the VRAM 13 as well as a character memory 22 which is one example of character storing means are connected to the PPU 12 through a PPU address bus 16 and a PPU data bus 17.
  • the character memory 22 is divided into storage areas each having a relatively large space, and each of the storage areas is designated by a higher order address.
  • Dot (font) data (8 x 8 dots) of each of characters constituting a still picture is stored corresponding to character identification data or a character code in each of the storage areas.
  • the character code is applied as a lower order address, thereby allowing the dot data of the character to be read out.
  • the program memory 21 previously stores at least first program data for writing a character code into the VRAM 13, second program data for writing modifying data into an EXRAM 25 as described later, and third program data for reading out the character code and the modifying data.
  • the modifying data includes character modifying data when the present embodiment is applied for the purpose of increasing the number of characters, includes color modifying data when it is applied for the purpose of designating colors for each character, and includes both the character modifying data and the color modifying data when it is applied for the purposes of increasing the number of characters as well as designating colors for each character.
  • the character modifying data is used for significantly increasing the maximum number of characters by adding higher order bits to the character code in correlation with the number of the bits as added.
  • Color modifying data of two bits is added for each character in place of the conventional color data of two bits added for each four characters.
  • the color of each of dots constituting each of characters is designated by a combination of this color modifying data with color pallet data set separately therefrom.
  • the VRAM 13 has a plurality of coordinate addresses corresponding to character display positions on a screen of a laster scan type display (not shown). A character code of a desired character is written into each of the coordinate addresses, or the character code previously written into each of the coordinate addresses is read out.
  • a write control circuit for an extended RAM (referred to as “EXRAM” hereinafter) (referred to as “write control circuit” hereinafter) 23 which is one example of second writing means and a read control circuit for an EXRAM (referred to as “read control circuit") 24 which is one example of reading means are respectively connected to the address buses 14 and 16 of the CPU 11 and the PPU 12.
  • the PPU 12 as well as the EXRAM 25 are connected to the data bus 15 of the CPU 11.
  • the EXRAM 25 has a capacity capable of storing modifying data corresponding to character codes on one still picture cell stored in the VRAM 13, and is allocated addresses corresponding to the addresses of the VRAM 13. Modifying data can be written into or read out of each of the addresses.
  • Write address data outputted from the write control circuit 23 and various signals for write control are applied to the EXRAM 25, and read address data outputted from the read control circuit 24 and various signals for read control are applied thereto. Modifying data for each character are sequentially read out of the EXRAM 25, and are loaded into a register 26 which is one example of temporary storing means.
  • Character modifying data (for example, lower order six bits) in the modifying data loaded into the register 26 is applied as a higher order address of the character memory 22.
  • color modifying data (for example, higher order two bits) is applied to the PPU data bus 17 through a bus buffer 27 as required.
  • the bus buffer 27 can be omitted.
  • a vertical blanking period of a laster scan type display (not shown), the CPU 11 applies address data for designating a character code to the program memory 21 on the basis of a program of the program memory 21 and reads out the character code to apply the same to the PPU 12.
  • This character code is written into a coordinate address of the VRAM 13 corresponding to a position on the screen of the laster scan type display on which the character is to be displayed.
  • the CPU 11 applies write address data to the write control circuit 23 through the address bus 14 so as to write modifying data (character modifying data and/or color modifying data) corresponding to the character code at arbitrary timing and at the same time, applies the character modifying data and/or the color modifying data to the EXRAM 25 through the data bus 15.
  • the write control circuit 23 detects the application of an address for designating the EXRAM 25 and outputs a write signal W and at the same time, generates write address data to apply the same to the EXRAM 25. Consequently, the modifying data outputted from the above described CPU 11 is stored in the address designated by the write control circuit 23 of the EXRAM 25.
  • the PPU 12 addresses the VRAM 13 in synchronization with the scanning to read out a character code.
  • the character code is applied to the character memory 22 as a lower order address (PAO to PA9) for reading out font data (dot data of eight dots in the horizontal direction constituting one character) in the character memory 22, and is applied to the read control circuit 24.
  • the read control circuit 24 applies to the EXRAM 25 read address data corresponding to the character code, to read out modifying data.
  • This modifying data is temporarily stored in the register 26. Character modifying data in the modifying data stored in the register 26 is applied as a higher order address to the character memory 22.
  • the character memory 22 includes a memory space determined by the character modifying data applied as a higher order address, and outputs dot data addressed by the character code applied as a lower order address to apply the same to the PPU 12.
  • the color modifying data stored in the register 26 is applied to the PPU data bus 17 through the bus buffer 27.
  • the PPU 12 outputs a color video signal (a PGB signal or an AV signal or a television signal) on the basis of the font data and the color modifying data, to apply the same to the laster scan type display.
  • the CPU 11 can also change the modifying data.
  • Fig. 2 is a block diagram showing in principle an external memory cartridge applied to such a still picture display apparatus.
  • An embodiment shown in Fig. 2 is the same as the embodiment shown in Fig. 1 in that a still picture display apparatus is divided into a television game set 10 which is one example of an image processing unit and an external memory cartridge 20, and the external memory cartridge 20 is constructed detachably from the television game set 10. Consequently, the television game set 10 comprises a CPU 11, a PPU 12 and a VRAM 13, and is further provided with a connector 18 for connecting the CPU 11 and the PPU 12 to the external memory cartridge 20.
  • the external memory cartridge 20 comprises a substrate (not shown) having a plurality of terminals electrically connected to the television game set 10 formed thereon when it is inserted into the connector 18.
  • a program memory 21, a character memory 22, a write control circuit 23, a read control circuit 24, an EXRAM 25 and a register 26 shown in Fig. 1 are mounted on the substrate, and the respective circuits are connected through address buses 14a and 16a as well as data buses 15a and 17a and the other buses or signal lines in the same manner as that shown in Fig. 1.
  • Fig. 3 is a block diagram showing still another embodiment of the present invention.
  • the embodiment shown in Fig. 3 is the same as that shown in Fig. 1 in that a still picture display apparatus is divided into a television game set 10 which is one example of an image processing unit, and an external memory cartridge 20A and an adaptor 30, and the entire circuit is constructed by inserting the external memory cartridge 20A into the adaptor 30 with the adapter 30 being inserted into the television game set 10. Consequently, the adaptor 30 is constructed detachably from the television games set 10, and the external memory cartridge 20A is constructed detachably from the adaptor 30.
  • a program memory 21 and a character memory 22 are provided on a substrate (not shown) in the external memory cartridge 20A in the same manner as that in the prior art.
  • a write control circuit 23, a read control circuit 24, an EXRAM 25, a register 26 and a connector 31 are mounted on a printed board (not shown) in the adaptor 30. Consequently, in the present embodiment, a circuit equivalent to the external memory cartridge 20 shown in Fig. 2 is constructed by combining the external memory cartridge 20A and the adaptor 30.
  • program data stored in the program memory 21 includes modifying data and data for transferring the modifying data, as in the embodiment shown in Fig. 1.
  • one adaptor 30A is shared by different external memory cartridges 20A, thereby to make it possible to achieve an improved still picture display apparatus at low cost.
  • a television game set 10 comprises an address decoder 19 for detecting the selection of a program memory 21 on the basis of address data, unlike the embodiment shown in Fig. 2.
  • an external memory cartridge 20 comprises the same circuits as those in the embodiment shown in Fig. 2.
  • a character memory (CH-ROM) 22 out of the circuits has a plurality of memory spaces each storing dot data of 256 characters. Each of the memory spaces is designated by a higher order address of six bits, and it is determined by a lower order address of eight bits which dot data in each of the memory spaces is to be designated.
  • a combination of four types of colors is selected for each character from the maximum number of colors which can be represented by the television game set 10 by color pallet data, and which color of the four colors selected by the color pallet data is to be used to display any one of the dots is determined by the above described data "00", "01 ", "10” and "11 ".
  • a write control circuit 23 in the external memory cartridge 20 comprises an address decoder 231, a mode register 232, an address bus selector 234 and an NAND gate 235.
  • the address decoder 231 is used for detecting the selection of an EXRAM 25 on the basis of address data from a CPU 11 (for example, 5COOH to 5FFFH; where the last H indicates hexadecimal notation).
  • the mode register 232 is used for storing a write mode or a read mode of the EXRAM 25.
  • the address bus selector 234 is used for switching a write address and a read address by connecting an address bus 15 to an address bus of the EXRAM 25 in the write mode while connecting an address bus 16 to the address bus of the EXRAM 25 in the read mode.
  • the AND gate 235 is used for detecting the write conditions of the EXRAM 25 and applying a write enable signal EXWE to the EXRAM 25.
  • a read control circuit 24 comprises an address decoder 241, AND gates 242, 243 and 245, and an AND gate 244.
  • the address decoder 241 is used for detecting a color address (a color pallet selection signal) on the basis of address data from a PPU 12.
  • the AND gate 242 is used for detecting a signal (COLAD-) representing the read mode of the EXRAM 25 and the timing when color modifying data is to be read out.
  • the AND gate 243 enables a bus buffer 27 and provides outputs D6 to D7 of a register 26 to a data bus 17a as color pallet selection data provided that no output of the AND gate 242 is obtained, there is an address PA13, and the PPU 12 is performing a reading operation.
  • the AND gates 244 and 245 are used for detecting the timing when certain character modifying data stored in the EXRAM 25 is to be loaded into the register 26.
  • Modifying data (EXDO to EXD7) corresponding to a character code designated by a read address is loaded into the register 26.
  • the register 26 is used for loading character modifying data by lower order six bits (DO to D5) and loading color modifying data by higher order two bits (D6 and D7), as shown in Fig. 5.
  • the character modifying data in the modifying data loaded into the register 26 is applied as a higher order address (MPA12 to MPA17), and the color modifying data is applied to the bus buffer 27.
  • the details of an operation of the CPU 11 writing modifying data (character modifying data and/or color modifier data) corresponding to a character code to the EXRAM 25 at arbitrary timing are as follows. More specifically, the CPU 11 applies a selection signal of the program memory 21 to the address decoder 19 and applies address data for reading out second program data to the program memory 21. The CPU 11 outputs an address (for example, 5104H) for designating the mode register 232 and mode data (DO to D1) representing the write mode on the basis of the second program data.
  • the address decoder 231 applies a write signal to the mode register 232, so that the mode register 232 loads data for designating the write mode.
  • the mode register 232 applies a signal representing a write (CPU) mode to the address bus selector 234 and the AND gate 235, so that the address bus selector 234 is switched to the side of a CPU address bus 14a.
  • the CPU 11 applies write address data of the EXRAM 15 to the address bus selector 234 through an address bus 14, and applies character modifying data and/or color modifying data as write data to the EXRAM 25 through the data bus 15.
  • a write enable signal from the AND gate 235 is applied to the EXRAM 25.
  • the modifying data is written into the designated address of the EXRAM 25.
  • the PPU 12 sequentially reads out for each character a character code, color modifying data, data of eight dots in the horizontal direction for the front font constituting the designated character, and data of eight dots in the horizontal direction for the back font constituting the character in synchronization with the horizontal scanning of the laster scan type display, as shown in Fig. 6. Meanwhile, the character modifying data is read out at the same timing as the timing when a character code is to be read out.
  • the PPU 12 brings the address PA13 for designating the VRAM 13 into a high level and at the same time, applies the address PA13 to the character memory 22, the address bus selector 234 and the address decoder 141 as a lower order address (PAO to PA11) for designating a character code through address buses 16 and 16a.
  • the address decoder 241 and the AND gate 242 detect the timing when no color modifying data is to be read out, and the AND gate 244 applies an enable signal (CS-) to the VRAM 13, so that the character code is read out by the PPU 12 in synchronization with a read signal (RD-).
  • the enable signal (CS-) of the AND gate 244 is also applied to the AND gate 245. Since an output (COLAD-) of the address decoder 241 is not in an enable state, the AND gate 245 generates a latch command signal (L) to the register 26 in synchronization with the read signal. Character modifying data and color modifying data are loaded into the register 26 in response to this latch command signal.
  • the PPU 12 outputs a read signal (RD-) and at the same time, applies a character code to the character memory 22 as a lower order address (PAO to PA9) through the address buses 16 and 16a.
  • character modifying data loaded into the register 26 for example, MPA 12 to 17 is applied to the character memory 22 as a higher order address.
  • the PPU 12 applies address data for designating reading of color selection data to the address decoder 241 as a lower order address (PAO to PAl 1) through the address buses 16 and 16a.
  • the address decoder 241 detects the timing when color modifying data is to be read out, and the AND gates 242 and 243 apply an enable signal (E) to the bus buffer 27 in synchronization with the read signal, so that color modifying data is applied to the PPU 12 in synchronization with the read signal (RD-).
  • an output (a selection signal CS-) of the AND gate 242 is in an inactive state, so that the VRAM is not enabled.
  • a character is selected by a combination of the higher order address designated by the character modifying data and the lower order address designated by a PPU address, so that data of the character on one line for the front font and the back font (dot data of eight dots in the horizontal direction constituting one character) is read out and is applied to the PPU 12.
  • two bits (D6 and D7) of the color modifying data in the modifying data loaded into the register 26 are extended to eight bits by the bus buffer 27 and are applied to the PPU 22 through the PPU data buses 17a and 17. Consequently, the PPU 12 generates a color video signal on the basis of data of two bits per dot for the front font and the back font and outputs the same to the laster scan type display (not shown).
  • the foregoing reading or outputting operation is repeated for each character in synchronization with the horizontal scanning of the laster scan type display during one frame period.
  • the present embodiment has advantages superior to the conventional bank switching technique. More specifically, in the conventional bank switching technique, the PPU 12 must regularly monitor bank switching timing (S) so as to switch banks from the beginning of the next horizontal scanning, as shown in Fig. 7. On the other hand, according to the present embodiment, no monitoring of bank switching timing is required, not to increase the burden on the PPU 12.
EP91903626A 1990-02-02 1991-02-01 Gerät zur anzeige von standbildern und dafür verwendete externe speicherkassette Expired - Lifetime EP0466935B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2024715A JP2955760B2 (ja) 1990-02-02 1990-02-02 背景画表示制御装置およびそれに用いられる外部メモリカードリッジ
JP24715/90 1990-02-02
PCT/JP1991/000128 WO1991011798A1 (fr) 1990-02-02 1991-02-01 Dispositif d'affichage d'images immobiles et cartouche de memoire externe utilisee avec un tel dispositif

Publications (3)

Publication Number Publication Date
EP0466935A1 true EP0466935A1 (de) 1992-01-22
EP0466935A4 EP0466935A4 (en) 1993-02-24
EP0466935B1 EP0466935B1 (de) 1996-04-10

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EP91903626A Expired - Lifetime EP0466935B1 (de) 1990-02-02 1991-02-01 Gerät zur anzeige von standbildern und dafür verwendete externe speicherkassette

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Country Link
EP (1) EP0466935B1 (de)
JP (1) JP2955760B2 (de)
KR (1) KR0175142B1 (de)
AT (1) ATE136677T1 (de)
AU (1) AU648540B2 (de)
BR (1) BR9104306A (de)
CA (1) CA2050279C (de)
DE (1) DE69118599T2 (de)
ES (1) ES2088484T3 (de)
WO (1) WO1991011798A1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5599232A (en) * 1992-05-02 1997-02-04 Codemasters Limited Memory cartridge with interface having graphics co-processor
EP0761265A1 (de) * 1994-12-30 1997-03-12 Sega Enterprises, Ltd. Videospielsystem zur spielsimulation eines comicheftes
EP0969444A1 (de) * 1998-07-03 2000-01-05 THOMSON multimedia Einrichtung zur Ansteuerung von Zeichen in einem Videosystem

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US4180805A (en) * 1977-04-06 1979-12-25 Texas Instruments Incorporated System for displaying character and graphic information on a color video display with unique multiple memory arrangement
US4368461A (en) * 1979-12-03 1983-01-11 Hitachi, Ltd. Digital data processing device
DE3346458A1 (de) * 1982-12-22 1984-06-28 Nintendo Co. Ltd., Kyoto Bildverarbeitungssystem
EP0351912A1 (de) * 1988-07-20 1990-01-24 Philips Electronics Uk Limited Videotextdekodierer

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JPS56133790A (en) * 1980-03-24 1981-10-20 Fujitsu Ltd Pattern code adding system
JP2769345B2 (ja) * 1989-02-21 1998-06-25 三菱電機株式会社 表示制御装置

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Publication number Priority date Publication date Assignee Title
US4180805A (en) * 1977-04-06 1979-12-25 Texas Instruments Incorporated System for displaying character and graphic information on a color video display with unique multiple memory arrangement
US4368461A (en) * 1979-12-03 1983-01-11 Hitachi, Ltd. Digital data processing device
DE3346458A1 (de) * 1982-12-22 1984-06-28 Nintendo Co. Ltd., Kyoto Bildverarbeitungssystem
EP0351912A1 (de) * 1988-07-20 1990-01-24 Philips Electronics Uk Limited Videotextdekodierer

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Title
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5599232A (en) * 1992-05-02 1997-02-04 Codemasters Limited Memory cartridge with interface having graphics co-processor
EP0761265A1 (de) * 1994-12-30 1997-03-12 Sega Enterprises, Ltd. Videospielsystem zur spielsimulation eines comicheftes
EP0761265A4 (de) * 1994-12-30 2005-03-16 Sega Corp Videospielsystem zur spielsimulation eines comicheftes
EP0969444A1 (de) * 1998-07-03 2000-01-05 THOMSON multimedia Einrichtung zur Ansteuerung von Zeichen in einem Videosystem
FR2780804A1 (fr) * 1998-07-03 2000-01-07 Thomson Multimedia Sa Dispositif de controle de l'affichage de caracteres dans un systeme video
US6630966B1 (en) 1998-07-03 2003-10-07 Thomson Licensing S.A. Device for controlling the displaying of characters in a video system

Also Published As

Publication number Publication date
ES2088484T3 (es) 1996-08-16
JP2955760B2 (ja) 1999-10-04
KR920701937A (ko) 1992-08-12
JPH0418598A (ja) 1992-01-22
ATE136677T1 (de) 1996-04-15
BR9104306A (pt) 1992-03-03
WO1991011798A1 (fr) 1991-08-08
KR0175142B1 (ko) 1999-05-01
EP0466935B1 (de) 1996-04-10
DE69118599D1 (de) 1996-05-15
CA2050279C (en) 1996-03-05
AU7185991A (en) 1991-08-21
EP0466935A4 (en) 1993-02-24
AU648540B2 (en) 1994-04-28
DE69118599T2 (de) 1996-09-19

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