EP0461240A4 - Methods and apparatus for efficient resource allocation for error and exception handling in convergent division - Google Patents

Methods and apparatus for efficient resource allocation for error and exception handling in convergent division

Info

Publication number
EP0461240A4
EP0461240A4 EP19910902487 EP91902487A EP0461240A4 EP 0461240 A4 EP0461240 A4 EP 0461240A4 EP 19910902487 EP19910902487 EP 19910902487 EP 91902487 A EP91902487 A EP 91902487A EP 0461240 A4 EP0461240 A4 EP 0461240A4
Authority
EP
European Patent Office
Prior art keywords
value
input value
seed
input
convergence function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19910902487
Other languages
English (en)
Other versions
EP0461240A1 (fr
Inventor
Brett Louis Lindsley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0461240A1 publication Critical patent/EP0461240A1/fr
Publication of EP0461240A4 publication Critical patent/EP0461240A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
    • G06F2207/5355—Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/487—Multiplying; Dividing
    • G06F7/4873—Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/49926—Division by zero

Definitions

  • efficient resource allocation together with an appropriate mapping of data input, allow processing of all data inputs in a continuous, accurate, and efficient manner in a digital computer such as a digital signal processor utilizing a computer program storage medium having a computer program stored thereon that modifies and propagates data inputs through a convergent division algorithm.
  • a divisor input is assigned a seed value according to a predetermined categorization of divisor inputs, and is modified to indicate a divisor value suitable for efficient propagation through a convergent division algorithm.
  • This selection of two feasible values for implementation of the convergent division algorithm is a useful preliminary determination for efficient computation.
  • the solution of a convergent division algorithm for all inputs by careful choice of seed values and modified divisor values constrains the computation to a substantially shorter duration than in the past, improving cost- effectiveness of signal processing. Utilization of fewer resources to allocate the seed values and to modify the divisors also is cost-effective.
  • Figure 1 is a general flow chart depicting implementation of a floating-point division algorithm under the prior art.
  • Figure 2 is a flow chart of an implementation of the invention wherein a seed and a modified input value are assigned in parallel.
  • Figure 3 is a flow chart of an implementation of the invention wherein a seed and a modified input value are assigned in series.
  • Figure 4 is a block diagram of a computer hardware implementation of the invention.
  • Figure 5 is a table setting forth the error matrix achieved without exception correction, according to the prior art.
  • Figure 6 is a table setting forth an application of the present invention for exception correction.
  • Figure 7 is a table illustrating the output seed and corrected divisor for a given input divisor according to the present invention.
  • FIG. 1 is a graphical representation, depicted generally by the numeral 100, of the constraints on an implementation of floating-point division, according to the prior art.
  • a programming model may provide a division mode utilizing two numbers, N and D (102), typically represented in the floating-point number form.
  • the program determines whether or not a divisor D is zero (104). If the divisor D is zero (104), the program may substitute a very small number for the divisor so that division may continue (106), or may skip division altogether (105).
  • the program may determine whether or not the divisor is infinity (108). If the divisor is infinity (108), the program may substitute a very large number so that division may continue (106), or may skip division altogether (109). Following the check for division by zero and for division by infinity, the program executes the division algorithm (110) in accordance with prior art technique.
  • the program checks to see whether or not the desired degree of accuracy has been reached (112). If insufficient accuracy has been attained, the program recycles to repeat the division algorithm computation (110) until the desired degree of accuracy is obtained (112), then stops. If the desired degree of accuracy has already been attained (112), the program stops.
  • FIG. 2 illustrates the steps executed by a programming model incorporating the present invention, wherein the implementation of a mapping of an input value D to a seed S and a modified input value D occurs in parallel, depicted generally by the numeral 200.
  • the program obtains an input value D and a second value, N, related to the first value, for a division algorithm computation (202).
  • the program checks for a plus or minus zero input value D, implemented as a divisor (104). If the divisor D is plus or minus zero, a seed S is assigned a corresponding infinity value with the same sign as D and a modified input value D, implemented as a divisor, is assigned a non-zero value with the opposite sign as the seed S (208), -S being a workable value.
  • the program checks to see if the input value D, implemented as a divisor, is plus or minus infinity (108). If the divisor D is plus or minus infinity, a seed S is set to a corresponding plus or minus zero and a modified input value D, implemented as a divisor, is assigned a non-infinite number (210), S being a workable value. If the divisor D is not plus or minus infinity, the divisor D may be a plus or minus normalized or denormalized number according to the IEEE 754-1985 standard.
  • a seed S is set to an approximation corresponding to plus or minus 1/D and the divisor D remains the same (212).
  • the checking for division by zero (104) and for division by infinity (108) may be accomplished in alternate order if desired. In this embodiment all arithmetic operations, addition, subtraction, and multiplication, conform to the IEEE 754-1985 standard for binary floating-point arithmetic.
  • the second value N and the divisor D, modified or unchanged are each premultiplied by the seed value S (214), yielding a numerator and a denominator, respectively.
  • a convergence function value f1 is obtained by subtracting the denominator from the value 2.0.
  • the program multiplies both the numerator and the denominator by the convergence function value f1 , obtaining a quotient having a next numerator and a next denominator, respectively (110).
  • the next denominator is subtracted from 2.0, yielding a next convergence function value, f2.
  • ⁇ D * S * fl * f2 is utilized in this invention, and a convergence factor f is obtained by subtracting the modified divisor D from the value 2.0.
  • the approximated seed S must have a value such that D * S is less than 2.0.
  • FIG. 3 illustrates the steps executed by a programming model incorporating the present invention wherein the implementation of a mapping of an input value D to a seed S and a modified input value D occurs in series, depicted generally by the numeral 300.
  • the program obtains an input value D and a second value, N, related to the first value, for a division algorithm computation (202).
  • the program checks for a plus or minus zero input value D, implemented as a divisor (104). If the divisor D is plus or minus zero, a seed S is assigned a corresponding plus or minus infinity value (308). If the divisor D is not plus or minus zero (104), the program checks to see if the divisor D is plus or minus infinity (108).
  • a seed S is set to a corresponding plus or minus zero (310). If the divisor D is not plus or minus infinity (108), a corresponding seed S is set to an approximation of plus or minus 1/D (312).
  • the checking for division by zero (104) and for division by infinity (108) may be accomplished in alternate order if desired.
  • the program now checks to see if the seed value S is plus or minus zero (314). If the seed value S is plus or minus zero, or alternatively, since S is directly related to D, if a divisor D is equal to plus or minus infinity, a modified input value D, implemented as a divisor, is assigned a non-infinite number (318), S being a workable value . If the seed value S is not plus or minus zero (314), the program checks to see if the seed value S is plus or minus infinity (316).
  • a divisor D is equal to plus or minus zero (316)
  • a modified input value D is assigned a non-zero value with the opposite sign of S (320), -S being a workable value. If the seed value S is not plus or minus infinity (316), the divisor value remains the same (322).
  • FIG. 4 illustrates a hardware implementation of the present invention, generally depicted by the numeral 400.
  • a computer program for implementation of the present invention may be stored in the program memory (404), other memory (412), or may be embodied in hardware in the ALU (406).
  • the program control unit (402) utilizes the bus (410) to select the program to implement the present invention, and the status register (408) determines whether division by zero or by infinity is taking place.
  • the ALU (406) performs the previously described manipulations of values in application of the convergent division algorithm set forth above.
  • the ALU (406) generates an initial seed S with a mantissa that is stored in 8 binary bits of memory.
  • Figure 5 illustrates the prior art, setting forth the error matrix achieved without exception correction.
  • This prior art implementation allows all operands to propagate through the quadratic convergent algorithm without any operand checking. Division by zero or division by infinity results in a NaN, a result that is inconsistent with the IEEE 754-1985 floating point standard.
  • Figure 6 depicts application of the present invention for exception correction.
  • the operands are modified according to the present invention, and the modified operands propagate through the quadratic convergent division algorithm using IEEE 754-1985 arithmetic, outputting quotient and exception results, including signs for zeros and infinities for exception cases, in accordance with the IEEE 754-1985 floating point standard.
  • Figure 7 illustrates the output seed and corrected divisor for a given input divisor according to the present invention.

Abstract

Procédé utilisant une seule étape de prétraitement (214, 216) afin de modifier un diviseur (D) en division à point flottant, et afin de valider une opération de correction d'exception et de contrôle d'erreurs (104, 108) ayant lieu simultanément avec une opération de division. L'invention permet d'obtenir le résultat prédéterminé correct s'il existe une exception, ou le quotient si aucune exception ne se produit.
EP19910902487 1989-12-29 1990-12-17 Methods and apparatus for efficient resource allocation for error and exception handling in convergent division Withdrawn EP0461240A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45909089A 1989-12-29 1989-12-29
US459090 1989-12-29

Publications (2)

Publication Number Publication Date
EP0461240A1 EP0461240A1 (fr) 1991-12-18
EP0461240A4 true EP0461240A4 (en) 1993-08-11

Family

ID=23823363

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19910902487 Withdrawn EP0461240A4 (en) 1989-12-29 1990-12-17 Methods and apparatus for efficient resource allocation for error and exception handling in convergent division

Country Status (5)

Country Link
EP (1) EP0461240A4 (fr)
JP (1) JPH04504774A (fr)
KR (1) KR940008617B1 (fr)
CA (1) CA2047180A1 (fr)
WO (1) WO1991010190A1 (fr)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0377992A2 (fr) * 1989-01-13 1990-07-18 International Business Machines Corporation Méthode et dispositif de division à virgule flottante

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4724529A (en) * 1985-02-14 1988-02-09 Prime Computer, Inc. Method and apparatus for numerical division

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0377992A2 (fr) * 1989-01-13 1990-07-18 International Business Machines Corporation Méthode et dispositif de division à virgule flottante

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of WO9110190A1 *
WEITEK APPLICATION NOTE 'WTL 1032/1033 Floating Point Division/Square Root/ IEEE Arithmetic' 1983 , WEITEK CORPORATION , SANTA CLARA, CA, USA *

Also Published As

Publication number Publication date
KR940008617B1 (ko) 1994-09-24
JPH04504774A (ja) 1992-08-20
WO1991010190A1 (fr) 1991-07-11
CA2047180A1 (fr) 1991-06-30
EP0461240A1 (fr) 1991-12-18
KR920701904A (ko) 1992-08-12

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