EP0461240A4 - Methods and apparatus for efficient resource allocation for error and exception handling in convergent division - Google Patents

Methods and apparatus for efficient resource allocation for error and exception handling in convergent division

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Publication number
EP0461240A4
EP0461240A4 EP19910902487 EP91902487A EP0461240A4 EP 0461240 A4 EP0461240 A4 EP 0461240A4 EP 19910902487 EP19910902487 EP 19910902487 EP 91902487 A EP91902487 A EP 91902487A EP 0461240 A4 EP0461240 A4 EP 0461240A4
Authority
EP
European Patent Office
Prior art keywords
value
input value
seed
input
convergence function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19910902487
Other languages
French (fr)
Other versions
EP0461240A1 (en
Inventor
Brett Louis Lindsley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
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Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0461240A1 publication Critical patent/EP0461240A1/en
Publication of EP0461240A4 publication Critical patent/EP0461240A4/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
    • G06F2207/5355—Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/487—Multiplying; Dividing
    • G06F7/4873—Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/49926—Division by zero

Definitions

  • efficient resource allocation together with an appropriate mapping of data input, allow processing of all data inputs in a continuous, accurate, and efficient manner in a digital computer such as a digital signal processor utilizing a computer program storage medium having a computer program stored thereon that modifies and propagates data inputs through a convergent division algorithm.
  • a divisor input is assigned a seed value according to a predetermined categorization of divisor inputs, and is modified to indicate a divisor value suitable for efficient propagation through a convergent division algorithm.
  • This selection of two feasible values for implementation of the convergent division algorithm is a useful preliminary determination for efficient computation.
  • the solution of a convergent division algorithm for all inputs by careful choice of seed values and modified divisor values constrains the computation to a substantially shorter duration than in the past, improving cost- effectiveness of signal processing. Utilization of fewer resources to allocate the seed values and to modify the divisors also is cost-effective.
  • Figure 1 is a general flow chart depicting implementation of a floating-point division algorithm under the prior art.
  • Figure 2 is a flow chart of an implementation of the invention wherein a seed and a modified input value are assigned in parallel.
  • Figure 3 is a flow chart of an implementation of the invention wherein a seed and a modified input value are assigned in series.
  • Figure 4 is a block diagram of a computer hardware implementation of the invention.
  • Figure 5 is a table setting forth the error matrix achieved without exception correction, according to the prior art.
  • Figure 6 is a table setting forth an application of the present invention for exception correction.
  • Figure 7 is a table illustrating the output seed and corrected divisor for a given input divisor according to the present invention.
  • FIG. 1 is a graphical representation, depicted generally by the numeral 100, of the constraints on an implementation of floating-point division, according to the prior art.
  • a programming model may provide a division mode utilizing two numbers, N and D (102), typically represented in the floating-point number form.
  • the program determines whether or not a divisor D is zero (104). If the divisor D is zero (104), the program may substitute a very small number for the divisor so that division may continue (106), or may skip division altogether (105).
  • the program may determine whether or not the divisor is infinity (108). If the divisor is infinity (108), the program may substitute a very large number so that division may continue (106), or may skip division altogether (109). Following the check for division by zero and for division by infinity, the program executes the division algorithm (110) in accordance with prior art technique.
  • the program checks to see whether or not the desired degree of accuracy has been reached (112). If insufficient accuracy has been attained, the program recycles to repeat the division algorithm computation (110) until the desired degree of accuracy is obtained (112), then stops. If the desired degree of accuracy has already been attained (112), the program stops.
  • FIG. 2 illustrates the steps executed by a programming model incorporating the present invention, wherein the implementation of a mapping of an input value D to a seed S and a modified input value D occurs in parallel, depicted generally by the numeral 200.
  • the program obtains an input value D and a second value, N, related to the first value, for a division algorithm computation (202).
  • the program checks for a plus or minus zero input value D, implemented as a divisor (104). If the divisor D is plus or minus zero, a seed S is assigned a corresponding infinity value with the same sign as D and a modified input value D, implemented as a divisor, is assigned a non-zero value with the opposite sign as the seed S (208), -S being a workable value.
  • the program checks to see if the input value D, implemented as a divisor, is plus or minus infinity (108). If the divisor D is plus or minus infinity, a seed S is set to a corresponding plus or minus zero and a modified input value D, implemented as a divisor, is assigned a non-infinite number (210), S being a workable value. If the divisor D is not plus or minus infinity, the divisor D may be a plus or minus normalized or denormalized number according to the IEEE 754-1985 standard.
  • a seed S is set to an approximation corresponding to plus or minus 1/D and the divisor D remains the same (212).
  • the checking for division by zero (104) and for division by infinity (108) may be accomplished in alternate order if desired. In this embodiment all arithmetic operations, addition, subtraction, and multiplication, conform to the IEEE 754-1985 standard for binary floating-point arithmetic.
  • the second value N and the divisor D, modified or unchanged are each premultiplied by the seed value S (214), yielding a numerator and a denominator, respectively.
  • a convergence function value f1 is obtained by subtracting the denominator from the value 2.0.
  • the program multiplies both the numerator and the denominator by the convergence function value f1 , obtaining a quotient having a next numerator and a next denominator, respectively (110).
  • the next denominator is subtracted from 2.0, yielding a next convergence function value, f2.
  • ⁇ D * S * fl * f2 is utilized in this invention, and a convergence factor f is obtained by subtracting the modified divisor D from the value 2.0.
  • the approximated seed S must have a value such that D * S is less than 2.0.
  • FIG. 3 illustrates the steps executed by a programming model incorporating the present invention wherein the implementation of a mapping of an input value D to a seed S and a modified input value D occurs in series, depicted generally by the numeral 300.
  • the program obtains an input value D and a second value, N, related to the first value, for a division algorithm computation (202).
  • the program checks for a plus or minus zero input value D, implemented as a divisor (104). If the divisor D is plus or minus zero, a seed S is assigned a corresponding plus or minus infinity value (308). If the divisor D is not plus or minus zero (104), the program checks to see if the divisor D is plus or minus infinity (108).
  • a seed S is set to a corresponding plus or minus zero (310). If the divisor D is not plus or minus infinity (108), a corresponding seed S is set to an approximation of plus or minus 1/D (312).
  • the checking for division by zero (104) and for division by infinity (108) may be accomplished in alternate order if desired.
  • the program now checks to see if the seed value S is plus or minus zero (314). If the seed value S is plus or minus zero, or alternatively, since S is directly related to D, if a divisor D is equal to plus or minus infinity, a modified input value D, implemented as a divisor, is assigned a non-infinite number (318), S being a workable value . If the seed value S is not plus or minus zero (314), the program checks to see if the seed value S is plus or minus infinity (316).
  • a divisor D is equal to plus or minus zero (316)
  • a modified input value D is assigned a non-zero value with the opposite sign of S (320), -S being a workable value. If the seed value S is not plus or minus infinity (316), the divisor value remains the same (322).
  • FIG. 4 illustrates a hardware implementation of the present invention, generally depicted by the numeral 400.
  • a computer program for implementation of the present invention may be stored in the program memory (404), other memory (412), or may be embodied in hardware in the ALU (406).
  • the program control unit (402) utilizes the bus (410) to select the program to implement the present invention, and the status register (408) determines whether division by zero or by infinity is taking place.
  • the ALU (406) performs the previously described manipulations of values in application of the convergent division algorithm set forth above.
  • the ALU (406) generates an initial seed S with a mantissa that is stored in 8 binary bits of memory.
  • Figure 5 illustrates the prior art, setting forth the error matrix achieved without exception correction.
  • This prior art implementation allows all operands to propagate through the quadratic convergent algorithm without any operand checking. Division by zero or division by infinity results in a NaN, a result that is inconsistent with the IEEE 754-1985 floating point standard.
  • Figure 6 depicts application of the present invention for exception correction.
  • the operands are modified according to the present invention, and the modified operands propagate through the quadratic convergent division algorithm using IEEE 754-1985 arithmetic, outputting quotient and exception results, including signs for zeros and infinities for exception cases, in accordance with the IEEE 754-1985 floating point standard.
  • Figure 7 illustrates the output seed and corrected divisor for a given input divisor according to the present invention.

Abstract

A method which utilizes a single preprocessing step (214, 216) to modify a divisor (D) in floating point division and to enable an exception correction and error checking operation (104, 108) to run concurrently with a division operation. The invention permits achievement of the correct predetermined result if an exception is present or the quotient if no exception occurs.

Description

METHODS AND APPARATUS FOR EFFICIENT RESOURCE ALLOCATION FOR ERROR AND EXCEPTION HANDLING
IN CONVERGENT DIVISION
Background of the Invention
The need exists to achieve accurate processing of all inputs to a digital computer, such as a digital signal processor, having a computer program that utilizes floating point arithmetic to propagate through a convergent division algorithm. In general, to date, certain operand combinations are: (a) simply not processed; (b) require a large decision tree implemented by software; or (c) require several preprocessing cycles implemented by hardware. When all inputs are not processed, such as when division computation is skipped altogether (105, 109), the digital signal processor may require intervention to realign the processing program to facilitate further processing, requiring significant additional time consumption. If a software program is implemented to process a decision tree that provides outputs for error-causing operand combinations (106), again significant additional time is consumed. Present hardware implementations that preprocess error-causing operand combinations to avoid excessive time consumption require substantial resources. Thus, each of the previous solutions to the problem of processing error- causing operand combinations involves either significant time consumption or substantial resource allocation.
In data handling, a computer program should be designed to accommodate the greatest time-consuming event in each step. Hence, the above-described solutions not utilizing a hardware solution necessitate lengthy stepwise time-allocations within the computer program in order to accommodate a greatest possible processing time requirement for each arithmetic operation. Thus a need exists for a practicable method and apparatus to achieve efficient, conservative time and resource implementation of a convergent division algorithm in a digital platform.
Summary of the Invention
In the present invention, efficient resource allocation, together with an appropriate mapping of data input, allow processing of all data inputs in a continuous, accurate, and efficient manner in a digital computer such as a digital signal processor utilizing a computer program storage medium having a computer program stored thereon that modifies and propagates data inputs through a convergent division algorithm.
More specifically, in one embodiment a divisor input is assigned a seed value according to a predetermined categorization of divisor inputs, and is modified to indicate a divisor value suitable for efficient propagation through a convergent division algorithm. This selection of two feasible values for implementation of the convergent division algorithm is a useful preliminary determination for efficient computation. In the present invention the solution of a convergent division algorithm for all inputs by careful choice of seed values and modified divisor values constrains the computation to a substantially shorter duration than in the past, improving cost- effectiveness of signal processing. Utilization of fewer resources to allocate the seed values and to modify the divisors also is cost-effective.
Brief Description Of The Drawings Figure 1 is a general flow chart depicting implementation of a floating-point division algorithm under the prior art. Figure 2 is a flow chart of an implementation of the invention wherein a seed and a modified input value are assigned in parallel. Figure 3 is a flow chart of an implementation of the invention wherein a seed and a modified input value are assigned in series.
Figure 4 is a block diagram of a computer hardware implementation of the invention. Figure 5 is a table setting forth the error matrix achieved without exception correction, according to the prior art.
Figure 6 is a table setting forth an application of the present invention for exception correction. Figure 7 is a table illustrating the output seed and corrected divisor for a given input divisor according to the present invention.
Best Mode For Carrying Out The Invention FIG. 1 is a graphical representation, depicted generally by the numeral 100, of the constraints on an implementation of floating-point division, according to the prior art.
In accordance with the prior art, a programming model may provide a division mode utilizing two numbers, N and D (102), typically represented in the floating-point number form. The program determines whether or not a divisor D is zero (104). If the divisor D is zero (104), the program may substitute a very small number for the divisor so that division may continue (106), or may skip division altogether (105). The program may determine whether or not the divisor is infinity (108). If the divisor is infinity (108), the program may substitute a very large number so that division may continue (106), or may skip division altogether (109). Following the check for division by zero and for division by infinity, the program executes the division algorithm (110) in accordance with prior art technique. The program checks to see whether or not the desired degree of accuracy has been reached (112). If insufficient accuracy has been attained, the program recycles to repeat the division algorithm computation (110) until the desired degree of accuracy is obtained (112), then stops. If the desired degree of accuracy has already been attained (112), the program stops.
FIG. 2 illustrates the steps executed by a programming model incorporating the present invention, wherein the implementation of a mapping of an input value D to a seed S and a modified input value D occurs in parallel, depicted generally by the numeral 200. First the program obtains an input value D and a second value, N, related to the first value, for a division algorithm computation (202). The program checks for a plus or minus zero input value D, implemented as a divisor (104). If the divisor D is plus or minus zero, a seed S is assigned a corresponding infinity value with the same sign as D and a modified input value D, implemented as a divisor, is assigned a non-zero value with the opposite sign as the seed S (208), -S being a workable value. If the divisor D is not plus or minus zero, the program checks to see if the input value D, implemented as a divisor, is plus or minus infinity (108). If the divisor D is plus or minus infinity, a seed S is set to a corresponding plus or minus zero and a modified input value D, implemented as a divisor, is assigned a non-infinite number (210), S being a workable value. If the divisor D is not plus or minus infinity, the divisor D may be a plus or minus normalized or denormalized number according to the IEEE 754-1985 standard. If the divisor D is not plus or minus infinity, a seed S is set to an approximation corresponding to plus or minus 1/D and the divisor D remains the same (212). The checking for division by zero (104) and for division by infinity (108) may be accomplished in alternate order if desired. In this embodiment all arithmetic operations, addition, subtraction, and multiplication, conform to the IEEE 754-1985 standard for binary floating-point arithmetic.
The second value N and the divisor D, modified or unchanged are each premultiplied by the seed value S (214), yielding a numerator and a denominator, respectively. A convergence function value f1 is obtained by subtracting the denominator from the value 2.0. The program multiplies both the numerator and the denominator by the convergence function value f1 , obtaining a quotient having a next numerator and a next denominator, respectively (110). The next denominator is subtracted from 2.0, yielding a next convergence function value, f2. Iteration of a determination of a successive convergence function value f and a quotient having a next numerator N and a next denominator D continues until a next numerator N, being the solution, is obtained with sufficient accuracy (110, 112), halting the process. The convergent division algorithm,
N * S * fl * f2
^~ D * S * fl * f2 is utilized in this invention, and a convergence factor f is obtained by subtracting the modified divisor D from the value 2.0. The approximated seed S must have a value such that D * S is less than 2.0.
FIG. 3 illustrates the steps executed by a programming model incorporating the present invention wherein the implementation of a mapping of an input value D to a seed S and a modified input value D occurs in series, depicted generally by the numeral 300. First the program obtains an input value D and a second value, N, related to the first value, for a division algorithm computation (202). The program checks for a plus or minus zero input value D, implemented as a divisor (104). If the divisor D is plus or minus zero, a seed S is assigned a corresponding plus or minus infinity value (308). If the divisor D is not plus or minus zero (104), the program checks to see if the divisor D is plus or minus infinity (108). If the divisor D is plus or minus infinity (108), a seed S is set to a corresponding plus or minus zero (310). If the divisor D is not plus or minus infinity (108), a corresponding seed S is set to an approximation of plus or minus 1/D (312). The checking for division by zero (104) and for division by infinity (108) may be accomplished in alternate order if desired.
The program now checks to see if the seed value S is plus or minus zero (314). If the seed value S is plus or minus zero, or alternatively, since S is directly related to D, if a divisor D is equal to plus or minus infinity, a modified input value D, implemented as a divisor, is assigned a non-infinite number (318), S being a workable value . If the seed value S is not plus or minus zero (314), the program checks to see if the seed value S is plus or minus infinity (316). If the seed value S is plus or minus infinity, or alternatively, since S is directly related to D, if a divisor D is equal to plus or minus zero (316), a modified input value D, implemented as a divisor, is assigned a non-zero value with the opposite sign of S (320), -S being a workable value. If the seed value S is not plus or minus infinity (316), the divisor value remains the same (322).
The process then continues as described above until a satisfactory quotient is obtained (218).
FIG. 4 illustrates a hardware implementation of the present invention, generally depicted by the numeral 400. A computer program for implementation of the present invention may be stored in the program memory (404), other memory (412), or may be embodied in hardware in the ALU (406). In one embodiment, the program control unit (402) utilizes the bus (410) to select the program to implement the present invention, and the status register (408) determines whether division by zero or by infinity is taking place. The ALU (406) performs the previously described manipulations of values in application of the convergent division algorithm set forth above. In one embodiment the ALU (406) generates an initial seed S with a mantissa that is stored in 8 binary bits of memory. The eight bits for binary storage of the mantissa limit accuracy of the first division iteration to approximately 8 bits. Each iteration of convergent division doubles the number of bits of accuracy. If the IEEE 754-1985 single precision standard is to be employed, two iterations are necessary to obtain 32 bits of accuracy (8*2*2 = 32) which may then be rounded to the required 24 bits of precision.
Figure 5 illustrates the prior art, setting forth the error matrix achieved without exception correction. This prior art implementation allows all operands to propagate through the quadratic convergent algorithm without any operand checking. Division by zero or division by infinity results in a NaN, a result that is inconsistent with the IEEE 754-1985 floating point standard. Figure 6 depicts application of the present invention for exception correction. The operands are modified according to the present invention, and the modified operands propagate through the quadratic convergent division algorithm using IEEE 754-1985 arithmetic, outputting quotient and exception results, including signs for zeros and infinities for exception cases, in accordance with the IEEE 754-1985 floating point standard.
Figure 7 illustrates the output seed and corrected divisor for a given input divisor according to the present invention.
What is claimed is:

Claims

Claims
1. A digital signal processor comprising: a computer program storage medium having a computer program stored thereon for execution by said digital signal processor, said program comprising:
A) means for determining a seed value for an input value;
B) means for preprocessing and modifying the input value to provide a modified input value; and C) means for storing and manipulating the seed value, a second value related to the first value, and the modified input value through a convergent division algorithm and for determining a convergence function value related thereto.
2. The apparatus of claim 1 , wherein the computer program storage medium comprises a stored version of the program that can be transferred upon request to a different hardware program to be executed. 3. The apparatus of claim 1 , wherein the computer program storage medium comprises a fixed hardware embodiment of a program such that storage means itself can execute the program.
4. The apparatus of claim 1 , further including means for iterating the convergent division algorithm and the convergence function determination in step (C) until a solution with a predetermined degree of accuracy is obtained.
5. The apparatus of claim 1 , wherein the means for determining a seed value for an input value outputs the following: for an input value of -∞, a seed value of -0.0; for an input value of +∞, a seed value of +0.0; for an input value of -0.0, a seed value of -∞; for an input value of +0.0, a seed value of +∞; for an input value of a positive denormalized or normalized number, a seed value of =1/(that signed number); and for an input value of a negative denormalized or normalized number, a seed value of =1/(that signed number).
6. The apparatus of claim 1 , wherein the means for preprocessing and modifying the input value to provide a modified input value outputs the following: for a seed value of ± 0.0, a non-infinite value for the modified input value; for a seed value of ± = 1/(a number), ± that number itself for the modified input value; and for a seed value of ± ∞, a non-zero value having the opposite sign of the seed value for the modified input value.
7. The apparatus of claim 1 , wherein the means for manipulating a seed value, an input value, and a second value related to the first input value through a convergent division algorithm and for determining a convergence function related thereto comprises:
A) means for implementing determination of a product of a seed value and a modified input value to obtain a denominator;
B) means for implementing determination of a product of a seed value and a second value related to the first input value to obtain a numerator;
C) means for subtracting the denominator obtained in step (A) from 2.0 to obtain a convergence function value; and
D) means for utilizing associated numerator, denominator, and convergence function values to determine a quotient having a next numerator and a next denominator.
8. The apparatus of claim 1 , wherein the means for manipulating a seed value, an input value, and a second value related to the first input value through a convergent division algorithm and for determining a convergence function related thereto further includes a means for iterating the convergent division algorithm and the convergence function value determination in step (C) until a solution with a predetermined degree of accuracy is obtained, wherein that means comprises:
A) means for implementing determination of a product of a seed value and a modified input value to obtain a denominator; B) means for implementing determination of a product of a seed value and a second value related to the first input value to obtain a numerator;
C) means for subtracting the denominator obtained in step (A) from 2.0 to obtain a convergence function value; D) means for utilizing associated numerator, denominator, and convergence function values to determine a quotient having a next numerator and a next denominator;
E) means for subtracting a next denominator obtained in step (D) from 2.0 to obtain a next convergence function value; and F) means for iterating steps (D) through (E) until a numerator of the quotient, being the solution, has the predetermined degree of accuracy.
9. A method for allocating data storage means and data manipulation means of a computer program stored within a computer storage medium so as to expedite and improve the process of error checking and exception correction in division, said method comprising the steps of:
A) allocating one or more data input devices for storing an input value;
B) allocating one or more data input devices for storing a second input value related to the first input value; C) allocating one or more data manipulation and storage devices for allocating and storing a seed value associated with an input value;
D) allocating one or more data manipulation and storage devices for modifying an input value and storing the modified input value;
E) allocating one or more data manipulation and storage devices for manipulating the seed value, the modified input value, and the second value related to the first input value through a convergent division algorithm, and for determining a convergence function value related thereto, followed by iteration of the convergent division algorithm and determination of the convergence function value until a solution with a predetermined degree of accuracy is obtained, allocating said data input devices, data storage devices and data manipulation devices in accordance with an optimized time and resource conservation process of exception correction and error correction handling.
10. An improvement in digital signal processing methods for optimally allocating resources among a plurality of data input, data storage and data manipulation devices so as to improve accuracy and minimize time consumption during error checking and exception correction manipulations which includes the steps of:
A) allocating data storage and data manipulation devices for selection and storage of a predetermined seed value and an input value; B) allocating a data storage device for a second input value related to the first input value;
C) modifying the first input value and manipulating the seed value, modified input value, and second input value related to the first input value through a convergent division algorithm and for determining a convergence function value related thereto; and
D) iterating the convergent division algorithm and the convergence function value determination in step (C) until a numerator of the quotient, being the solution, has the predetermined degree of accuracy.
11 . A system for maximizing a conservation of time and resources process and improving the accuracy thereof, for use with a general purpose digital computer in accordance with a manipulation optimization strategy, said system comprising: A) process control devices for controlling said process in response to control signal sets;
B) a plurality of sensors for sensing inputs affecting the operation of said process;
C) a controller responsive to said sensors and said input devices for providing improved control signal sets to said process control devices in accordance with a predetermined manipulation optimization strategy,
D) said controller including means for allocating a seed value for an input value, means for preprocessing and modifying the input value to obtain a modified input value, means for manipulating the seed value, modified input value and a second input value related to the first input value through a convergent division algorithm and for determining a convergence function value related thereto, including means for iteration of said manipulations so as to achieve time and resource efficient utilization within said general purpose digital computer system.
EP19910902487 1989-12-29 1990-12-17 Methods and apparatus for efficient resource allocation for error and exception handling in convergent division Withdrawn EP0461240A4 (en)

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US45909089A 1989-12-29 1989-12-29
US459090 1989-12-29

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Citations (1)

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Publication number Priority date Publication date Assignee Title
EP0377992A2 (en) * 1989-01-13 1990-07-18 International Business Machines Corporation Floating point division method and apparatus

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US4724529A (en) * 1985-02-14 1988-02-09 Prime Computer, Inc. Method and apparatus for numerical division

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EP0377992A2 (en) * 1989-01-13 1990-07-18 International Business Machines Corporation Floating point division method and apparatus

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See also references of WO9110190A1 *
WEITEK APPLICATION NOTE 'WTL 1032/1033 Floating Point Division/Square Root/ IEEE Arithmetic' 1983 , WEITEK CORPORATION , SANTA CLARA, CA, USA *

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EP0461240A1 (en) 1991-12-18
JPH04504774A (en) 1992-08-20
KR940008617B1 (en) 1994-09-24
KR920701904A (en) 1992-08-12
CA2047180A1 (en) 1991-06-30
WO1991010190A1 (en) 1991-07-11

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