JPS63254524A - Digital signal processor - Google Patents

Abstract

PURPOSE:To decrease the number of steps down to 1/4 by using a 2-bit rounding bit prescribing register to perform the rounding arithmetic for valid data of 4, 8, 12 and 16 bits respectively just in a single step. CONSTITUTION:A rounding bit prescribing register 2 which prescribes a rounding bit uses the figure series set at and before the final bit directly as a figure series of the approximate value in the case of the rounding arithmetic carried out by a computing element 1, i.e., when the numeric value lower than the final bit by one bit to be left is equal to 0. When said numeric values equal to 0, an operation where 1 is added to the final bit and this addition result is defined as the figure series of the approximate value is applied to an optional bit. Thus a rounding operation is possible to the optional bit length. In such a way, the number of arithmetic steps is decreased to 1/4 and the system performance is improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a digital signal processing device.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of the digital signal processing device. In FIG. 2, 201 is a read-only memory program storage device, which is a program ROM.
shall be. ), 202 is a read-only memory data storage device (hereinafter referred to as data ROM), and 20B is a random access memory data storage device (hereinafter referred to as RA).
Let it be M. ), 204 is an address counter of the program ROM 201, which is configured to sequentially count up by 1 if no next address designation command is input. 2
05 and 206 are save registers for the address counter 204, 207 is a multiplier, 208 and 209 are input registers to the multiplier that store data input to the multiplier 207, and 2
10 is a multiplier output register that stores the output of the multiplier 207, that is, the multiplication result. 211 is a computing unit, 212
．． 213 is a register that stores the calculation result of the calculation unit 211; A single-precision data bus 214 transfers data for executing various instructions. 215 is the computing unit 21
This is a double-precision data bus for transferring input data to 1, output data from arithmetic unit 211, and data from multiplication result storage register 210. Single precision data bus 214 and double precision data bus 215 are connected at connection point 216. 217 is a data register which is an interface section for parallel data input/output, 218 is a serial input register, and 219 is a serial output register.

In digital signal processing, the sum of products of data occupies a large part of the equation. Therefore, in order to prevent deterioration of calculation accuracy, the data bus 215 has a bit length that allows the multiplication result to be transferred to the arithmetic unit 211 without being truncated. The bit length of the data bus 214 is the same as that of the data ROM 202. RAM2
The bit length is the same as that of 03. For example, data ROM
If the bit length of 202゜RAM 203 is 16 bits, code 1 bit, data 15 bits), data bus 2
14 is 16 bits. Also, 16 bits of data and 1
Multiplication of 6 bits of data yields 31 bits of data (1 bit of code, 30 bits of data), so the bit length of the data bus 215 is 31 bits. Further, the bit length of the arithmetic unit 211 is also 31 bits. In the format of data in a digital signal processing device, the most significant bit indicates a sign, and a decimal point usually exists between the most significant bit and the next lower bit. Therefore connection point 2
16, data bus 214 is connected to the upper 16 bits of data bus 215. Also, a data register 217. which is an input/output interface with the outside. Serial input register 218. The bit length of the serial output register 219 is 16 bits, which is the same as that of the data bus 214, but the bit length of actual input/output data can be changed programmably. This bit length is the bit length of the host CPU for parallel data handled by the data register 217, and the bit length of the serial input register 2.
18. Regarding serial data handled by the serial output register 219, A/D, D/A converter and PCM
Much depends on the bit length of the codec.

When the data in the calculation result storage register 212 is transferred to another register, the lower 15 bits are naturally truncated by passing through the data bus 214. Therefore, in order to prevent the error from increasing due to the truncation of the lower 15 bits, a rounding instruction is provided, and conventionally, the rounding instruction is used to perform a rounding operation on a value one bit below the upper 16 bits in an arithmetic unit.

[Problem that the invention seeks to solve]

The conventional rounding operation described above targets the numerical value one bit below the upper 16 bits in the arithmetic unit 211 in order to prevent data truncation errors caused by passing from the data bus 215 to the data bus 214 in FIG. , has the following drawbacks.

For example, if the upper 8 bits of the calculation result are to be output serially or in parallel, conventional rounding calculations are meaningless. Therefore, in the arithmetic unit 211, 1 of the upper 8 bits
The program must handle rounding for numbers below the bit.

First, as an initial setting, write 0080 to an address in RAM.
The data 8 is stored. Rounding is then performed in the following steps.

■Saving the current RAM address pointer value to an empty register.

(2) Transfer the address where 0080H is stored in the RAM address pointer.

(2) In the arithmetic unit, the target data and the data pointed to by the RAM address pointer are added.

■Restore the address saved to all registers to the RAM address pointer.

Although this is only an increase of 4 steps in one rounding process, there is a large amount of useless processing in the entire program. In other words, if there is a limit to the processing time or the capacity of the program ROM or RAM, the performance of the system will deteriorate.

[Means for solving problems]

The digital signal processing device of the present invention includes a program storage device, an instruction decoder that converts control instructions output from the program storage device into microcode and outputs it, and executes a predetermined operation based on the microcode. It is equipped with an arithmetic unit and a multiplier, and in addition to a data bus with a single-precision word length, the arithmetic unit and its surroundings adopt a double-precision word length so that the double-precision data from the multiplier can be handled as is. The word length data bus is a rounding operation performed by the arithmetic unit in the digital signal processing device connected to the upper side of the double precision word length data bus, that is, the value one bit below the last bit to be retained. If is 0, the last bit and the number series before it are used as the approximate number series, and if the number one bit below the last bit to be kept is O, the last bit is set to 1. This operation is performed on arbitrary bits by adding the result to a numerical sequence of an approximate value, thereby making it possible to round to an arbitrary bit length.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows the periphery of the arithmetic unit and the periphery of external input/output. 1 is a 31-bit arithmetic unit. 2 is a rounding bit specification register that specifies the rounding bit, and its value is set by the microcode.

The bit length of register 2 depends on how many bits of valid data are required, but input/output data of 16 bits or less is usually limited to 4 bits, 8 bits, 12 bits, or 16 bits, so 2 bits is sufficient. .

The rounding bit operation using the value of register 2 is as follows. When the value of register 2 is OOB, arithmetic unit 1 performs a rounding operation on the value 1 bit below the upper 16 bits. It becomes OOB at hardware reset. In other words, approximation is performed such that the number of effective bits is 16 bits. When the value of the register is OIB, rounding is performed on the value 1 bit below the upper 12 bits. In other words, approximation is performed such that the number of effective bits is 12 bits. When the value of the register is IOB, a rounding operation is performed on the value one bit below the upper eight bits. When the value of the register is 11B, rounding is performed on the value 1 bit below the upper 4 bits. 3 is a 31-bit data bus. 4 is a 16-bit data bus. The 31-bit data bus 3 and the 16-bit data bus 4 are connected at a connection point 5. 6 is a data register which is an interface section for parallel data input/output, 7 is a serial input register, and 8 is a serial output register. Registers 9 and 10 are 31-bit registers for storing the operation results of the arithmetic unit 1.

Now PCMCodec as serial interface
(8 bits) are connected, data 0011 0111 11110B is stored in the operation result storage register 9, and when the upper 8 bits are serially output, the following is the case. First, by microprogram,
Set IOB in rounding bit specification register 2. Next, a rounding operation is performed so that the number of effective bits becomes 8 bits. When rounding operation is performed, the result is 0011 1001111
1'lOB, and is stored in the operation result storage register 9 again. Then 16 via 31-bit data bus 3
It is input to the bit data bus 4. Here the data is 00
11 1000 0111 0011 B, and is input to the serial output register 8 as is. Here, only the upper 8 bits, ie, 0011 1000 B, are serially output.

Also, 0011 011111 is stored in the calculation result storage register 9.
Data of 110B is stored, and when the upper 8 bits are output serially, the process is as follows. First, the microprogram sets IOB in the 2nd rounding bit specification register. If it is already set,
This part can be omitted. Next, a rounding operation is performed so that the number of effective bits becomes 8 bits. That is, in the arithmetic unit 1, 0011 0111 0111 00110011
1111 1111 110B and 000000 00
Addition of 00 000B is performed.

After performing the rounding operation, the result is 0011 011111 1
10B, and is stored in the calculation result storage register 9 again. The signal is then input to a 16-bit data bus 4 via a 31-bit data bus 3.

Here the data is 0011 0111 11110011
It becomes B. Then, it is input to the serial output register 8 as is. Here, only the upper 8 bits, i.e. 00
11 0111 B is serially output.

〔Effect of the invention〕

As explained above, the present invention provides 4-bit, 8-bit,
Rounding operations for 12-bit and 16-bit valid data can be performed in one step, and the number of steps can be reduced to 1/4 compared to the corresponding processing in conventional programs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention. FIG. 2 is a block diagram of a conventional example. 1... Arithmetic unit, 2... Rounding bit specification register, 3
...31-bit data bus, 4...16-bit data bus
Data bus, 5... Connection point between data bus 3 and data bus 4, 6... Data register, 7... Serial input register, 8... Serial output register, 9.10
...This is the output register of the arithmetic unit. 201...Program ROM, 202-...Data ROM, 20 B-
RAM, 204... Address counter of program ROM, 205, 206... Address counter save register, 207... Multiplier, 208, 209...
- Input register to multiplier, 210... Output register of multiplier, 211... Arithmetic unit, 212, 213...
Output register of arithmetic unit, 214... single-precision data bus, 215... double-precision data bus, 216; connection point between data bus 214 and data bus 215, 217...
Data register, 218... serial input register, 219... serial output register. Agent Patent Attorney Susumu Uchihara l', Set ↓ 7 gap 3 2 31 Hi 7 Top 41 and To data / \'λ 6 Data and Restough cisional input test, teri 8 Sisual output n, 7 - gu 9; output of tiger register

Claims (1)

[Claims] It includes a program storage device, an instruction decoder that converts control instructions output from the program storage device into microcode and outputs it, an arithmetic unit that executes a predetermined operation based on the microcode, and a multiplier. In addition to a single-precision word length data bus, a double-precision word length is adopted for the arithmetic unit and the surroundings of the arithmetic unit so that double-precision data from the multiplier can be handled as is. In the digital signal processing device connected to the upper side of the data bus, the rounding operation performed by the arithmetic unit, that is, if the value one bit below the last bit to be kept is 0, the last bit is and the number series before it are used as the approximate value number series, and if the number one bit below the last bit to be retained is 0, add 1 to the last bit and use the result as the approximate value number. A digital signal processing device that performs sequence operations on arbitrary bits, thereby enabling rounding to an arbitrary bit length.