KR940008617B1 - Method and apparatus for efficient resource allocation for error and exception handling in convergent division - Google Patents

Abstract

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Description

[Name of invention]

Resource Allocation Method and Device for Error and Exception Correction in Convergence Division

[Brief Description of Drawings]

1 is a general flow diagram illustrating the implementation of a floating point division algorithm according to the prior art.

2 is a flowchart of the present invention in which seed values and modified input values are specified in parallel.

3 is a flowchart of the present invention in which a seed value and a modified input value are specified in series.

4 is a block diagram of a computer hardware implementation of the present invention.

5 is a table according to the error matrix achieved without exception correction according to the prior art.

6 is a table according to the application of the present invention for exception correction.

7 is a table showing the output sheet and the corrected number of jets for a given number of input jets in accordance with the present invention.

Detailed description of the invention

[Background of invention]

Convergence division algorithms require accurate processing of all inputs in a digital computer such as a digital signal processor with a computer program using floating point arithmetic. In general, any operand combination is as follows. (a) It is not simply processed. (b) requires a large decision tree to be implemented by the software. (c) require multiple preprocessing cycles to be implemented by the hardware.

When the division calculations are skipped altogether (105, 108), i.e. when all the inputs are not processed, the digital signal processor will require effective additional time consumption and may require adjustments to rearrange the processing program for further processing. It may be. If a software program is used to process the decision tree that provides output to the error-causing operand combination 106, then additional time is available that is valid. Hardware implementations that preprocess the error-cause operand combination to require excessive time consumption require substantial resources. Therefore, conventional methods of solving the problems that occur in handling error-caused operand combinations include effective time consumption or substantial resource allocation.

In adjusting data, the computer program is designed to accommodate the largest time consuming event at each stage. Therefore, the above-described solution without using a hardware solution requires length segmentation time allocation within the computer program to accommodate the largest processing time requirements during each computational operation. Therefore, there is a need for a practical method and apparatus for achieving effective retention time and resources of a convergent division algorithm in a digital platform.

[Summary of invention]

In the present invention, effective resource allocation with data input is continuous and accurate in a digital computer such as a digital signal processor using a computer program storage medium having a stored computer program that modifies and forwards data input through a convergent division algorithm. Allows for efficient processing of all data inputs.

In particular, in one embodiment, the divisor input is assigned to a seed value according to a predetermined list of jet number inputs, and is modified to indicate a suitable jet number value that is effectively passed through a convergence division algorithm. The choice of two viable values for the implementation of a convergent division algorithm is a preliminary decision available for effective computation.

In the present invention, the solution of the convergence division algorithm for all inputs by careful selection of the seed value and the modified jet number value improves the cost-effectiveness of signal processing by performing calculations for a shorter time than in the past.

Best Mode for Implementing the Invention

1 is an illustration showing an implementation of a floating-point division according to the prior art as shown by reference numeral 100.

According to the prior art, the programming model may provide a division mode using two symbols N and D 102 represented in the form of floating-point symbols. The program determines 104 whether the jet number D is zero or not. If the jet number D is zero (104), the program continues to perform division 106 or uses very small symbols instead of the jet number to deepen the whole division. The program determines whether the jets are infinite (108). If the number of jets is infinite (108), the program may use very large symbols to keep the division running (106) or to deepen the whole division. In accordance with the division by zero and the division by infinity, the program performs the division algorithm 110 according to the prior art. The program retrieves 112 whether the required precision has been reached. If insufficient precision is reached, the program repeats the division algorithm calculation until the required precision has been achieved and stopped (112). If the required precision has already been achieved (112), the program stops.

2 shows the steps performed by a programming model incorporating the present invention, wherein the mapping implementation of the seed S and the modified input value D occurs in parallel as shown by reference numeral 200. First, the program obtains a second value N and an input value D associated with the first value for division algorithm calculation 202 (202). The program searches whether the input value D shifted to jet number 104 is plus or minus zero. If the jet number D is positive or negative zero, the seed S is assigned a corresponding infinite value equal to D, and the modified input value D, which transitions to the jet number, is assigned a non-zero value opposite to the seed S (208) -S Is a workable value. If the jet number D is not positive or negative zero, the program retrieves 108 whether the input value D transitioning to the jet number is positive or negative infinity.

If the jet number D is plus or minus infinity, the seed S is set to the corresponding plus or minus zero, and the modified input value D, which transitions to the jet number, is set to a non-infinity number and S is a workable value. If the jet number D is positive or negative infinity, the jet number D may be normalized or unnormalized to plus or minus in accordance with the IEEE 754-1985 standard. If the jet number D is not plus or minus infinity, the seed S is set to plus or minus 1 / D and the jet number D is the same (212). Division by zero 104 and division search by infinity may be accomplished in the proper order, if necessary. In this embodiment, all computational operations, additions, subtractions, and multiplications are in accordance with the IEEE 754-1985 standard for binary floating point operations.

The modified or unconverted second value N and the jet number D are premultiplied by the seed value S 214 to generate the numerator and denominator, respectively. The convergence function value f1 is obtained by subtracting the denominator from the value 2.0. The program multiplies the numerator and denominator by the convergence function value f1 to obtain a quotient with the next numerator and the next denominator, respectively (110). The next denominator is subtracted from 2.0 to produce the next convergent function value f2. The iterative determination of the quotient with the next molecule N and the next denominator D and the continuous convergence function value f continues until the next molecule N has obtained sufficient precision (110, 112) and the process is stopped. The convergence division algorithm is

Used in the present invention. The convergence factor f is obtained by subtracting the modified jet number D from the value 2.0.

Seed S must have a value such that D * S is less than 2.0.

3 illustrates the steps performed by a programming model incorporating the present invention, wherein the mapping implementation of seed S and modified input value D occurs in series, as shown by reference numeral 300.

First, the program obtains a second value N and an input value D associated with the first value for division algorithm calculation. The program detects whether the input value D shifted to the jet number is plus or minus zero. If the jet number D is plus or minus zero, the seed S is designated 308 with a corresponding plus minus infinity value. If the jet number D is positive or negative zero (104), the program searches if the jet number D is positive or negative infinity. If the jet number D is plus or minus infinity (108), the seed is set to the corresponding plus or minus zero. If the jet number D is not plus or minus infinity (108), the corresponding seed S is set adjacent to plus or minus 1 / D (312), division 104 by zero and division 108 by infinity are required. If so, they may be achieved in the proper order.

The program searches for seed value S whether it is plus or minus zero. If the seed value S is plus or minus zero, or if S is directly associated with D and the jet number D is equal to plus or minus infinity, then the modified input value D, which transitions to the jet number, is designated by a non-infinity symbol (318). Is a workable value. If the seed value S is not positive or negative zero (314), the program searches (316) if the seed value S is positive or negative infinity. If the seed value S is plus or minus infinity, then optionally if S is directly associated with D and the jet number D is equal to plus or minus zero (316), then the modified input value D, which is shifted to the jet number, has a non-signal sign of S. It is assigned a value of zero and -S is a workable value. If the seed value S is not positive or negative infinity (316), then the division value remains equivalent.

The process as described above then continues (218) until a satisfactory share is obtained.

4 illustrates a hardware implementation of the present invention as shown by reference numeral 400. Computer programs for the implementation of the present invention may be stored in program memory 404, or other memory 412, or may be used in ALU 406 hardware. In one embodiment, program control unit 402 uses bus 410 to select a program to implement the present invention, and status register 408 determines whether division by zero or infinity occurs. The ALU 406 performs the manipulations described above in accordance with the application of the convergence division algorithm as described above. In one embodiment, ALU 406 generates an initial seed S with a mantissa stored in an 8 binary bit memory. Eight bits for mantissa binary storage are approximately eight bits, limiting the precision of the first division iteration. Each iteration of the convergence division doubles the precision of the number of bits. If the IEEE 754-1985 single precision standard is used, two iterations are needed to get 32 bits (8 * 2 * 2 = 32) rounded to the required 24 bits.

5 is a diagram of an error matrix achieved without exception correction. The prior art implementation allows all operands to pass through the second convergence algorithm without any operand search. Division by zero or division by infinity results in NaN, which is inconsistent with the IEEE 754-1985 floating point standard.

6 shows the application of the present invention for exception correction. Operands are modified in accordance with the present invention, the modified operands use IEEE-754-1985 operations, output quotient and exception results, are passed through a second convergent division algorithm containing zero sine, and IEEE 754-1985. Start with a floating point standard.

Figure 7 shows the output seed and corrected jet number of a given input jet number in accordance with the present invention.

Claims (11)

A signal processing processor having a computer program storage medium having a stored computer program executed by a digital signal processor, the program comprising: A) means for determining a seed value for an input value, and B) a modified input value Means for preprocessing and modifying the input value to provide C, and seeding, a second value proportional to the first value, and a converged function value associated with the modified input value through the convergence division algorithm; And a means for determining the number of digital signals. 2. The digital signal processor of claim 1, wherein the computer program storage medium includes a stored vision of a program that communicates a request to another hardware program to be executed. The digital signal processor as claimed in claim 1, wherein the computer program storage medium has a fixed hardware embodiment of the program such that the storage means itself can execute the program. 2. The digital signal processor of claim 1, comprising means for repeating convergent division algorithms and convergent function decisions in step (C) until the required precision is obtained. The method of claim 1, wherein the means for determining a seed value for the input value comprises: a seed value of −0.0 for an input value of ∞; A seed value of +0.0 for an input value of + ∞; A seed value of -∞ for an input value of -0.0; A seed value of + ∞ for an input value of +0.0; For input values of positive or negative normalization, Seed value of 1 / (signed number); For negative negative or normalized numbers of inputs, A digital signal processor that outputs a seed value of 1 / (signed number). The method of claim 1, wherein the means for preprocessing and modifying the input value to provide a modified input value comprises: a non-infinity value of the modified input value for a seed value of ± 0.0 of the input value; ± " ± its own number of modified inputs for a seed of 1 (number); A digital signal processor for outputting a non-zero value with a sign opposite to the seed value of the modified input value for a seed value of ± ∞. The apparatus of claim 1, further comprising: means for adjusting a second value associated with the first input value via a seed value, an input value, a convergence division algorithm, and determining a convergence function associated therewith; (A) means for determining seed values and modified input values to obtain a denominator; (B) means for determining a second and seed value associated with the first input value to obtain a molecule, C) means for subtracting the denominator obtained in step (A) from 2.0 to obtain a convergent function value, and D) And a means for using the associated numerator, denominator and convergent function values to determine the quotient with the next numerator and the next denominator. The method of claim 1, wherein the means for adjusting the second value associated with the first value associated with the first input value via a seed value, input value, a convergence division algorithm, and determining a convergence function associated therewith, wherein the predetermined precision is obtained. Means for repeating a convergence division algorithm and convergent function value determination in step (C) until it is lost, said repeating means comprising: (A) means for determining a seed value and a modified input value to obtain a denominator; B) means for determining a second and seed value associated with the first input value to obtain a molecule, C) means for subtracting the denominator obtained in step (A) from 2.0 to obtain a convergent function value, and D) next Means for using the associated numerator, denominator and convergent function values to determine the quotient with the numerator and the next denominator, E) means for subtracting the next denominator obtained in step (D) from 2.0 to obtain the next convergent function value, F) A digital signal processor comprising means for repeating steps (D) to (E) until the required share of molecules has a predetermined precision. A method for allocating data storage means and data adjusting means of a computer program stored in a computer storage medium to expedite the process of error retrieval and exception correction in divisions, the method comprising: A) at least one data input device for storing input values; Allocating one or more data input devices to store a second input value related to the first input value, and C) allocating one or more data adjustment and storage devices to seed values coupled to the input values. (E) assigning and storing the modified input values by assigning one or more data adjustment and storage devices to modify the input values, and (e) seeding, modified input values, and convergent division algorithms. One or more data adjustment and storage devices to adjust a second value associated with the first input value via Assigning and determining the convergence function value associated therewith according to the iteration of the convergence division algorithm and determination of the convergence function value until a predetermined precision is obtained, and the input according to the optimal time and resource conservation processing of exception correction and error correction adjustment. And allocating a device, a data storage device, and a data adjustment device. A digital signal processing method for optimally allocating resources between multiple data inputs, data storage and data adjustment devices to improve precision and minimize time consumption during error detection and exception correction adjustments, comprising: A) a predetermined seed value and input Allocating a data storage and data adjustment device for selection and storage of values; B) assigning a data storage device to a second input value related to the first input value; and C) modifying the first input value. And adjusting a seed value, a modified input value, and a second value associated with the first input value through a convergence division algorithm, and determining a convergence function value associated therewith. A system for improving the precision used with a general digital computer and maximizing the preservation of time and resource processing in accordance with an optimal tuning method, comprising: A) a process control device controlling said process in response to a set of control signals; A plurality of detectors for sensing inputs affecting the operation of the process, C) a controller in response to the detector and the input device to provide an improved set of control signals to the process control device in accordance with a predetermined adjustment optimization method; D) The controller further comprises means for assigning a seed value for the input value, means for preprocessing and modifying the input value to obtain a modified input value, the seed value, the modified input value, and a convergence division algorithm. Means for adjusting a second input value associated with one input value, wherein the means for determining a convergence function value comprises: And repeating means of said adjustment to achieve sufficient time and resource usage within the computer system.