EP0420584B1 - Circuit PLL démodulateur dans un récepteur d'informations de trafic - Google Patents

Circuit PLL démodulateur dans un récepteur d'informations de trafic Download PDF

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Publication number
EP0420584B1
EP0420584B1 EP90310493A EP90310493A EP0420584B1 EP 0420584 B1 EP0420584 B1 EP 0420584B1 EP 90310493 A EP90310493 A EP 90310493A EP 90310493 A EP90310493 A EP 90310493A EP 0420584 B1 EP0420584 B1 EP 0420584B1
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European Patent Office
Prior art keywords
signal
traffic information
pll
pll circuit
circuit
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EP90310493A
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German (de)
English (en)
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EP0420584A3 (en
EP0420584A2 (fr
Inventor
Koichi C/O Pioneer Electronic Corporation Kasa
Toshihito C/O Pioneer Electronic Co. Ichikawa
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Pioneer Corp
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Pioneer Electronic Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/53—Arrangements specially adapted for specific applications, e.g. for traffic information or for mobile receivers
    • H04H20/55—Arrangements specially adapted for specific applications, e.g. for traffic information or for mobile receivers for traffic information
    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/09—Arrangements for giving variable traffic instructions
    • G08G1/091—Traffic information broadcasting
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/28—Arrangements for simultaneous broadcast of plural pieces of information
    • H04H20/33—Arrangements for simultaneous broadcast of plural pieces of information by plural channels
    • H04H20/34—Arrangements for simultaneous broadcast of plural pieces of information by plural channels using an out-of-band subcarrier signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95

Definitions

  • the present invention relates to a PLL (phase locked loop) demodulating circuit in a traffic information receiver.
  • a traffic information bradcasting system (see DE-A-37 33 096 corresponding to JP-A-63-87 052) which supplies traffic information in such a manner as a time-sharing during a normal program of a braodcasting station for listeners to a car radio or the like.
  • a subcarrier of 57 kHz equal to a ternary harmonic of a stereophonic pilot signal of 19 kHz is used as a traffic information station identification (ID) signal (hereinafter, referred to as an SK signal) indicative of a broadcasting station of traffic information, the subcarrier frequency being out of the FM carrier band.
  • ID traffic information station identification
  • the subcarrier of 57 kHz amplitude modulated by a region ID signal (having one of the frequencies of from 23.75 Hz to 53.98 Hz which are equal to the values of the integer fractions of 57 kHz; this signal is hereinafter referred to as a BK signal) respectively designating a region the traffic information relates to and, further, by a message ID signal (a single tone of 125 Hz; this signal is referred to as a DK signal hereinafter) indicating that the traffic information is at present being broadcasted.
  • the amplitude modulated subcarrier modulates in frequency a main FM carrier which is transmitted as a traffic information broadcasting wave.
  • Fig. 3(a) shows a frequency spectrum of the above signals.
  • Fig. 3(b) shows a base band after the demodulation.
  • a receiver When a receiver receives the traffic information broadcasting wave it performs FM detection to produce a detection output, from which the SK signal is demodulated by a PLL circuit of 57 kHz and, further, the DK signal is demodulated by a PLL circuit of 125 Hz from the demodulated output.
  • a VCO voltage controlled oscillator
  • a VCO in the PLL circuit of 57 kHz has a locking range of about 1 % ( ⁇ 600 Hz) as shown in Fig. 4(a).
  • a VCO in the PLL circuit of 125 Hz has a locking range of about ⁇ 10 Hz as shown in Fig. 4(b).
  • the DK signal does not exist and, on the other hand, the SK and BK signals exist.
  • the difference between the lower BK signal frequency and the oscillating frequency of the VCO is equal to about 125 Hz of the DK signal as shown in Fig. 5(a). Therefore, there is a case where as shown in Fig. 5(b), the BK signal after the demodulation lies within a locking range of the PLL circuit for the DK signal and is locked into the particular PLL circuit, thereby causing erroneous detection of, the BK signal.
  • the present invention is made in view of the foregoing problem and it is an object of the invention to provide a PLL demodulating circuit in a traffic information receiver in which a demodulated BK signal is not locked into a PLL circuit for DK signal even if an influence by a multi-path phenomenon or the like is exerted.
  • a PLL demodulating circuit in a traffic information receiver for reception of an FM carrier wave carrying a subcarrier which is first ID signal indicative of a broadcasting station of traffic information which is amplitude modulated by a second ID signal indicating to which region the traffic information relates and by a third ID signal indicating that the traffic information is being broadcast, the amplitude modulated subcarrier being carried by a main FM carrier.
  • the receiver includes a first PLL circuit for demodulating the first ID signal from a detection output which is obtained by FM detection and a second PLL circuit for demodulating the third ID signal from a demodulated output of the first PLL circuit, and, assuming that the maximum frequency of the second ID signal is equal to BK and a frequency of the third ID signal is equal to DK, the locking ranges ⁇ f SK and ⁇ f DK of the first and second PLL circuits are determined so as to satisfy a condition of (DK - BK) > ( ⁇ f SK + ⁇ f DK ).
  • the total of the locking ranges of the first and second PLL circuits is not larger than the difference between the maximum frequency of the BK signal as a second ID signal and the frequency of the DK signal as a third ID signal.
  • Fig. 1 is a block diagram showing an outline of a fundamental construction of an FM multiplex broadcasting receiver which can receive a traffic information broadcasting.
  • the receiver can also receive an FM broadcasting wave in a radio data system which is so-called as RDS.
  • the radio data system is a system in which a broadcasting station braodcasts during a usual program a data signal having, information indicative of the kind of program content by means of a multiplex modulation and, a desired program content can be selected on the basis of the demodulated data on the reception side, that is, a radio listener.
  • a signal of 57 kHz is set to a subcarrier
  • the subcarrier of 57 kHz is amplitude modulated into the radio data signal by a data signal indicative of a program content which has been filtered and biphase encoded
  • the amplitude modulated subcarrier is carried by the main carrier which is broadcasted.
  • the RDS signal which was amplitude modulated by the data signal from the subcarrier (hereinafter, referred to as an SDS signal) which was amplitude modulated by the data signal from the subcarrier (hereinafter, referred to as an SDK signal) which was amplitude modulated by the DK signal of the traffic information broadcasting system
  • the RDS signal has a phase difference of about ⁇ /2 for the SDK signal.
  • the detection output of the FM detector 4 passes through a filter 6, so that the RDS signal or SDK signal as a subcarrier of 57 kHz is extracted and supplied to a PLL circuit 7.
  • the PLL circuit 7 the RDS signal or SDK signal which has been extracted from the FM detection output is demodulated.
  • the demodulated RDS signal is supplied to a digital (D) PLL circuit 8 and a decoder 9.
  • the SDK signal is supplied to a PLL circuit 10 to demodulate the DK signal.
  • the D-PLL circuit 8 produces clocks for data demodulation on the basis of the demodulated output of the PLL circuit 7.
  • the produced clocks are supplied to the decoder 9 and are also used as clocks when a process such as an error correction or the like is executed for the output data of the decoder 9.
  • the RDS signal as a demodulated output of the PLL circuit 7 is decoded synchronously with the clocks produced by the D-Pll circuit 8 and is output as data indicative of the kind of program content of the radio broadcasting.
  • a locking state detecting circuit 11 detects a locking state and an unlocking state of the D-PLL circuit 8 and controls the switching operation between the locking ranges of the PLL circuit 7 and D-PLL circuit 8 on the basis of the detection output.
  • a costas loop type PLL circuit is used as a PLL circuit 7.
  • Fig. 2 shows a construction of the costas loop type PLL circuit.
  • the RDS signal or SDK signal is individually multiplied with an output signal of a VCO (voltage controlled oscillator) 23 and a signal whose phase has been delayed by only ⁇ /2 by passing the VCO output through a phase shifting circuit 24.
  • the multiplied outputs are transmitted through LPFs (low pass filters) 25 and 26 and are multiplied by a mutiplier 27.
  • a harmonic component in an error signal as an output signal of the multiplier 27 is eliminated by a loop filter 28 and the resultant signal is used as a control voltage of the VCO 23.
  • the outputs of the multipliers 21 and 22 which have passed through the LPFs 25 and 26 are supplied to a selecting switch 29.
  • the selecting switch 29 is switched by, for instance, a detection signal issued from an SDK detecting circuit 30 for detecting a DC component of the output of the multiplier 21 which has passed through the LPF 25, thereby selectively passing therethrough either one of the outputs of the multipliers 21 and 22.
  • a selected output of the selecting switch 29 is derived as demodulated data.
  • the output of the multiplier 21 which has passed through the LPF 25 is extracted as an SDK signal and supplied to the PLL circuit 10 for DK (shown in Fig. 1).
  • the maximum change amount for the SK signal of the VCO 23 in the PLL circuit 7, that is, a locking range of the PLL circuit 7 is set to ⁇ f SK
  • the maximum change amount for the DK signal of the VCO (not shown) in the PLL circuit 10 is set to ⁇ f DK
  • the maximum frequency (53.98 Hz) of the BK signal is set to BK
  • the frequency (125Hz) of the DK signal is set to DK.
  • the locking ranges ⁇ f SK and ⁇ f DK of the PLL circuits 7 and 10 are determined so as to satify a condition of (DK - DB) > ( ⁇ f SK + ⁇ F DK ).
  • a digital PLL construction is formed by using a high accurate oscillator such as a crystal oscillator or the like as an oscillating source of a reference frequency of the PLL circuit 7 of 57 kHz and its locking range is set to about ⁇ 15 Hz. Since the PLL circuit 10 of 125 Hz generally has a locking range of about ⁇ 10 Hz as mentioned above, the difference between the maximum frequency of the DK signal and the maximum frequency of the BK signal is as follows (DK - BK) ⁇ 71 ( ⁇ f SK + ⁇ f DK ) ⁇ 25 even if it is influenced by the multi-path phenomenon. Accordingly, the BK signal after the demodulation does not fall into the locking range of the PLL circuit 10 for DK.
  • a high accurate oscillator such as a crystal oscillator or the like
  • the locking range of the PLL circuit of 57 kHz to demodulate the SDK signal from the FM detection output is set to ⁇ f SK
  • the locking range of the PLL circuit of 125 Hz to demodulate the DK signal from the PLL demodulated output is set to ⁇ f DK
  • the maximum frequency of the BK signal is set to BK
  • the frequency of the DK signal is set to DK
  • the locking ranges ⁇ f SK and ⁇ f DK of the PLL circuits are determined so as to satisfy the condition of (DK - BK) > ( ⁇ f SK + ⁇ f DK ). Therefore, the BK signal after the demodulation does not fall into the PLL circuit for DK of 125 Hz even if it is influenced by the multi-path noises or the like.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Claims (1)

  1. Circuit PLL démodulateur dans un récepteur d'informations de trafic, pour la réception d'une onde porteuse de modulation de fréquence (FM), cette onde portant une sous-porteuse qui est un premier signal d'identification (ID) indiquant une station de radiodiffusion d'informations de trafic dont l'amplitude est modulée par un deuxième signal ID qui indique quelle région est concernée par ces informations de trafic, et par un troisième signal ID qui indique que les informations de trafic sont radiodiffusées, ledit circuit comprenant :
    - un premier circuit PLL (7) de démodulation du premier signal ID provenant d'une sortie de détection et obtenu par la démodulation FM de la porteuse FM reçue ; et
    - un deuxième circuit PLL (10) de démodulation du troisième signal ID provenant d'une sortie démodulée du premier circuit PLL,
    dans lequel, si l'on suppose que la fréquence maximum du deuxième signal ID est égale à BK et qu'une fréquence du troisième signal ID est égale à DK, les taux de verrouillage ΔfSK et ΔfDK des premier et deuxième circuits PLL sont déterminés de manière à satisfaire à la condition (DK - BK) > (Δf SK + Δf DK ).
    Figure imgb0008
EP90310493A 1989-09-27 1990-09-25 Circuit PLL démodulateur dans un récepteur d'informations de trafic Expired - Lifetime EP0420584B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP251135/89 1989-09-27
JP1251135A JPH0736532B2 (ja) 1989-09-27 1989-09-27 交通情報受信機におけるｐｌｌ復調回路

Publications (3)

Publication Number Publication Date
EP0420584A2 EP0420584A2 (fr) 1991-04-03
EP0420584A3 EP0420584A3 (en) 1992-08-05
EP0420584B1 true EP0420584B1 (fr) 1995-11-22

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Application Number Title Priority Date Filing Date
EP90310493A Expired - Lifetime EP0420584B1 (fr) 1989-09-27 1990-09-25 Circuit PLL démodulateur dans un récepteur d'informations de trafic

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EP (1) EP0420584B1 (fr)
JP (1) JPH0736532B2 (fr)
DE (1) DE69023729D1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4788538B2 (ja) * 2006-09-12 2011-10-05 ソニー株式会社 ホログラム包装体

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2408947C3 (de) * 1974-02-25 1979-02-22 Blaupunkt-Werke Gmbh, 3200 Hildesheim Schaltungsanordnung zur Frequenzerkennung auf dem Gebiet des Verkehrsfunkempfangs
DE2527857A1 (de) * 1975-06-23 1977-01-13 Blaupunkt Werke Gmbh Decoder fuer frequenzmodulierte steuersignale
JPS6387052A (ja) * 1986-09-30 1988-04-18 Pioneer Electronic Corp Ｆｍ多重放送受信機におけるデ−タ復調回路

Also Published As

Publication number Publication date
EP0420584A3 (en) 1992-08-05
JPH03113921A (ja) 1991-05-15
JPH0736532B2 (ja) 1995-04-19
EP0420584A2 (fr) 1991-04-03
DE69023729D1 (de) 1996-01-04

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