EP0403287A2 - Procédé de polissage de plaquettes semi-conductrices - Google Patents

Procédé de polissage de plaquettes semi-conductrices Download PDF

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Publication number
EP0403287A2
EP0403287A2 EP90306519A EP90306519A EP0403287A2 EP 0403287 A2 EP0403287 A2 EP 0403287A2 EP 90306519 A EP90306519 A EP 90306519A EP 90306519 A EP90306519 A EP 90306519A EP 0403287 A2 EP0403287 A2 EP 0403287A2
Authority
EP
European Patent Office
Prior art keywords
semiconductor wafer
polishing
thickness
polished
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP90306519A
Other languages
German (de)
English (en)
Other versions
EP0403287A3 (fr
EP0403287B1 (fr
Inventor
Yasuaki Nakazato
Hiroo Ogawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of EP0403287A2 publication Critical patent/EP0403287A2/fr
Publication of EP0403287A3 publication Critical patent/EP0403287A3/fr
Application granted granted Critical
Publication of EP0403287B1 publication Critical patent/EP0403287B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/005—Control means for lapping machines or devices
    • B24B37/013—Devices or means for detecting lapping completion

Definitions

  • the present invention relates to a method of polishing semiconductor wafers, more particular to an effective technique suitable for polishing semiconductor wafers, whose surfaces to be polished are required to be very flat.
  • the final step of manufacturing semiconductor silicon wafers includes a polishing step for forming a specular surface.
  • This step generally employs a method called the mechanochemical method, which combines mechanical attrition and chemical reaction.
  • Fig. 4 shows the main components of a polishing apparatus for polishing one face of a semiconductor wafer.
  • numeral 1 indicates a glass plate.
  • a plurality of semiconductor wafers 2 are bonded with wax to the under surface of the glass plate 1.
  • These semiconductor wafers 2, having undergone processes such as lapping, beveling and etching, are bonded in such a manner that they can be attached or removed.
  • a polishing cloth 3a is firmly held on the surface of a turntable 3, which is positioned under the glass plate 1. Polishing is performed by using the apparatus in the following way.
  • the semiconductor wafer 2 contacts the polishing cloth 3a under the pressure of the glass plate 1.
  • the turntable 3 rotates to cause the glass plate 1, supporting the semiconductor wafer 2, to rotate so as to bring the semiconductor wafer 2 into contact with the polishing cloth 3a on which polishing slurry is sprayed.
  • the polishing slurry is a weak alkaline aqueous solution containing colloidal silica as fine abrasive grains.
  • the present invention discloses a method of polishing a semiconductor wafer, wherein when the semiconductor wafer bonded to a plate is polished to a desired thickness by pressing the semiconductor wafer against a rotating turntable side, the semiconductor wafer is bonded to the plate, and at the same time, a thickness regulating member, at least whose surface layer is made of a material where polishing speed is slower than the semiconductor wafer, is arranged on the plane of the plate in order to control the thickness of the semiconductor wafer.
  • a semiconductor wafer to be polished is bonded to a plate, and at the same time, the thickness regulating member, made of a material where polishing speed is slower than the semiconductor wafer, is arranged around the bonded semiconductor wafer and closely spaced-apart from it on the plane of the plate.
  • the semiconductor wafer is polished by using the thickness regulating member, as a stopper. For these reasons, even if the polishing speed increases under circumstances that the semiconductor wafer is pressed to the turntable at increased pressure, a part of the pressure is to be borne by the thickness regulating member when the polishing is just about finished.
  • the polishing speed becomes slow according to the increase in the pressure applied to the wafer by the amount of the pressure borne as mentioned above, and thus it is easy to control the polishing amount of the semiconductor wafer as well as the thickness of the semiconductor wafer.
  • the polished surface of the semiconductor wafer thus becomes even in thickness variation across and specular.
  • the thickness regulating member arranged around the semiconductor wafer, acts as a stopper, the semiconductor wafer is so polished that the surface of the thickness regulating member on the turntable side is substantially flush with the semiconductor wafer, thereby contributing to a less uneven thickness across the whole surface of the semiconductor wafer where one surface is the surface to be polished.
  • Fig. 1 shows the major components of a polishing apparatus for polishing one face of the semiconductor wafer.
  • one semiconductor wafer 12 having undergone processes such as lapping, beveling and etching is bonded with wax to the central under surface of the glass plate 11.
  • a total of eight dummy wafers 15, serving as thickness regulating members are so arranged on the under surface of the glass plate 11 as to encircle the above semiconductor wafer 12.
  • the semiconductor wafer 12 is bonded to the surface of the glass plate 11 after molten wax is uniformly sprayed in very fine particles by a sprayer on the surface of the wafer 12 to be bonded; or the semiconductor wafer 12 and the dummy wafers 15 are heated after being just placed on the surface of the glass plate 11, and then the wax is introduced to the gaps under the wafers having been melted at a point of the periphery already warmed up before the semiconductor wafer 12 and the dummy wafers 15 are pressed and cooled to fix in order to decrease the gaps and thus clear the reverest precision of less than 0.1 ⁇ m.
  • Either the entire matrix of the dummy wafers 15 or at least their surface layers are made of a material slower to polish than the semiconductor wafer 12.
  • the matrix of the dummy wafer 15 is made of silicon and a silicon oxide film is formed on the surface layer of the dummy wafer 15.
  • the silicon oxide film may be a thermal oxide film or an oxide film obtained by chemical vapor deposition method (CVD) and is preferably a thermal oxide film, which is slower to remove in polishing by the mechanochemical polishing method.
  • the dummy wafers 15 are bonded with wax to the glass plate 11 in the same manner as in the semiconductor wafer 12, that is, they can be attached or removed, or they are bonded semipermanently with epoxy resin or the like to the glass plate 11.
  • the dummy wafer 15 is made of a material quite extremely slower to polish than the semiconductor wafer 12, it is convenient to bond the dummy wafer 15 semipermanently to the glass plate 11.
  • the matrix of the dummy wafer 15 is made of silicon, it is possible to control the thickness of the semiconductor 12 very effectively and accurately.
  • a polishing cloth 13a is bonded to the upper surface of the turntable 11 under the glass plate 11.
  • Polishing is performed by using the polishing apparatus as follows: the semiconductor wafer 12 contacts the polishing cloth 13a under the pressure of the glass plate 11. At the same time, the turntable 13 rotates to cause the glass plate 11, supporting the semiconductor wafer 12, to rotate so as to bring the semiconductor wafer 12 into contact with the polishing cloth 13a. As a result, the main surface of the semiconductor wafer 12 bonded to the under surface of the glass plate 11 is polished.
  • a polishing agent during the polishing operation, colloidal silica, dispersed in an aqueous solution with a pH adjusted to weak alkalinity with NaOH or NH4OH, is employed.
  • the semiconductor wafer 12 to be polished is bonded to the central under surface of the glass plate 11, and at the same time, dummy wafers 15, made of a material slower to polish than the semiconductor wafer 12, are arranged around the semiconductor 12 under the glass plate 11.
  • the polishing speed for the dummy wafer 15 is, depending upon polishing conditions, 1/200 or less of the polishing speed of the silicon.
  • the semiconductor wafer 12 is polished by using the dummy wafers 15 as a stopper, even if polishing speed increases owing to the condition that the semiconductor wafer 12 is pressed to the turntable 11 under increased pressure, part of the pressure will be borne by the dummy wafers 15 through the whole polishing operation. As a result, the polishing speed slows according to an amount of the pressure shared with the dummy wafers, and thus it is easy to control the polishing amount of the semiconductor wafer 12 as well as the thickness across the whole surface of the semiconductor wafer 12. The polished surface of the semiconductor wafer 12 thus becomes even in thickness across and specular.
  • the semiconductor wafer 12 is so polished that the surfaces of the dummy wafers 15 on the turntable side 11 are substantially flush with the semiconductor wafer 12, thereby contributing to a less uneven thickness of the semiconductor wafer 12 where one surface is the surface to be polished. For all the reasons described above, a highly geometrically controlled semiconductor wafer 12 can be obtained.
  • Fig. 3 there are nine positions for measuring the thickness of the semiconductor wafer.
  • the dummy wafer 15 whose matrix is silicon and with a silicon oxide film formed on its surface layer
  • a dummy wafer whose matrix is silicon and with a silicon nitride film formed on its surface layer
  • materials such as quartz, plastic or sapphire can be used for the dummy wafer as the thickness regulating member.
  • Metal can be used for dummy wafer if contamination is not a factor.
  • the shape of the dummy wafer is not necessarily the same as that of the semiconductor wafer.
  • a ring-shaped dummy wafer can be employed so as to encircle the semiconductor wafer 12. The important thing to be considered is to use a dummy wafer, which is capable of sharing part of the pressure used to polish the semiconductor wafer on the turntable and which is capable of serving as a stopper.
  • the semiconductor wafer is polished to its desired thickness by pressing it against the rotating turntable side, the semiconductor wafer is bonded to the plate, and at the same time, the thickness regulating member, at least whose surface layer is made of a material slower to polish than the semiconductor wafer, is arranged on the plane of the plate.
  • the thickness regulating member controls the semiconductor wafer thickness. For these reasons, even if the polishing speed increases, it becomes easy to control the polishing amount of the semiconductor wafer.
  • the semiconductor wafer is not polished to a thinner thickness than the thickness of the thickness regulating member. As a result, the uneven thickness of a semiconductor wafer where one surface is the surface to be polished is reduced and thus a highly geometrically controlled semiconductor wafer can be obtained.

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
EP90306519A 1989-06-16 1990-06-14 Procédé de polissage de plaquettes semi-conductrices Expired - Lifetime EP0403287B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1153748A JPH0319336A (ja) 1989-06-16 1989-06-16 半導体ウェーハの研磨方法
JP153748/89 1989-06-16

Publications (3)

Publication Number Publication Date
EP0403287A2 true EP0403287A2 (fr) 1990-12-19
EP0403287A3 EP0403287A3 (fr) 1991-10-23
EP0403287B1 EP0403287B1 (fr) 1994-10-05

Family

ID=15569254

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90306519A Expired - Lifetime EP0403287B1 (fr) 1989-06-16 1990-06-14 Procédé de polissage de plaquettes semi-conductrices

Country Status (3)

Country Link
EP (1) EP0403287B1 (fr)
JP (1) JPH0319336A (fr)
DE (1) DE69013065T2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0561532A2 (fr) * 1992-03-16 1993-09-22 AT&T Corp. Méthode de fabrication d'un circuit intégré comprenant la planarisation d'une plaquette
GB2275130A (en) * 1992-05-26 1994-08-17 Toshiba Kk Polishing apparatus and method for planarizing layer on a semiconductor wafer
US5445996A (en) * 1992-05-26 1995-08-29 Kabushiki Kaisha Toshiba Method for planarizing a semiconductor device having a amorphous layer

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2778659B2 (ja) 1993-12-24 1998-07-23 キヤノン株式会社 導光体及び照明装置及び画像読取装置
JP3983887B2 (ja) * 1998-04-09 2007-09-26 沖電気工業株式会社 基板研磨用治具及び半導体ウエハの研磨方法
CN105199610B (zh) * 2015-10-16 2017-12-19 郑州磨料磨具磨削研究所有限公司 一种蓝宝石抛光组合物及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2979868A (en) * 1957-11-29 1961-04-18 Siemens Ag Lapping device for semiconductor wafers
US3559346A (en) * 1969-02-04 1971-02-02 Bell Telephone Labor Inc Wafer polishing apparatus and method
US4165584A (en) * 1977-01-27 1979-08-28 International Telephone And Telegraph Corporation Apparatus for lapping or polishing materials
FR2521895A1 (fr) * 1982-02-23 1983-08-26 Ansermoz Raymond Tasseau multiple pour le rodage, au lapidaire, de pieces en forme de lames minces
JPS6471663A (en) * 1987-09-08 1989-03-16 Hitachi Cable Lapping method for gaas wafer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6451268A (en) * 1987-08-19 1989-02-27 Sanyo Electric Co Mechanical polishing method
JP3351687B2 (ja) * 1996-08-05 2002-12-03 株式会社東芝 雑音消去に用いられるフィルタ演算装置及びフィルタ演算方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2979868A (en) * 1957-11-29 1961-04-18 Siemens Ag Lapping device for semiconductor wafers
US3559346A (en) * 1969-02-04 1971-02-02 Bell Telephone Labor Inc Wafer polishing apparatus and method
US4165584A (en) * 1977-01-27 1979-08-28 International Telephone And Telegraph Corporation Apparatus for lapping or polishing materials
FR2521895A1 (fr) * 1982-02-23 1983-08-26 Ansermoz Raymond Tasseau multiple pour le rodage, au lapidaire, de pieces en forme de lames minces
JPS6471663A (en) * 1987-09-08 1989-03-16 Hitachi Cable Lapping method for gaas wafer

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 13, no. 244 (M-834)(3592) 07 June 1989 ; & JP-A-1 051 268; & JP-A-64 051 268 *
PATENT ABSTRACTS OF JAPAN vol. 13, no. 244 (M-834)(3592) 07 June 1989, & JP-A-01 051 268 (SANYO) 27 February 1989, *
SOVIET INVENTIONS ILLUSTRATED, Sections P/Q, week 8544, 11 December 1985. Derwent Publications Ltd., London GB. *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0561532A2 (fr) * 1992-03-16 1993-09-22 AT&T Corp. Méthode de fabrication d'un circuit intégré comprenant la planarisation d'une plaquette
EP0561532A3 (en) * 1992-03-16 1997-08-20 American Telephone & Telegraph Method of manufacturing an integrated circuit including planarizing a wafer
GB2275130A (en) * 1992-05-26 1994-08-17 Toshiba Kk Polishing apparatus and method for planarizing layer on a semiconductor wafer
US5445996A (en) * 1992-05-26 1995-08-29 Kabushiki Kaisha Toshiba Method for planarizing a semiconductor device having a amorphous layer
GB2275130B (en) * 1992-05-26 1997-01-08 Toshiba Kk Polishing apparatus and method for planarizing layer on a semiconductor wafer
US5914275A (en) * 1992-05-26 1999-06-22 Kabushiki Kaisha Toshiba Polishing apparatus and method for planarizing layer on a semiconductor wafer
US5948205A (en) * 1992-05-26 1999-09-07 Kabushiki Kaisha Toshiba Polishing apparatus and method for planarizing layer on a semiconductor wafer

Also Published As

Publication number Publication date
EP0403287A3 (fr) 1991-10-23
JPH0319336A (ja) 1991-01-28
DE69013065T2 (de) 1995-01-26
EP0403287B1 (fr) 1994-10-05
DE69013065D1 (de) 1994-11-10

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