EP0349605A1 - Dispositifs a semi-conducteurs avec couche programmable au moyen de composants passifs et procede de production de tels dispositifs - Google Patents

Dispositifs a semi-conducteurs avec couche programmable au moyen de composants passifs et procede de production de tels dispositifs

Info

Publication number
EP0349605A1
EP0349605A1 EP19880909595 EP88909595A EP0349605A1 EP 0349605 A1 EP0349605 A1 EP 0349605A1 EP 19880909595 EP19880909595 EP 19880909595 EP 88909595 A EP88909595 A EP 88909595A EP 0349605 A1 EP0349605 A1 EP 0349605A1
Authority
EP
European Patent Office
Prior art keywords
layer
passive components
polysilicon
active devices
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19880909595
Other languages
German (de)
English (en)
Inventor
Peter Fred Blomley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Logic Europe Ltd
Original Assignee
LSI Logic Europe Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Europe Ltd filed Critical LSI Logic Europe Ltd
Publication of EP0349605A1 publication Critical patent/EP0349605A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to semiconductor devices which include- a programmable passive-component layer, and is also concerned with a process for producing such devices. Included within the scope of the invention are both integrated circuit (IC) arrays and also semiconductor wafers processed to a stage where they incorporate the programmable passive-component layer.
  • IC integrated circuit
  • the invention is relevant both to analogue arrays and to analogue/digital arrays.
  • the present invention arises from a consideration of how best to produce application specific system ICs (ASSICs).
  • ASSICs application specific system ICs
  • the turnaround from "sign off" to end of batch and supply of parts is usually about two to three weeks, and could be as little as one week.
  • the average total processing time of all layers in an IC would be in the range of twelve to sixteen weeks.
  • this is the metal layers with the vias (metal to metal contacts) and in some cases with the inclusion of the contacts to the silicon as well.
  • the active devices e.g. bipolar or CMOS, are fixed in terms of their integer values as programmed b the metal layers.
  • the programming of the passive component layer or layers is achieved by again using the metal layers, connecting resistors either in parallel or series or in a combination of both, in order to make up the required values.
  • the problem with such techniques is that the range of passive component values is fixed absolutely and one has to have a very high degree of redundancy in order to be able to create a useful range of component values. This is extremely wasteful and does not necessarily guarantee that one can create the particular component values which one needs for the customer's requirements.
  • the key problem with any analogue design is the massive range of passive components which are required. In most cases these are a wide range of matched resistors with some small capacitors.
  • a polysilicon layer is used for the gates of the CMOS devices and for the emitters of the bipolar devices. It is a primary object of the present invention to use a layer of material which has a substantially linear resistance characteristic as a programmable passive-component layer.
  • the material may be polysilicon or chrome disilicide for example.
  • this polysilicon material for example would not be considered as a programmable- resistance because * the polysilicon layer usually only occurs in CMOS technology and, because its resistance is relatively low (50ohms per square), it would be incompatible with CMOS linear designs.
  • these materials are extremely useful and appropriate.
  • a semiconductor wafer which incorporates a layer of material which has a substantially linear resistance characteristic and which is arranged to be programmed with passive components.
  • an IC array, analogue or analogue/digital which comprises a layer of material which has a substantially linear resistance characteristic and which is programmed with passive components.
  • the material of the layer is preferably polysilicon or chrome disilicide.
  • a process for the manufacture of semiconductor wafers or IC arrays which comprises the steps of: a) effecting a first, etching step to define at least part of active devices; b) depositing a layer of material having a substantially linear resistance characteristic; and, c) patterning desired passive components on said 4 laye _
  • the patterning of the passive components is effected by a second etching step following the first etching step which defines the 5 active components.
  • At least one metal definition stage follows the patterning of the passive components.
  • Fig. shows part of a BiCMOS analogue array to illustrate how the programmable passive component area 35 is integrated into the array;
  • Fig. 2 illustrates the sequence of process steps in the creation of an IC array in accordance with the invention
  • Fig. 3 shows one alternative analogue array
  • Fig. 4 shows a further alternative analogue array
  • Fig. 5 shows a total system layout in .accordance with the invention.
  • bipolar devices are indicated at B
  • P-channel MOS transistors are indicated at P
  • N-channel MOS transistors are indicated at N
  • resistors are indicated at R
  • capacitors are indicated at C.
  • Fig. 1 shows a typical analogue array.
  • the area in which the passive components, here shown as resistors R and capacitors C, are created or patterned is indicated generally by the cross-hatched area 10 which encompasses the active components B,P,N. Power rails are indicated at -Vg, +Vs, 0, +Vs and -Vs.
  • the centre group 12 of active devices P,B may define basic amplifier blocks.
  • the group 14 of active devices N,P shown at the right-hand side of Fig.1 may define logic gates, as required.
  • Each active device is shown as having a width dimension of 24 micron.
  • the active device spacing is based on a grid of 6 micron pitch.
  • Fig. 2 illustrates the sequence of manufacturing steps involved in the creation of a wafer or IC array of the present invention.
  • the initial, conventional BiCMOS process steps, indicated generally at 16, are first carried out using masks, for example 12 masks.
  • One step in this process, as indicated in Fig. 2 is a first etch stage 18 carried out on a polysilicon layer in order to define the gates of the CMOS devices and the bipolar emitters, i.e. active devices.
  • the wafers undergo ion implantation, etc. as indicated at 20. This includes the CMOS source/drain implants.
  • a layer of material having a substantially linear resistance characteristic in this embodiment referred to as polysilicon by way of example, is deposited, as step 22, in the area or areas designated for the passive components of the array.
  • polysilicon a layer of material having a substantially linear resistance characteristic
  • the polysilicon layer is deposited on top of the silicon surface.
  • CMOS gates and bipolar emitters, as well as the presently unconfigured passive component area are covered by a photoresist coating and * using a mask, the polysilicon area is etched to create the desired passive components from the predefined areas. These predefined areas, such as that indicated at 10 in Fig. 1, do not have active devices within them.
  • This second etch stage configures the passive component area or areas 10. This technique allows an array to be constructed which, for the first time, allows the customer to define his own passive component values on an analogue design array.
  • Polysilicon resistors can also be used for creating' the metal routing channels.
  • chrome disilicide is an alternative material which can be used. Indeed, the
  • 25 scope of the invention includes any material which has a linear or substantially linear resistance . characteristic and which is compatible with the other manufacturing process steps.
  • Figs. 3 and 4 show two alternatives to the layout
  • the choice of topology mainly depends on the required ratio between the active B,P and N devices and the total value of the resistors R arid/or capacitors.
  • the active devices B,P,N are logic gates and the passive
  • Fig. 5 shows an arrangement for a total IC array comprising digital and analogue sections.
  • the digital section 34 is a compacted array of standard cells which are metal programmable and the analogue section 36 may be composed as described above.
  • a test logic area 38' is provided therebetween.
  • a ratio of approximately 4 to 1 is presently preferred for the ratio between the areas of .the * digital and ' analogue sections 34,36 respectively.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Un réseau de circuits intégrés ou une tranche de semi-conducteurs, de type analogiques ou analogiques et numériques, comprennent une couche de matériau qui présente une caractéristique de résistance sensiblement linéaire et qui peut être programmée avec des composants passifs, c'est-à-dire des résistances (R) et des condensateurs (C). Le matériau est de préférence à base de polysilicium ou de disiliciure de chrome. Les composants passifs (R, C) sont disposés dans la zone (10) qui entoure les dispositifs actifs (B, P, N), qui sont constitués par exemple par des dispositifs MOS complémentaires et par des dispositifs bipolaires. Le procédé servant à obtenir la disposition désirée des composants passifs peut comporter l'attaque de la couche de matériau.
EP19880909595 1987-11-11 1988-11-11 Dispositifs a semi-conducteurs avec couche programmable au moyen de composants passifs et procede de production de tels dispositifs Withdrawn EP0349605A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8726366 1987-11-11
GB8726366A GB8726366D0 (en) 1987-11-11 1987-11-11 Ic array

Publications (1)

Publication Number Publication Date
EP0349605A1 true EP0349605A1 (fr) 1990-01-10

Family

ID=10626763

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19880909595 Withdrawn EP0349605A1 (fr) 1987-11-11 1988-11-11 Dispositifs a semi-conducteurs avec couche programmable au moyen de composants passifs et procede de production de tels dispositifs

Country Status (5)

Country Link
EP (1) EP0349605A1 (fr)
JP (1) JPH02502054A (fr)
AU (1) AU2626388A (fr)
GB (2) GB8726366D0 (fr)
WO (1) WO1989004553A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69012848T2 (de) * 1989-02-09 1995-03-09 Sony Corp Integrierte Halbleiterschaltungsanordnungen.
JP2836318B2 (ja) * 1991-10-18 1998-12-14 日本電気株式会社 半導体装置
US5631492A (en) * 1994-01-21 1997-05-20 Motorola Standard cell having a capacitor and a power supply capacitor for reducing noise and method of formation

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124015A (ja) * 1983-12-08 1985-07-02 Seiko Epson Corp 磁気ヘッド
JPS6289341A (ja) * 1985-10-15 1987-04-23 Mitsubishi Electric Corp マスタスライス方式大規模半導体集積回路装置の製造方法
JPH0666446A (ja) * 1992-08-19 1994-03-08 Matsushita Electric Ind Co Ltd パーソナルスペース用温度環境調整装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8904553A1 *

Also Published As

Publication number Publication date
GB8726366D0 (en) 1987-12-16
GB2219436A (en) 1989-12-06
WO1989004553A1 (fr) 1989-05-18
GB8915545D0 (en) 1989-08-23
AU2626388A (en) 1989-06-01
JPH02502054A (ja) 1990-07-05

Similar Documents

Publication Publication Date Title
EP0058504B1 (fr) Procédé de fabrication d'un circuit de retard dans un circuit intégré à partir d'une matrice standard
US5691218A (en) Method of fabricating a programmable polysilicon gate array base cell structure
JP2664403B2 (ja) 特注集積回路の製造方法
US3335338A (en) Integrated circuit device and method
JPH0661442A (ja) プログラマブル・ゲート・アレー及びその製造方法
US5760428A (en) Variable width low profile gate array input/output architecture
US5998275A (en) Method for programmable integrated passive devices
JP2006100826A (ja) 集積回路の抵抗体の抵抗値を調整する構造および方法
US7893518B2 (en) Method for generating a layout, use of a transistor layout, and semiconductor circuit
EP0210397A1 (fr) Circuits LSI, adaptables à des méthodes de configurations personnalisées
US5111273A (en) Fabrication of personalizable integrated circuits
EP0029369B1 (fr) Procédé de fabrication d'un dispositif semiconducteur
US5206184A (en) Method of making single layer personalization
JPH05114649A (ja) マスクプログラマブルゲートアレイ製造方法
EP0349605A1 (fr) Dispositifs a semi-conducteurs avec couche programmable au moyen de composants passifs et procede de production de tels dispositifs
US6943415B2 (en) Architecture for mask programmable devices
US7648912B1 (en) ASIC customization with predefined via mask
KR20000057940A (ko) 병합 집적 회로 장치를 제조하는 방법
EP0650196A2 (fr) Dispositif de circuit intégré du type masterslice et son procédé de fabrication
WO2001013134A1 (fr) Reglage de parametres dans un circuit integre mos
US5068702A (en) Programmable transistor
US6868530B2 (en) Method for fabricating an integrated semiconductor circuit
EP0316104A2 (fr) Circuits intégrés comprenant des résistances et des transistors bipolaires
JP3288802B2 (ja) 半導体集積回路装置
EP0240273A2 (fr) Transistors programmables

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19891109

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE FR GB IT LI LU NL SE

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19920603