EP0342681B1 - Procédé pour produire un dispositif électrique - Google Patents

Procédé pour produire un dispositif électrique Download PDF

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Publication number
EP0342681B1
EP0342681B1 EP89108973A EP89108973A EP0342681B1 EP 0342681 B1 EP0342681 B1 EP 0342681B1 EP 89108973 A EP89108973 A EP 89108973A EP 89108973 A EP89108973 A EP 89108973A EP 0342681 B1 EP0342681 B1 EP 0342681B1
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EP
European Patent Office
Prior art keywords
lead
chip
leads
alternating voltage
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP89108973A
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German (de)
English (en)
Other versions
EP0342681A2 (fr
EP0342681A3 (en
Inventor
Shunpei Yamazaki
Noriya Ishida
Mitsunori Sakama
Mari Sasaki
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63124360A external-priority patent/JPH01292846A/ja
Priority claimed from JP63124361A external-priority patent/JPH01292833A/ja
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of EP0342681A2 publication Critical patent/EP0342681A2/fr
Publication of EP0342681A3 publication Critical patent/EP0342681A3/en
Application granted granted Critical
Publication of EP0342681B1 publication Critical patent/EP0342681B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • the present invention relates to a manufacturing method of an electric device in accordance with the preamble of independent claim 1.
  • Integrated semiconductor circuits are most important electric devices which have been broadly used in a variety of fields.
  • One of the problems from the view point of reliability is the invasion of moisture or other impurities into the IC chips embedded in molding. The invasion takes place through cracks or gaps occuring in the molding to form paths from the outside of the molding to the surface of the IC chip. The moisture which reaches the IC surface causes undesirable corrosion of the semiconductor constituting the IC chip and leads to malfunction of the chip.
  • Patent Abstracts of Japan, Vol. 9, No. 106 (E313) [1829] May 10, 1985, and JP-A-59 231810 discloses how to obtain a semiconductor device having high humidity resistance by a method wherein the surfaces of a semiconductor chip, pads and wires are covered by an Si3N4 film, and moreover sealed with a plastic material.
  • Figure 1 is a schematic diagram showing a sculpturema CVD apparatus for use in embodying the present invention.
  • Figure 2(A) is a schematic plan view showing an arrangement of IC chip assemblies.
  • Figure 2(B) is a partial cross sectional view taken along A-A line of Figure 2(A).
  • Figure 2(C) is a partial expanded view of Figure 2(A).
  • Figure 3 is a partial expanded view of Figure 2(C).
  • FIG. 1 is a schematic cross sectional diagram showing a plasma CVD apparatus.
  • the apparatus comprises a depostion chamber 1, a loading-unloading chamber 7 coupled to the deposition chamber 1 through a gate valve 9, a pair of mesh or grid electrodes 11 and 14 provided in the deposition chamber 1, a gas feeding system 3, a vacuum pump 20 connected to the chamber 1 through a valve 21, and a high frequency power source 10 for supplying electric energy between the electrode 11 and 14 through a transformer 26.
  • the mid point 25 of the secondary coil of the transformer 26 is grounded.
  • the gas feeding system includes three sets of flow rate meters 18 and valves 19.
  • the high frequency energy inputted to the electrodes 11 and 14 causes a positive column glow discharge therebetween.
  • the glow discharge region (deposition region) is confined by a four-sided frame 40 in order to avoid undesirable deposition outside the region.
  • the frame 40 is supported by a supporter 40 and may be a grounded metal frame or an insulating frame.
  • a number of substrate assembly 2 are supported by the frame 40 and disposed in parallel with intervals of 3 to 13 cm, e.g. 8 cm.
  • a plurality of IC chips are mounted on each assembly 2. AC electric energy is supplied to the assembly (the chips) from an AC source 24 through a bias device 12.
  • the chip assembly is comprised of holding jigs 44 and lead frames 29 interposed and supported between the adjacent jigs as illustrated in Figs.2(A) and 2(B).
  • IC chips have been mounted on appropriate positions (dies) of the lead frame 29 and electrically connected with leads arranged therearound by means of Au wiring 39.
  • Fig.2(C) shows a unit structure of the frame corresponding to leads necessary for one chip, but the illustration of the lead in the right side of the chip is dispensed with in the figure.
  • the unit structure repeatedly appears along the frame between the upper and lower rails of the frame.
  • One frame contains 5 to 25 unit structures, e.g. 18 units.
  • a number of the jigs are integrally assembled in order to support 10 to 50 frames, e.g. 10 as shown in Fig.2(A).
  • a number of lead frames are mounted on the assemblies 2 after completing the electrical connection between the chips and the associated leads.
  • the assemblies are disposed in the deposition chamber at a constant interval through the loading-unloading chamber 7.
  • NH3, Si2H6 and N2 carrier gas
  • NH3, Si2H6 and N2 carrier gas
  • the introduction molar ratio of NH3/Si2H6/N2 is 1/3/5.
  • Positive column glow discharge takes place when high frequency energy is input to the pair of electrodes 11 and 14 at 1 KW and 1 to 500 MHz, e.g. 13.56 MHZ.
  • the assemblies are removed from the chamber and undergo moulding process.
  • Each assembly is placed on a moulding apparatus as it is.
  • An epoxy material (410A) is injected from the center position 42, which is depicted for explanatory purpose in Fig.2(A), to an appropriate portion around each chip with suitable moulds and form an external chip package.
  • the IC's are separated from the frames by cutting the ends of the leads.
  • Each lead, which extends beyond the moulding structure, is then bended downwardly in order to form the legs of a "worm IC".
  • the leads are cleaned by acid washing, followed by solder plating.
  • the protective film of silicon nitride is covering the surfaces of the CI chip mounted on the die 35′, contacts 38, the Au wiring 39 and the leads 37.
  • the protective coating By virtue of the protective coating, the chip is protected from the attach of moisture which may invade the same through cracks 33 or gaps 33′′′ between the mould and the lead. Such a crack is particularly likely at the wiring (33′) or at the corner edge (33 ⁇ ).
  • the IR absorbing spectrum shows a peak at 864 cm ⁇ 1 which is indicative of Si-N bondings.
  • the withstanding voltage level of the insulating coating was measured to be 8 x 106 V/cm.
  • the resistivity of the coating is measured to be 2 x 105 ohm centimeter.
  • the reflective index of the coating is measured to be 1.7 to 1.8.
  • the protection ability of the coating was evaluated by effecting HF etching.
  • the etching speed was 0.3 to 1.0 nm/sec, which was substantially small as compared to the figure, about 3.0 nm/sec, of conventional silicon nitride coatings 3.0 nm/sec.
  • the thickness of such an excellent coating may be sufficiently 100 nm (30 to 500 nm in general).
  • IC devices manufactured in accordance with the present invention were subjected to PCT (pressure cooker test) under 10 atmospheres at 150°C for 100 hours. As a result, there was found no defective after the test, and the fraction defective was decreased from 50 - 100 fits to 5 - 10 fits. One fit means 10 ⁇ 8.
  • Diamond like carbon, silicon oxide or other insulating material can be deposited to form the protective coating.
  • the embodiment was IC chips, the present invention can be applied to other electric devices, such as resistors and capacitors. Also, the present invention is effective in case utilizing other bonding methods such as flip chip bonding and solder bump bonding.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Claims (7)

  1. Procédé pour la production de dispositifs électriques, comprenant les étapes consistant à:
       réaliser la connexion électrique entre un chip et au moins un conducteur (37) associé,
       alimenter un gaz de réaction dans une chambre de réaction (1),
       revêtir ledit chip et ledit conducteur (37) d'un matériau isolant par DCVPE,
       blinder ledit chip et ledit conducteur à l'aide d'une résine organique, de manière qu'une partie dudit conducteur ressorte de l'enceinte de résine organique,
    caractérisé par
       le dépôt dudit chip et dudit conducteur entre une paire d'électrodes (13, 14) dans ladite chambre de réaction (1) d'un appareil de DCV au plasma,
       l'application d'une première tension alternative entre lesdites électrodes (13, 14), afin de générer une décharge luminescente, et
       l'application d'une seconde tension alternative sur ledit chip et ledit conducteur.
  2. Procédé suivant la revendication 1, caractérisé en ce que la fréquence de ladite première tension alternative est supérieure à celle de ladite seconde tension alternative.
  3. Procédé suivant la revendication 2, caractérisé en ce que la fréquence de ladite première tension alternative est de 1 à 500 MHz et la fréquence de ladite seconde tension alternative est de 1 à 500 kHz.
  4. Procédé suivant la revendication 1, caractérisé en ce qu'une pluralité de chips sont connectés à une pluralité desdits conducteurs (37) qui sont formés de manière solidaire avec une connexion en cadre (29).
  5. Procédé suivant la revendication 4, caractérisé en ce que lesdits conducteurs (37) sont séparés de ladite connexion en cadre (29) après la formation de ladite enceinte.
  6. Procédé suivant la revendication 1, caractérisé en ce que ladite connexion entre ledit chip et ledit conducteur (37) est réalisée par liaison de cablage.
  7. Procédé suivant la revendication 1, caractérisé en ce qu'une pluralité desdits chips sont connectés à une pluralité desdits conducteurs, et par, au cours de ladite étape de dépôt, le placement d'un porte-substrat (2) dans ladite chambre de réaction (1), ledite support (2) portant ladite pluralité de chips avec les conducteurs associés,
       le retrait dudit support (2) de ladite chambre (1) après ledit procédé au plasma,
       le placement dudit support (2) portant ladite pluralité de chips avec les conducteurs associés dans un appareil à mouler.
EP89108973A 1988-05-19 1989-05-18 Procédé pour produire un dispositif électrique Expired - Lifetime EP0342681B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP63124360A JPH01292846A (ja) 1988-05-19 1988-05-19 電子装置作製方法
JP124361/88 1988-05-19
JP124360/88 1988-05-19
JP63124361A JPH01292833A (ja) 1988-05-19 1988-05-19 電子装置作製方法

Publications (3)

Publication Number Publication Date
EP0342681A2 EP0342681A2 (fr) 1989-11-23
EP0342681A3 EP0342681A3 (en) 1990-07-04
EP0342681B1 true EP0342681B1 (fr) 1995-08-09

Family

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Application Number Title Priority Date Filing Date
EP89108973A Expired - Lifetime EP0342681B1 (fr) 1988-05-19 1989-05-18 Procédé pour produire un dispositif électrique

Country Status (5)

Country Link
US (1) US5096851A (fr)
EP (1) EP0342681B1 (fr)
KR (1) KR900019177A (fr)
CN (1) CN1020317C (fr)
DE (1) DE68923732T2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451550A (en) * 1991-02-20 1995-09-19 Texas Instruments Incorporated Method of laser CVD seal a die edge
WO2004061959A1 (fr) * 2002-12-18 2004-07-22 Freescale Semiconductor, Inc. Circuit integre mis sous boitier a l'aide d'un fil isole

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6613978B2 (en) 1993-06-18 2003-09-02 Maxwell Technologies, Inc. Radiation shielding of three dimensional multi-chip modules
US5880403A (en) 1994-04-01 1999-03-09 Space Electronics, Inc. Radiation shielding of three dimensional multi-chip modules
US6455864B1 (en) 1994-04-01 2002-09-24 Maxwell Electronic Components Group, Inc. Methods and compositions for ionizing radiation shielding
US6261508B1 (en) 1994-04-01 2001-07-17 Maxwell Electronic Components Group, Inc. Method for making a shielding composition
US6720493B1 (en) 1994-04-01 2004-04-13 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
KR100202668B1 (ko) * 1996-07-30 1999-07-01 구본준 크랙 방지를 위한 반도체 패키지와 그 제조방법 및 제조장치
US6368899B1 (en) 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
US6432737B1 (en) 2001-01-03 2002-08-13 Amkor Technology, Inc. Method for forming a flip chip pressure sensor die package
US6441503B1 (en) 2001-01-03 2002-08-27 Amkor Technology, Inc. Bond wire pressure sensor die package
US6661080B1 (en) 2001-06-28 2003-12-09 Amkor Technology, Inc. Structure for backside saw cavity protection
US6399418B1 (en) * 2001-07-26 2002-06-04 Amkor Technology, Inc. Method for forming a reduced thickness packaged electronic device
US6586824B1 (en) 2001-07-26 2003-07-01 Amkor Technology, Inc. Reduced thickness packaged electronic device
US7382043B2 (en) * 2002-09-25 2008-06-03 Maxwell Technologies, Inc. Method and apparatus for shielding an integrated circuit from radiation
US7191516B2 (en) * 2003-07-16 2007-03-20 Maxwell Technologies, Inc. Method for shielding integrated circuit devices
US9953952B2 (en) * 2008-08-20 2018-04-24 Infineon Technologies Ag Semiconductor device having a sealant layer including carbon directly contact the chip and the carrier
DE102016106137B4 (de) * 2016-04-04 2023-12-28 Infineon Technologies Ag Elektronikvorrichtungsgehäuse umfassend eine dielektrische Schicht und ein Kapselungsmaterial
DE102016109349A1 (de) * 2016-05-20 2017-11-23 Infineon Technologies Ag Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4056681A (en) * 1975-08-04 1977-11-01 International Telephone And Telegraph Corporation Self-aligning package for integrated circuits
US4091407A (en) * 1976-11-01 1978-05-23 Rca Corporation Combination glass/low temperature deposited Siw Nx Hy O.sub.z
JPS55163850A (en) * 1979-06-08 1980-12-20 Fujitsu Ltd Semiconductor device
JPS5627941A (en) * 1979-08-17 1981-03-18 Hitachi Ltd Manufacture of semiconductor device
JPS56108247A (en) * 1980-01-31 1981-08-27 Sanyo Electric Co Ltd Semiconductor device
JPS5745259A (en) * 1980-09-01 1982-03-15 Hitachi Ltd Resin sealing type semiconductor device
JPS57210646A (en) * 1981-06-19 1982-12-24 Seiko Epson Corp Resin-sealed semiconductor device
JPS59231840A (ja) * 1983-06-14 1984-12-26 Semiconductor Energy Lab Co Ltd 半導体装置作成方法
JPS59231810A (ja) * 1983-06-14 1984-12-26 Toshiba Corp 電子ビ−ム露光装置
JPS601846A (ja) * 1983-06-18 1985-01-08 Toshiba Corp 多層配線構造の半導体装置とその製造方法
JPS60107841A (ja) * 1983-11-16 1985-06-13 Hitachi Ltd 窒化シリコン膜の形成方法
JPS61148824A (ja) * 1984-12-21 1986-07-07 Mitsubishi Electric Corp 半導体装置の製造方法
JPS61258436A (ja) * 1985-05-13 1986-11-15 Nec Corp 半導体装置の製造方法
US4729010A (en) * 1985-08-05 1988-03-01 Hitachi, Ltd. Integrated circuit package with low-thermal expansion lead pieces
KR920003431B1 (ko) * 1988-02-05 1992-05-01 가부시끼가이샤 한도다이 에네르기 겐뀨쇼 플라즈마 처리 방법 및 장치

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451550A (en) * 1991-02-20 1995-09-19 Texas Instruments Incorporated Method of laser CVD seal a die edge
US6355973B1 (en) 1991-02-20 2002-03-12 Texas Instruments Incorporated Integrated circuit having a sealed edge
WO2004061959A1 (fr) * 2002-12-18 2004-07-22 Freescale Semiconductor, Inc. Circuit integre mis sous boitier a l'aide d'un fil isole
US7138328B2 (en) 2002-12-18 2006-11-21 Freescale Semiconductor, Inc. Packaged IC using insulated wire

Also Published As

Publication number Publication date
US5096851A (en) 1992-03-17
CN1020317C (zh) 1993-04-14
KR900019177A (ko) 1990-12-24
CN1039504A (zh) 1990-02-07
DE68923732T2 (de) 1996-01-18
EP0342681A2 (fr) 1989-11-23
DE68923732D1 (de) 1995-09-14
EP0342681A3 (en) 1990-07-04

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