EP0333864B1 - Emitterfolgerschaltung - Google Patents

Emitterfolgerschaltung Download PDF

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Publication number
EP0333864B1
EP0333864B1 EP88907769A EP88907769A EP0333864B1 EP 0333864 B1 EP0333864 B1 EP 0333864B1 EP 88907769 A EP88907769 A EP 88907769A EP 88907769 A EP88907769 A EP 88907769A EP 0333864 B1 EP0333864 B1 EP 0333864B1
Authority
EP
European Patent Office
Prior art keywords
emitter follower
mos transistor
circuit
source
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP88907769A
Other languages
English (en)
French (fr)
Other versions
EP0333864A4 (de
EP0333864A1 (de
Inventor
Yasuhiro Ishii
Isao Room 25 Villa Hakuraku Fukushi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0333864A1 publication Critical patent/EP0333864A1/de
Publication of EP0333864A4 publication Critical patent/EP0333864A4/de
Application granted granted Critical
Publication of EP0333864B1 publication Critical patent/EP0333864B1/de
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Definitions

  • the present invention relates to an emitter follower circuit, and particularly to an emitter follower circuit employing a metal oxide semiconductor transistor.
  • an emitter follower circuit is used as an input circuit for inputting a signal or an output circuit for outputting a signal.
  • Bipolar-CMOS bipolar-complementaly metal oxide semiconductor
  • FIG .1 illustrates a level converter, which includes a conventional emitter follower circuit.
  • a differential circuit is made up of transistors Q1 and Q2.
  • the transistor Q1 is supplied with a voltage signal through a terminal 10, and the transistor Q2 supplied with a reference voltage V REF through a terminal 11.
  • Two output signals derived from the differential circuit pass through emitter follower circuits 12 and 13 including transistors Q3 and Q4, respectively, and are supplied to a flip-flop 14, which includes MOS transistors P1, P2, N1 and N2.
  • An output signal derived from the flip-flop 14 passes through an inverter 15 including MOS transistors P3 and N3, and is output through a terminal 16.
  • the flip-flop 14 has a function of converting the ECL (Emitter Coupled Logic) level of a supplied signal to the MOS level.
  • the emitter follower circuits 12 and 13 include transistors Q5 and Q6, respectively, which function as constant-current sources, each of which is supplied by a fixed voltage V R through a terminal 17.
  • N-channel MOS transistors N4 and N5 are current source resistors, and conduct when a chip select signal CS applied through a terminal 18 is held at a high (H) level, so that emitter follower circuits 12 and 13 are held in the active state.
  • the MOS transistors N4 and N5 are cut off when the chip select signal C5 is switched to a low (L) level, so that the emitter follower circuits 12 and 13 are switched to the inactive state.
  • FIG.2 illustrates a sense amplification circuit for a memory including a conventional emitter follower circuit.
  • terminals 20a and 20b are connected to bit lines (not shown) which are paired.
  • the voltages of the terminals 20a and 20b pass through emitter follower circuits 21 and 22 including transistors Q10 and Q11, respectively, and are then applied to a differential circuit made up of transistors Q12 and Q13.
  • the collectors of the transistors Q12 and Q13 are coupled to corresponding current/voltage conversion circuits 25 and 26 through corresponding common lines 23 and 24, which are used in common with differential circuits associated with other bit lines.
  • a fixed voltage V CON is applied, through a terminal 30, to the base of transistors Q14 and Q15, which are included in the current/voltage conversion circuits 25 and 16, respectively.
  • Collector currents of the transistors Q14 and Q15 are converted to corresponding voltages by the MOS transistors N12 and N13, respectively, which function as resistors.
  • the output signals of the current/voltage conversion circuits 25 and 26 are supplied to a differential amplifier (not shown) of the next stage through terminals 27a and 27b, respectively.
  • the N-channel MOS transistors N10 and N11 included in the emitter follower circuits 21 and 22 are current source resistors.
  • the MOS transistors N10 and N11 conduct when a bit select signal BS supplied from a terminal 28 through an inverter is held at L level, whereby the emitter follower circuits 21 and 22 are held in the active state.
  • the MOS transistors N10 and N11 are cut off when the bit select signal BS is held at H level, so that the emitter follower circuits 21 and 22 are held in the inactive state.
  • FIG.1 when the emitter follower circuits 12 and 13 are switched to the inactive state, the potential of the emitter of each of the transistors Q3 and Q4 becomes unstable. Therefore, the flip-flop 14 becomes unstable, and the input signal of the inverter is unnecessarily inverted. It is noted that the circuit of FIG.1 is wasteful of current when the MOS transistors P1, P2, N1 and N2 included in the flip-flop 14 and the inverter 15 are inverted. The above leads to an increase of consumption power.
  • the potential of emitter of each of the transistors Q10 and Q11 becomes unstable, when the emitter follower circuits 21 and 22 are switched to the inactive state.
  • the emitter potentials of the transistors Q10 and Q11 increase to the ground level (Vcc) as time goes. Therefore, it takes long for the emitter potential of each of the transistors Q10 and Q11 to become equal to the predetermined potential when the emitter follower circuits 21 and 22 is set to the active state again. The above prevents the sense amplifier from operating at high speeds.
  • An object of the present invention is to provide an emitter follower circuit capable of reducing power consumption in the level converter circuit and enabling it to be possible to operate the sense amplification circuit at high speeds.
  • the present invention relates to an emitter follower circuit including an emitter follower transistor, and a power source coupled to the emitter of the emitter follower transistor.
  • the power source includes a MOS transistor, and the emitter follower circuit is switched between active and inactive states by switching the MOS transistor by a control signal.
  • the present invention has the following essential features. That is, between the source and drain of the MOS transistor, there is provided current path means for providing a resistance considerably larger than the resistance of the MOS transistor provided when conducting, and when the MOS transistor is at least cut off passing an extremely small current therethrough at that time.
  • the extremely small current passes through the current path means during the time when the MOS transistor is OFF so that the emitter potential of the emitter follower transistor can be stabilized.
  • FIG.3 is a circuit diagram of a level converter circuit in which an emitter follower circuit of an embodiment of the present invention is employed.
  • Emitter follower circuits 12A and 13A correspond to emitter follower circuits 12 and 13, respectively.
  • a resistor R1 is connected across the source and drain of the MOS transistor N4 provided in the emitter follower circuit 12A.
  • a resistor R2 is connected across the drain and source of the MOS transistor N5.
  • the resistors R1 and R2 have resistances which are considerably larger than an ON resistance of each of the MOS transistors N4 and N5. It is preferable that each of the resistors R1 and R2 has a resistance as large as 10 times the ON resistance. Generally, the ON resistance of a MOS transistor is a few hundred ohms. Therefore, each of the resistors R1 and R2 is formed by a resistor having a resistance equal to or larger than a few kilo-ohms.
  • a P-channel MOS transistor may be substituted for the resistor R1 as the current path means.
  • the source and drain of the MOS transistor P4 are connected to the source and drain of the MOS transistor N4, respectively.
  • the gate of the MOS transistor P4 is connected to the terminal 18.
  • the ON resistance of the MOS transistor P4 is selected in the same way as the resistor R1. In the case of FIG. 4, an extremely small current passes through the MOS transistor P4, only when the MOS transistor N4 is cut off and thereby the emitter follower circuit 12A is held in the inactive state.
  • resistor R2 may be replaced with a P-channel MOS transistor as described previously.
  • FIG.5 illustrates a sense amplifier to which the present invention is applied.
  • Emitter follower circuits 21A and 22A correspond to the aforementioned emitter follower circuits 21 and 22.
  • a resistor R3 is connected across the drain and source of the MOS transistor N10 provided in the emitter follower circuit 21A, and a resistor R4 is connected across the drain and source of the MOS transistor N11.
  • the resistances of the resistors R3 and R4 are set considerably large, compared with the MOS transistors N10 and N11. Thereby, even when the bit select signal is held at H level and therefore the emitter follower circuits 21A and 22A are held in the inactive state, extremely small currents pass through the resistors R3 and R4. Therefore, the potentials of the emitters of the transistors Q10 and Q11 are fixed to levels which are lower by a fixed voltage than the potential of the terminals 20a and 20b, respectively. Thereby, it becomes possible to reduce the time it takes for the emitter potential of each of the transistors Q10 and Q11 to become equal to the predetermined potential when the emitter follower circuits 21A and 22A are switched to the active state.
  • the P-channel MOS transistor as shown in FIG .4 may be substituted for each of the resistors R3 and R4 as the current path means.
  • the emitter follower circuit of the present invention As described above, according to the emitter follower circuit of the present invention, an extremely small current passes through the emitter follower circuit when held in the inactive state, and thereby the emitter potential of the emitter follower transistor can be settled. As a result, it becomes possible to reduce the consumption power in the level converter circuit and operate the sense amplification circuit at high speeds. Consequently, the present invention is effective to practical use.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
  • Manipulation Of Pulses (AREA)
  • Static Random-Access Memory (AREA)

Claims (3)

1. Eine Emitterfolgerschaltung mit einem Emitterfolgertransistor (Q₅, Q₆, Q₁₀, Q₁₁) und einer mit dem Emitter des genannten Emitterfolgertransistors (Q₅, Q₆, Q₁₀, Q₁₁) gekoppelten Stromquelle, welche Stromquelle einen MOS-Transistor (N₄, N₅) beinhaltet, wobei die genannte Emitterfolgerschaltung durch das Schalten des genannten MOS-Transistors (N₄, N₅) durch ein Steuersignal (CS) zwischen aktiven und passiven Zuständen geschaltet wird,
dadurch gekennzeichnet, daß die genannte Emitterfolgerschaltung ein Stromwegmittel (R₁, R₂, P₄), welches zwischen der Quelle und der Senke des genannten MOS-Transistors (N₄, N₅) vorhanden ist, für das Bereitstellen eines Widerstandes umfaßt, der beträchtlich höher ist als der Widerstand des MOS-Transistors (N₄, N₅), der vorhanden ist, wenn er leitend ist, und wenn der MOS-Transistor (N₄, N₅) wenigstens gesperrt ist und durch ihn zu der Zeit ein extrem niedriger Strom fließt.
2. Eine Emitterfolgerschaltung nach Anspruch 1, dadurch gekennzeichnet, daß das genannte Stromwegmittel (R₁, R₂, P₄) einen Widerstand (R₁, R₂) beinhaltet.
3. Eine Emitterfolgerschaltung nach Anspruch 1, bei welcher das genannte Stromwegmittel (R₁, R₂, P₄) einen MOS-Transistor (P₄) eines anderen Leitungstyps als der des MOS-Transistors (N₄, N₅), welcher als genannte Stromquelle dient, umfaßt, und das Gate, der Drain und die Source des genannten MOS-Transistors (P₄) des genannten Stromwegmittels mit dem Gate, der Source bzw. dem Drain des genannten MOS-Transistors (N₄, N₅) der genannten Stromquelle verbunden sind.
EP88907769A 1987-09-17 1988-09-13 Emitterfolgerschaltung Expired EP0333864B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62233190A JPS6474823A (en) 1987-09-17 1987-09-17 Emitter follower circuit
JP233190/87 1987-09-17

Publications (3)

Publication Number Publication Date
EP0333864A1 EP0333864A1 (de) 1989-09-27
EP0333864A4 EP0333864A4 (de) 1989-12-18
EP0333864B1 true EP0333864B1 (de) 1992-07-22

Family

ID=16951153

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88907769A Expired EP0333864B1 (de) 1987-09-17 1988-09-13 Emitterfolgerschaltung

Country Status (5)

Country Link
US (1) US4958094A (de)
EP (1) EP0333864B1 (de)
JP (1) JPS6474823A (de)
DE (1) DE3873071T2 (de)
WO (1) WO1989002677A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2743401B2 (ja) * 1988-10-06 1998-04-22 日本電気株式会社 Ｅｃｌ回路
JPH082019B2 (ja) * 1989-09-13 1996-01-10 株式会社東芝 レベル変換回路
JP2547863B2 (ja) * 1989-10-06 1996-10-23 東芝マイクロエレクトロニクス株式会社 ソースカップルドｆｅｔロジック形出力回路
JP2518068B2 (ja) * 1989-11-17 1996-07-24 日本電気株式会社 電流切換回路
IT1236879B (it) * 1989-11-22 1993-04-26 Sgs Thomson Microelectronics Circuito elettronico comparatore
US5216298A (en) * 1989-12-14 1993-06-01 Mitsubishi Denki Kabushiki Kaisha ECL input buffer for BiCMOS
US5017812A (en) * 1990-03-20 1991-05-21 Integrated Device Technology, Inc. Combined ECL-to-TTL translator and decoder
JPH04172713A (ja) * 1990-11-06 1992-06-19 Fujitsu Ltd レベル変換回路
JP3001014B2 (ja) * 1991-03-13 2000-01-17 富士通株式会社 バイアス電圧発生回路
US5315167A (en) * 1992-04-09 1994-05-24 International Business Machines Corporation Voltage burn-in scheme for BICMOS circuits
US5355035A (en) * 1993-01-08 1994-10-11 Vora Madhukar B High speed BICMOS switches and multiplexers
JP2570185B2 (ja) * 1994-07-08 1997-01-08 日本電気株式会社 サンプルホールド回路
JP3149759B2 (ja) * 1995-11-17 2001-03-26 日本電気株式会社 ラッチ回路
US6380794B1 (en) * 2000-03-24 2002-04-30 Sige Microsystems Inc. Hybrid circuit having current source controlled by a comparator

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4953365A (de) * 1972-09-25 1974-05-23
US4099070A (en) * 1976-11-26 1978-07-04 Motorola, Inc. Sense-write circuit for random access memory
JPS5428707A (en) * 1977-08-08 1979-03-03 Tokyo Yogyo Kk Container for molten metal for use in iron producing process
DE2740353C2 (de) * 1977-09-07 1982-05-13 Siemens AG, 1000 Berlin und 8000 München ECL-kompatibler Registerbaustein mit bipolaren Speicherzellen
JPS5883434A (ja) * 1981-11-13 1983-05-19 Hitachi Ltd 半導体集積回路装置
JPS5912661A (ja) * 1982-07-13 1984-01-23 Fujitsu Ltd 閾値可変型差動信号レシ−バ
US4604533A (en) * 1982-12-28 1986-08-05 Tokyo Shibaura Denki Kabushiki Kaisha Sense amplifier
JPS60141019A (ja) * 1983-12-28 1985-07-26 Nec Corp 論理回路
JPS60176978A (ja) * 1984-02-22 1985-09-11 株式会社イナックス 高強度セメント製品の製法
JPS6145491A (ja) * 1984-08-10 1986-03-05 Fujitsu Ltd 半導体記憶装置
JPS62159916A (ja) * 1986-01-09 1987-07-15 Toshiba Corp レベル変換回路
US4713560A (en) * 1986-06-05 1987-12-15 Fairchild Semiconductor Corporation Switched impedance emitter coupled logic gate
JPS635617A (ja) * 1986-06-25 1988-01-11 Hitachi Ltd 半導体回路
US4868421A (en) * 1987-02-24 1989-09-19 Fairchild Semiconductor Corporation Bimos circuit that provides low power dissipation and high transient drive capability
US4858183A (en) * 1987-06-02 1989-08-15 Texas Instruments Incorporated ECL high speed semiconductor memory and method of accessing stored information therein
JPS6424628A (en) * 1987-07-21 1989-01-26 Fujitsu Ltd Emitter coupled logic circuit

Also Published As

Publication number Publication date
JPS6474823A (en) 1989-03-20
EP0333864A4 (de) 1989-12-18
WO1989002677A1 (fr) 1989-03-23
DE3873071T2 (de) 1992-12-03
DE3873071D1 (de) 1992-08-27
EP0333864A1 (de) 1989-09-27
US4958094A (en) 1990-09-18

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