Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
  • H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
  • H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
  • H02P25/022—Synchronous motors
  • H02P25/024—Synchronous motors controlled by supply frequency
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
  • H02P2207/00—Indexing scheme relating to controlling arrangements characterised by the type of motor
  • H02P2207/05—Synchronous machines, e.g. with permanent magnets or DC excitation

Definitions

• This invention is concerned with a circuit generating two- or three phase signal that can be utilized as current reference for a servo-amplifier that controls synchronous motors and in particular synchronous- servo-motors.
• a system for example requires the use of cams and/or variable reluctance detectors. These systems are closely dependent on the motor shape for which they were designed, their mechanical form being tied to the polar form, of the motor. Their output is therefore strictly dependent on the mechanical shape of the cams and/or the reluctance of the
• resolver installed on the motor axis.
• Theis resolver must have the same polar configuration as the motor. "This system therefore does not permit the use of any resolver with any motor. Furthermore, it does not allow any 15. simple continuous and automatic phase processing, which is however necessary for optimization of the servo-system efficiency. The only possible motor phase process must be achieved by means of a microcomputer, which makes the whole operation complicated and expensive.
• the main purpose of this invention is therefore to embody a simple and economical circuit allowing the elimination of any dependence 10. between the number of poles of the resolver and of the motor.
• Another purpose is to be able to utilize the same circuit used for the generation of motor control "phases" to carry out phase shifts depending on other variables, such as, for example, speed, current or voltage. This is 15. extremely important for the servo-system's performance in its entire operational range, but especially at high speed and/or in presence of high currents.
• Fig. 1 is an overall circuit diagram of the apparatus;
• Fig. 2 is a detailed diagram of a first embodiment ' that does not include phase correction;
• Fig. 3a up to 3i show voltage wave forms at various points shown on the diagram of fig. 2; 5.
• Fig. 4 and 5 are schematic views of further embodiments, that show double cycler
• Figs. 6a, 6b and 6c are further embodiments of the circuit allowing 10. the "AUTOMATIC PHASE CORRECTION";
• Figs. 7a and 7b show, as a diagram, the wave-forms at various points of the circuit in fig. 6b.
• - 7a shows the circuit 6b without phase correction that means
• V 12 0 V. -
• V 12 different from 0 V.
• Figs. 8 and 9 are diagrams of further embodiments of the circuit allowing phase correction
• Fig. 10 is a detail of the circuit in Fig. 6b, to which an improve- 20. ment has been made, for a better linearization
• Fig. 11a to 11f show the voltage at various points of the circuit illustrated in Fig. 10 before and after correction;
• Fig. 12a shows a circuit where the correction is made adding one short delay in serial between V5 and the output V6 25. (see also Fig. 6b) ;
• Fig. 12b, 12c and 12d show the voltage at various points of the circuit in fig. 12a.
• Fig. 1 shows the fundamental flow chart of a servo-mechanism according to this invention. It involves a syncrhonous servomotor M which can be three-phase, a resolver RES, assembled coaxial to the motor M for the detection of polar position and a tachymetric generator "G" for the detection of angular speed.
• a syncrhonous servomotor M which can be three-phase
• a resolver RES assembled coaxial to the motor M for the detection of polar position
• G tachymetric generator
• the servomotor M is controlled by a current generator for example three-phase (current loop) which, taking data from the resolver, generates the three control currents through one processing step, one memory, Digital to Analogic (D/A) converters and multipliers.
• the "phase" of the three currents is controlled by the current
• the difference between the two voltages, suitably amplified and 20.corrected, represents the amplitude multiplication coefficient of the three vector current signals feeding the servomotor M.
• the proposed apparatus includes the well known "angle measurement system", starting from a resolver
• a voltage V5 (fig. 3g) can be obtained at the common point on the RC circuit, its phase can differ from the resolver primary- input V3. This phase is strictly proportional to the mechanical 5. angle between the rotor and the stator axis of the resolver. This variation is shown in fig. 3g as "arrow movement"*.
• Fig. 2 we also have: a) the high frequency oscillating circuit "A" (2.56 MHz in this case) generates the V1 voltage high frequency. 10. b) the M1/M2 frequency divider “B” divides the 2.56 MHz frequency by 256 to obtain 10 KHz. (in this case) . c) the low-pass filter "C” eliminating the harmonic of the square wave V2, so transforming it into a pure sine wave V3 (fig. 3a) having the same fundamental frequency of "V2" (10 KHz. in this 15. case).
• This digital number 20 serves as a "storage address" to extract the data from the memory concerning the wave forms used to control the motor.
• Wave V3 (fig. 3a) is transformed into square wave V7 (fig. 3b) .
• Wave V5 (fig. 3g) is transformed into square wave V6 (fig. 3h) .
• 25.Eig. 3h shows four waves, V6, marked 1, 2, 3 and 4. Each one of these detects a specific phase difference to V3 (corresponding to the rotation) .
• V6 and V7 control the state of a bistable circuit ( ) , with set S and reset R input.
• bistable commutation occurs during positive transition edge of input signal (can be reversed) .
• the signal V8 (fig. 3i) is obtained, that remains positive (or, vice-versa, negative) for a period directly propor ⁇ tional to the value of the mechanical angle, between rotor and 10. stator of the resolver, or rather, to the value of the phase difference angle between the two waves V3 and V5.
• Fig. 3i shows the "V8" signal corresponding to the four different angular phase difference values "V6" the four waves V6 showed in Fig. 3h as 1, 2, 3 and 4.
• V8 is thus utilized as “enable” for a COUNTER (binary type in this case) .
• the counting clock is given by V1 signal.
• the counter must have a maximum capacity equal to the number of clock (V1 pulses) , which can transit during one cycle of signal V3 or V5, corresponding to the divider ratio (b) as in 20. F g- 2.
• a logic circuit generates a signal allowing to reset' synchronously the counter at the beginning of each counting cycle. Then the counter process is activated by the signal "V8 enable” and clock "V1".
• the new content is dependent on the value of the mechanical angle and is then transferred as address to the memory through a latch 5.
• Control voltage (V10) applied to the latch (fig. 3f) (negative logic in this case) activates this transfer function.
• processing cycle time a period equal to two cycles of frequency V3 (fig. 3c - and 4) .
• V7 (here 10 KHz) is applied to a (bistable) flip-flop utilized as a by two frequency divider to generate the signal at 5 KHz (V10) (fig. 3c and 4) .
• Fig. 3a to 3i show all the wave forms of the utilized signals, in particular:
• Fig. 3a shows the voltage wave form of the (V3) 10 KHz. frequency feeding the resolver rotor.
• Fig. 3b shows the square wave signal V7, as result of signal V3 squaring.
• Fig 3c shows the square wave signal V10 resulting from the frequency 5. division of signal V7 (see fig. 4 as well) .
• Fig. 3d shows the control voltage that allows the successive switching commutation of selectors S1, S2 and S3, synchronized with the three memory cells read in each single cycle.
• Fig. 3e shows the counter "RESET" signal V11 (see fig. 4 as well) 10. positive edge action in this case.
• Fig. 3f shows the latch signal "V10" (negative edge) used to transfer and store in memory (address latch) the value contained in the counter.
• Fig. 3g shows the V5 signal.
• the signal is shifted with respect to 15. the reference signal V3.
• the phase displacement depends on the phase difference existing between the rotor polar axis and the stator polar axis of the resolver.
• Fig. 3h shows the V6 signal, corresponding to the squaring of four different V5 signals (time depending) .
• Fig. 3i shows four “enable” signals (V8) obtained on the flip-flop fig. 4 from the combination of “set” positive edge (V10) and “reset” (signal positive edge V6) .
• V10 is used as a SET for a flip-flop or bistable circuit while the ' positive edge of signal "V6" is used as a "RESET” (it is possible to invert functions and polarities) .
• Signal V8 is now utilized as enable control signal for the counter, so the counter will count and increment only during the positive 10. cycle of signal V8 (see fig. 3 and 4) .
• signal V8 can only be positive during phase A of signal V10 (fig. 3c) that means the "counting phase” of the cycle in phase A only, because the start "SET” (CORRESPONDING TO THE POSITIVE EDGE OF V10) takes place only in phase A.
• the RESET of the counter (fig. 4) is obtained by signal V11, being # positive if V7 and V10 are negative (NAND V7:V10) .
• the reset counter is ready to start a new cycle.
• the contents of the counter at the end of the next cycle will depend on the value of the mechanical angle and will serve as an address to the memory on which two (bi-phase) or three (three-phase) numbers that contain the 10. current vector information correspond for each address.
• DAC digital to analogic converter
• the DAC will receive the digital input information sequentially in two (in case of bi-phase) sequential time, the output of the DAC through the switch SI S2 S3 synchronized with the sequentially digital input will be applied to the three sampling hold output amplifier.
• the output of the three sampling hold represents the
• the AUTOMATIC CORRECTION or automatic processing of the phase can be obtained as weel, by this system, in accordance with other factors such as: speed, current, system's power supply or anything else.
• the entire conversion system often shows a delay due to the repetition rate of the operating cycle. In our case it is 5 KHz. and the resulting delay is 200 microseconds.
• Fig. 6a shows a block diagram with the "adder" (20) connected in series to V3 - V7 line.
• FIG. 6b shows a block diagram including the "adder" (20) connected in series to V5-V6 line.
• Fig. 6c shows a particular embodiment of the adder connected in series with V5 - V6 line where an additional adder (21) can be seen receiving the weight resistances corresponding to the desired corrections (this solution is suggested where more then one correction is needed) .
• Fig. 7a shows signals V5 and V6 referred to the circuit in fig. 6b without any correction (V12 - OV) . It has been noted that no phase difference exists. Furthermore, the leading edge of signal V6 is clear, being it used to reset the bistable circuit controlling the counter.
• Fig. 7b shows the effect of the correction of signal V6 caused by a positive voltage V12 added to the voltage V5.
• the leading edge of wave V6 is shiftefd on an additional angle f ⁇ in relation to the preceding state where V12 was zero.
• the shift of both wave edges of signal "V6" can be observed.
• phase displacements can be considered linear referred to the V12 correction voltage, even if the V5 signal is sinusoidal.
• the servo-mechanism can be automatically
• Vu, Vv and Vw will therefore depend not only on the phase between the rotor and stator of the resolver but also on external correction factors.
• Fig. 10 shows the circuit connected to line V5 - V6.
• the signal V1 is obtained (fig. 11e), which represents the V13 displaced vertically.
• the signal V14 so obtained is applied to a squarer generating the signal V6 (fig. 11f).
• the one shot In presence of a positive edge of V15 (fig. 12c) , the one shot becomes negative (fig. 12d) and becomes positive again (fig. 12e) after a period of time that varies according to the correction voltage V12.
• the correction voltage V12 (see fig. 8) can be taken and converted by an "analogic to digital" converter; then the digital data is applied as a "preset value" to the counter.
• Address B1 establishes the choice of a group of cells (in this case three cells) .
• Address B2 establishes a reading sequence in the group of cells chosen by address B1.
• each group is made up of three, they are read sequen- 5. tially by a logic combination of signals V7 and V10 (see fig. 3d, 4 and 5) .
• Decoding is automatically obtained inside the memory.
• selectors S1 , S2 and S3 in order to synchronize the output of the data from the memory with the analogic outputs Vu, Vv and Vw.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Control Of Motors That Do Not Use Commutators (AREA)
• Control Of Ac Motors In General (AREA)
• Control Of Electric Motors In General (AREA)

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• 1986
  • 1986-06-06 IT IT20700/86A patent/IT1204384B/it active
• 1987
  • 1987-06-05 BR BR8707723A patent/BR8707723A/pt unknown
  • 1987-06-05 AU AU75181/87A patent/AU7518187A/en not_active Abandoned
  • 1987-06-05 WO PCT/IT1987/000058 patent/WO1987007791A1/en not_active Application Discontinuation
  • 1987-06-05 EP EP87903902A patent/EP0308421A1/en not_active Ceased
• 1988
  • 1988-02-05 KR KR1019880700132A patent/KR880701490A/ko not_active Application Discontinuation
  • 1988-02-05 DK DK060588A patent/DK60588A/da not_active Application Discontinuation

Non-Patent Citations (1)

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