EP0306941B1 - Veränderliche Bitraten-Taktwiedergewinnungsschaltung - Google Patents
Veränderliche Bitraten-Taktwiedergewinnungsschaltung Download PDFInfo
- Publication number
- EP0306941B1 EP0306941B1 EP88114680A EP88114680A EP0306941B1 EP 0306941 B1 EP0306941 B1 EP 0306941B1 EP 88114680 A EP88114680 A EP 88114680A EP 88114680 A EP88114680 A EP 88114680A EP 0306941 B1 EP0306941 B1 EP 0306941B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- signal
- output
- phase error
- signals
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
Definitions
- the present invention relates to a clock recovery circuit for recovering a reference clock signal from a digitally modulated signal and, more particularly, to a variable bit rate clock recovery circuit required for a data communication system with a variable bit rate.
- US-A-4,270,093 relates to a PLL using a VCO wherein, when the PLL is put in an abnormal state, the output of the loop filter becomes +V, and causes a transistor to turn on, thereby supplying a predetermined voltage value to the VCO for outputting an output with a predetermined frequency.
- a predetermined voltage value to the VCO for outputting an output with a predetermined frequency.
- such frequency is limited within the pull-in range at the PLL.
- Fig. 1 shows one of such circuits.
- a clock phase error detector 1 receives a demodulated signal S DEM and the reference clock signal CLK, detects a phase difference between the two signals, and outputs the phase difference as a digitized time serial signal S ER .
- Fig. 2 shows an arrangement of the clock phase error detector 1. Referring to Fig. 2, the demodulated signal S DEM is supplied to an A/D converter 6. The reference clock signal CLK is supplied to a frequency multiplier 5, a phase error detector 7, and a zero-cross detector 8.
- the frequency multiplier 5 supplies a sampling signal having a frequency twice that of the reference clock signal CLK to the A/D converter 6.
- the A/D converter 6 A/D-converts the demodulated signal S DEM by using the sampling signal.
- the digital output signal from the A/D converter 6 is input to the phase error detector 7 and the zero-cross detector 8.
- the phase error detector 7 selects an odd-numbered sampling signal, i.e., the sampled value at a zero-cross point of the demodulated signal S DEM .
- the zero-cross detector 8 selects an even-numbered sampling signal, i.e., the sampled value at a signal point of the demodulated signal S DEM , and outputs a signal representing the polarity of the selected signal to the phase error detector 7.
- the phase error detector 7 multiplies the sampled value at the zero-cross point of the detected demodulated signal by the polarity of the sampled value at the signal point of the demodulated signal detected by the zero-cross detector 8, and obtains a phase error.
- the output from the phase error detector 7 represents a correct phase error only when the polarity is inverted at a signal point before or after the phase error detection point of the demodulated signal S DEM , i.e., at the zero-cross point. Therefore, when the zero-cross detector 8 detects that the polarity is inverted at a signal point before or after the phase error detection point of the demodulated signal S DEM , it outputs a zero-cross detection pulse to a selector 9.
- the selector 9 selects an output from the phase error detector 7 by using this zero-cross detection pulse.
- the selector 9 outputs a zero or outputs a value of the immediately preceding sampling period again.
- the outputs from the selector 9 become clock phase error signals S ER .
- the timings of the demodulated signal S DEM and the reference clock signal CLK coincide with each other, the mean value of the clock phase error signals S ER converges to zero.
- an output from the clock phase error detector 1 is input to the loop filter 2. Then, high-frequency components are removed from the output in accordance with the low-pass filter characteristics of the loop filter 2.
- This loop filter 2 is generally constituted by an infinite impulse response digital filter and is an important factor determining a noise bandwidth and synchronization characteristics of the clock recovery closed loop.
- a primary type loop can be formed.
- the digital time serial signal as the output from the loop filter 2 is converted into an analog signal by the D/A converter 3.
- the output frequency and phase of the voltage controlled oscillator 4 are controlled by the output voltage from the D/A converter 13, and the output from the voltage controlled oscillator 4 becomes the reference clock signal CLK.
- Fig. 3 shows a variable bit rate clock recovery circuit according to the embodiment of the present invention.
- a clock phase error detector 1 may employ the arrangement shown in Fig. 2.
- the clock phase error detector 1 receives a demodulated signal S DEM and a reference clock signal CLK, and outputs a clock phase error signal S ER having a value proportional to a phase difference between the signals S DEM and CLK.
- the detected clock phase error signal S ER is input to a loop filter 2.
- the loop filter 2 removes high-frequency components such as noise from the signal S ER .
- the loop filter 2 has low-pass filter characteristics which is an important factor determining a noise bandwidth, synchronization characteristics, and response characteristics of the loop.
- the type and the constant of the filter are selected in accordance with a required performance of the loop.
- a primary type loop can be formed by simply replacing the loop filter 2 with multiplication of DC gain K.
- An output signal from the loop filter 2 is supplied to an integrator 13 and is integrated therein.
- the integrator 4 can be easily realized by an adder 30 and a delay circuit 31 for delaying an input sampled value by one sampling period.
- Outputs from the integrator 13 are respectively supplied as addresses to ROMs 14 and 15, which store data of cosine and sine waves in a digital form in advance.
- Output digital signals from the ROMs 14 and 15 are respectively converted into analog signals by D/A converters 16 and 17.
- a variable frequency signal generator 18 generates signals S f having various frequencies in accordance with external frequency control signals S c .
- the output signal S f from the variable frequency signal generator 18 is supplied to a multiplier 20 and a ⁇ /2 phase shifter 19.
- the multiplier 20 multiplies the output signal from the D/A converter 16 by the output signal S f from the variable frequency signal generator 18, and supplies the multiplication result to one input terminal of a synthesizer 22.
- the ⁇ /2 phase shifter 19 shifts the output signal S f from the variable frequency signal generator 18 by ⁇ /2 radians, and supplies it to a multiplier 21.
- the multiplier 21 multiplies the output signal from the D/A converter 17 by the output signal from the ⁇ /2 phase shifter, and supplies the multiplication result to the other input terminal of the synthesizer 22.
- the synthesizer 22 adds the input signals to its respective input terminals together, and outputs the addition result as the reference clock signal CLK upon SSB (signal sideband) modulation.
- V c (t) cos( ⁇ t + ⁇ o ) (1)
- V s (t) sin( ⁇ t + ⁇ o ) (2)
- ⁇ ⁇ and ⁇ o are a frequency error and an initial phase error between the reference clock signal CLK and the output signal from the variable frequency signal generator 18, respectively, in a normal state of the loop.
- variable frequency signal generator 18 cos ⁇ c t (3)
- v s (t) sin ⁇ c t (4)
- the SSB-modulated output obtained by the synthesizer 22 can be given by: and hence the reference clock signal CLK is obtained.
- a ring counter is constituted by two D flip-flops 32 and 33 so that a clock signal is frequency-divided at a ratio of 1/4 to obtain a clock signal Q1 and a clock signal Q2 delayed by ⁇ /2 radians, as shown in Fig. 6.
- Fig. 7 is a circuit diagram showing the multipliers 20 and 21 according to the embodiment.
- the multiplier 20 comprises a differential converter 24 for differentially converting an output from the D/A converter 16, and switches 26 and 27 respectively connected to the inverted and noninverted signal output terminals of the differential converter 24.
- the switches 26 and 27 are respectively ON/OFF-controlled by the output signals Q1 and Q 1 from the variable frequency signal generator 18.
- the multiplier 21 comprises a differential converter 25 for differentially converting an output from the D/A converter 17, and switches 28 and 29 respectively connected to the inverted and noninverted signal output terminals of the differential converter 25.
- the switches 28 and 29 are respectively ON/OFF-controlled by the output signals Q2 and Q 2 from the ⁇ /2 phase shifter 19.
- the outputs from the D/A converters 16 and 17 are respectively converted by the differential converters 24 and 25 into in-phase and opposite-phase signals.
- the switch 26 or 28 is closed during an interval of an amplitude A in the waveform shown in Fig. 8 to output the in-phase signal.
- the switch 27 or 29 is opened to inhibit the opposite-phase signal.
- the switch 26 or 28 is opened during an interval of an amplitude -A to inhibit the in-phase signal.
- the switch 27 or 29 is closed to output the opposite-phase signal.
- a clock phase error signal detected by the clock phase error detector is filtered by the loop filter, and is then integrated.
- the frequency and phase of an output signal from the variable frequency signal generator are controlled by the ROM, the D/A converter, the multiplier, the ⁇ /2 phase shifter, and the synthesizer using the integrated output, thereby outputting a reference clock signal.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Claims (2)
- Veränderliche Bitraten-Taktwiedergewinnungsschaltung mit:- einer Taktphasenfehlerdetektoreinrichtung (1) zum Empfang eines demodulierten Signals (SDEM) eines digital modulierten Signals und eines Referenztaktsignals (CLK), zur Detektion eines Phasenfehlers zwischen den Eingangssignalen und zur Ausgabe eines Taktphasenfehlersignals;- einem Schleifenfilter (2) zum Entfernen einer Hochfrequenzkomponente aus dem Taktphasenfehlersignal; und- Oszillatoreinrichtungen (13-22) zur Erzeugung des Referenztaktsignals, die auf eine Ausgabe des Schleifenfilters ansprechen;dadurch gekennzeichnet, daß diese Oszillatoreinrichtungen umfassen:- einen Integrator (13) zur Integration der Ausgabe des Schleifenfilters;- erste und zweite ROMs (14, 15) zur Vorausspeicherung von Kosinus- und Sinuswellendaten in digitaler Form, wobei auf die ersten und zweiten ROMs durch eine Ausgabe des Integrators (13) zugegriffen wird;- erste und zweite D/A-Wandler (16, 17) zur jeweiligen Konvertierung von digitalen Ausgangssignalen aus dem ersten und zweiten ROM in analoge Signale;- einen veränderlichen Frequenzsignalgenerator (18), der durch ein Frequenzsteuersignal gesteuert wird, zur Erzeugung von Signalen mit verschiedenen Frequenzen;- einen Phasenschieber (19) zur Phasenverschiebung jedes Signals des veränderbaren Frequenzsignalgenerators (18) um π/2 Radiant;- einen ersten Multiplizierer (20) zur Modulation jeder Ausgabe des ersten D/A-Wandlers (16);- einen zweiten Multiplizierer (21) zur Modulation einer Ausgabe des Phasenschiebers (19) unter Verwendung eines Ausgabesignals des zweiten D/A-Wandlers (17); und- einen Synthesizer (22) zur Addition der Ausgaben der ersten und zweiten Multiplizierer (20, 21) und zur Ausgabe des Referenztaktsignals.
- Ein Schaltkreis gemäß Anspruch 1, in dem jeder der genannnten ersten und zweiten Multiplizierer (20, 21) einen differenziellen Wandler (24, 25) und einen Schalter (26, 27; 28, 29), der durch Rechteckausgangssignale aus dem veränderbaren Frequenzsignalgenerator (18) ein/ausgeschaltet wird, und einen π/2 Phasenschieber (19) aufweist.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP224148/87 | 1987-09-09 | ||
JP62224148A JPH0620197B2 (ja) | 1987-09-09 | 1987-09-09 | 速度可変型クロック再生回路 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0306941A2 EP0306941A2 (de) | 1989-03-15 |
EP0306941A3 EP0306941A3 (en) | 1989-11-15 |
EP0306941B1 true EP0306941B1 (de) | 1993-06-02 |
Family
ID=16809296
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP88114680A Expired - Lifetime EP0306941B1 (de) | 1987-09-09 | 1988-09-08 | Veränderliche Bitraten-Taktwiedergewinnungsschaltung |
Country Status (6)
Country | Link |
---|---|
US (1) | US4891598A (de) |
EP (1) | EP0306941B1 (de) |
JP (1) | JPH0620197B2 (de) |
AU (1) | AU601132B2 (de) |
CA (1) | CA1289200C (de) |
DE (1) | DE3881457T2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1990011662A1 (fr) * | 1989-03-29 | 1990-10-04 | Sharp Kabushiki Kaisha | Generateur de signaux d'horloge |
GB9019491D0 (en) * | 1990-09-06 | 1990-10-24 | Ncr Co | Clock recovery for a wireless local area network station |
US5237290A (en) * | 1992-05-08 | 1993-08-17 | At&T Bell Laboratories | Method and apparatus for clock recovery |
JPH06307025A (ja) * | 1993-04-23 | 1994-11-01 | Masayuki Tokida | 瓦棟補強材並びに瓦棟の形成方法 |
JPH0682234U (ja) * | 1993-05-06 | 1994-11-25 | 常田 正行 | 瓦棟面戸 |
JPH07193564A (ja) * | 1993-12-25 | 1995-07-28 | Nec Corp | クロック再生装置および再生方法 |
US6285722B1 (en) | 1997-12-05 | 2001-09-04 | Telcordia Technologies, Inc. | Method and apparatus for variable bit rate clock recovery |
US6807228B2 (en) | 1998-11-13 | 2004-10-19 | Broadcom Corporation | Dynamic regulation of power consumption of a high-speed communication system |
US6363129B1 (en) * | 1998-11-09 | 2002-03-26 | Broadcom Corporation | Timing recovery system for a multi-pair gigabit transceiver |
US6928106B1 (en) * | 1998-08-28 | 2005-08-09 | Broadcom Corporation | Phy control module for a multi-pair gigabit transceiver |
ATE368344T1 (de) * | 1999-04-22 | 2007-08-15 | Broadcom Corp | Gigabit-ethernt mit zeitverschiebungen zwischen verdrillten leitungspaaren |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4270093A (en) * | 1979-06-27 | 1981-05-26 | Gte Automatic Electric Laboratories Incorporated | Apparatus for forcing a phase-lock oscillator to a predetermined frequency when unlocked |
US4274067A (en) * | 1979-09-27 | 1981-06-16 | Communications Satellite Corporation | Universal clock recovery network for QPSK modems |
US4280099A (en) * | 1979-11-09 | 1981-07-21 | Sperry Corporation | Digital timing recovery system |
WO1984000089A1 (en) * | 1982-06-14 | 1984-01-05 | Western Electric Co | Timing recovery circuit |
FR2548488B1 (fr) * | 1983-06-28 | 1985-10-18 | Thomson Csf | Dispositif de generation d'un signal module en frequence |
US4694196A (en) * | 1984-12-07 | 1987-09-15 | American Telephone And Telegraph Company And At&T Information Systems | Clock recovery circuit |
US4631484A (en) * | 1984-12-21 | 1986-12-23 | Allied Corporation | Multimode pulse generator |
US4707842A (en) * | 1985-04-03 | 1987-11-17 | Siemens Aktiengesellschaft | Apparatus and method for acquiring data and clock pulses from asynchronous data signals |
-
1987
- 1987-09-09 JP JP62224148A patent/JPH0620197B2/ja not_active Expired - Lifetime
-
1988
- 1988-09-08 AU AU21996/88A patent/AU601132B2/en not_active Ceased
- 1988-09-08 DE DE8888114680T patent/DE3881457T2/de not_active Expired - Fee Related
- 1988-09-08 EP EP88114680A patent/EP0306941B1/de not_active Expired - Lifetime
- 1988-09-08 US US07/241,669 patent/US4891598A/en not_active Expired - Lifetime
- 1988-09-08 CA CA000576735A patent/CA1289200C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4891598A (en) | 1990-01-02 |
AU601132B2 (en) | 1990-08-30 |
EP0306941A2 (de) | 1989-03-15 |
DE3881457D1 (de) | 1993-07-08 |
JPS6468149A (en) | 1989-03-14 |
DE3881457T2 (de) | 1993-09-09 |
JPH0620197B2 (ja) | 1994-03-16 |
AU2199688A (en) | 1989-03-23 |
CA1289200C (en) | 1991-09-17 |
EP0306941A3 (en) | 1989-11-15 |
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