EP0300632A2 - In Plastikmaterial eingekapselte paketförmige integrierte Schaltung mit elektrostatischer Abschirmung - Google Patents

In Plastikmaterial eingekapselte paketförmige integrierte Schaltung mit elektrostatischer Abschirmung Download PDF

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Publication number
EP0300632A2
EP0300632A2 EP88306065A EP88306065A EP0300632A2 EP 0300632 A2 EP0300632 A2 EP 0300632A2 EP 88306065 A EP88306065 A EP 88306065A EP 88306065 A EP88306065 A EP 88306065A EP 0300632 A2 EP0300632 A2 EP 0300632A2
Authority
EP
European Patent Office
Prior art keywords
base
shield
leads
chip
fingers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88306065A
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English (en)
French (fr)
Other versions
EP0300632A3 (de
Inventor
George Erdos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gennum Corp
Original Assignee
Gennum Corp
Linear Technology LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gennum Corp, Linear Technology LLC filed Critical Gennum Corp
Publication of EP0300632A2 publication Critical patent/EP0300632A2/de
Publication of EP0300632A3 publication Critical patent/EP0300632A3/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01014—Silicon [Si]
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    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01076—Osmium [Os]
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    • H01L2924/01082—Lead [Pb]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • This invention relates to a plastic encapsula­ted integrated circuit package having an electrostatic shield fabricated therein.
  • DIP dual-in-line plastic package
  • RF radio frequency
  • ceramic packages are commonly used.
  • the ceramic packages consist of a ceramic base into which the integrated cir­cuit chip can be fitted, with slots for the leads to extend therefrom, and with a metal lid which can be assembled over the chip.
  • crosstalk isolation of 80 dB or better can be achieved, but the cost of these packages is typically ten times the cost of a DIP package.
  • the present invention provides an integrated circuit package comprising:
  • a conventional lead frame for an integrated circuit is indicated at 10.
  • the lead frame 10 includes side bars 12 connected by a cross-member 14 to a base or "paddle" 16.
  • An integrated circuit chip indicated in dotted lines at 18, is conventionally adher­ed to the paddle 16 by a suitable adhesive.
  • the lead frame 10 is typically fabricated from a material which has the same thermal coefficient of expansion as the chip 18.
  • the lead frame 10 is made from an alloy of nickel, silicon, manganese and iron as is well known in the industry.
  • the lead frame 10 includes a pair of further cross-members 20 on which are mounted a plurality of leads 22.
  • Each lead 22 has a finger 24 which extends close to but is spaced slightly from the paddle 16.
  • the leads 22 are located in the same plane as that of the outer portions of cross-member 14. As shown in Figs. 2 and 3, this plane is located above that of the paddle 16.
  • the plane of the paddle 16 is depressed below that of the leads 22 and outer portions of cross-member 14 by two angled portions or bends 26 in the cross-member 14. The bends 26 are located closely adjacent the paddle 16.
  • the leads 22 are connected to leads 22a, 22b which extend toward other paddles (not shown) in the lead frame 10. After the assembly and encapsulation to be described, the leads 22a, 22b are cut away at the weakened points 28 as the complete integrated circuit packages are removed from the lead frame.
  • the cross-members 20 which support the leads 22 also serve as dam bars during the plastic encapsulation process, as will be described.
  • the electrostatic shield 30 of the invention is typically made of the same metal alloy as the lead frame 10 and is secured to the bottom of the paddle 16.
  • the electrostatic shield 30 may be secured to the paddle 16 either by spot welding, or by an electrically conductive glue.
  • the electrostatic shield 30 is normally of the same shape as the paddle 16 (rectangular) and extends outward­ly laterally beyond the paddle 16 to underlie a portion of each of the fingers 24 of the leads 22. However, the shield 30 does not extend as far outwardly as the dam bars 20 or the side bars 12.
  • the integrated circuit chip 18 In assembly, the integrated circuit chip 18, after being mounted on the paddle 16, is connected to the fingers 24 by connecting wires indicated at 32 in Fig. 3.
  • the connecting wires 32 are typically bonded at points 34.
  • the combination of the shield 30, paddle 16, integrated circuit chip 18, connecting wires 32 and fingers 24 of the leads 22 are plastic encapsula­ted by a pair of mold halves (not shown) which are closed over the top and bottom of the lead frame 10.
  • the mold halves close over the side bars 12 and the dam bars 20.
  • Plastic is then injected into the mold.
  • the dam bars 20 prevent plastic from flowing laterally outwardly beyond the dam bars.
  • the side bars 12 perform the same function at the sides of the lead frame.
  • a thermosetting single component plastic epoxy is used, which cures after it has been heated, or alternatively a thermoplastic may be used.
  • the total thickness of the resultant package is about .135 inches, although this thickness can vary between about .110 and .160 inches.
  • the above dimensions assume a lead frame thick­ ness of about .010 inches, an electrostatic shield thick­ness of about .010 inches, and a dimension D (the differ­ence in level between the bottom of the leads 22 and the top of the paddle 16) of about .015 inches.
  • the electrostatic shield 30 projects as far as possible outwardly beyond the innermost por­tions of the lead fingers 24, but terminates inwardly of the dam bars 20 and side bars 12 sufficiently so as not to split the package in half. It is found sufficient if the shield 30 projects laterally to within .030 inches of the dam bars 20.
  • the completed device is removed from the lead frame by cutting the leads 22 at the weakened areas 28 and by cutting the cross-member 14 at points 36.
  • the dam bars 20 are cut away (i.e. the por­tions between the leads 22 and between the leads and side bars 12 are removed) to remove unwanted connections between the leads.
  • the ground pin of the chip 18 is indicated at 38 in Fig. 1.
  • a connection wire 40 is bonded between pin 38 and one of the lead fingers, namely finger 24A.
  • Finger 24A is integrally connected by a con­ductive strip 42 to the cross-member 14 near one of the side bars 12. This arrangement avoids the need for an operation to make an extra connection, since connecting wire 40 which connects lead finger 24A to ground pin 38 must normally be installed whether or not a shield 30 is used.
  • the package described is inexpensive and yet provides a consistent improvement of 3 to 4 dB over a standard dual-in-line plastic package. The difference is sufficient to permit the new package to be used in many video switch and similar RF applications without the need for a costly ceramic package. It is found that the electrostatic shield 30 of the invention, when it underlies a short portion of the leads 22, shorts out or attenuates the RF field which would otherwise exist between adjacent leads 22 and thereby reduces the level of crosstalk.
  • the upper surface of the shield 30 be physically located at a lower level than the lower surface of the fingers 24, so that the shield 30 will not contact the leads themselves.
  • the shield 30 terminates later­ ally sufficiently short of the dam bars 20, it is found that the shield 30 does not interfere with the plastic encapsulation process, and that the plastic will flow adequately in order to encapsulate the chip and the leads fully.
  • the spaces into which the plastic must flow are now made narrower than in the past, it is necessary to ensure during the encapsulation process that the plastic is sufficiently free flowing (i.e. suffi­ciently low viscosity) to fill all of the spaces between the mold halves.
  • the paddle 16′ can be formed in the same plane as cross-member 14′, and the shield 30′ can be downwardly dished.
  • the centre part 50 of the shield 30′ is conductively fixed to the bottom of the paddle 16′.
  • a downwardly extending rim 52 encircles the centre part 50, and a flange 54 projects outwardly from rim 52.
  • the flange 54 underlies the wires 32 and fingers 24 to attenuate any field therebetween.
  • the rim and flange 52,54 can extend on two, three or four sides depending on where there are leads to be underlaid.

Landscapes

  • Power Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
EP19880306065 1987-07-20 1988-07-04 In Plastikmaterial eingekapselte paketförmige integrierte Schaltung mit elektrostatischer Abschirmung Withdrawn EP0300632A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA542524 1987-07-20
CA000542524A CA1278618C (en) 1987-07-20 1987-07-20 Plastic encapsulated integrated circuit package with electrostatic shield

Publications (2)

Publication Number Publication Date
EP0300632A2 true EP0300632A2 (de) 1989-01-25
EP0300632A3 EP0300632A3 (de) 1990-12-12

Family

ID=4136108

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19880306065 Withdrawn EP0300632A3 (de) 1987-07-20 1988-07-04 In Plastikmaterial eingekapselte paketförmige integrierte Schaltung mit elektrostatischer Abschirmung

Country Status (5)

Country Link
US (1) US4953007A (de)
EP (1) EP0300632A3 (de)
JP (1) JPH01120041A (de)
AU (1) AU1913888A (de)
CA (1) CA1278618C (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103885520A (zh) * 2008-11-25 2014-06-25 凌力尔特有限公司 一种具有静电屏蔽的温度补偿金属电阻器

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254871A (en) * 1988-11-08 1993-10-19 Bull, S.A. Very large scale integrated circuit package, integrated circuit carrier and resultant interconnection board
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads
US5233220A (en) * 1989-06-30 1993-08-03 Texas Instruments Incorporated Balanced capacitance lead frame for integrated circuits and integrated circuit device with separate conductive layer
US5854094A (en) * 1992-07-28 1998-12-29 Shinko Electric Industries Co., Ltd. Process for manufacturing metal plane support for multi-layer lead frames
JPH0653394A (ja) * 1992-07-28 1994-02-25 Shinko Electric Ind Co Ltd 多層リードフレーム用プレーン支持体
US5424896A (en) * 1993-08-12 1995-06-13 Lsi Logic Corporation Semiconductor package electrostatic discharge damage protection
US5661336A (en) * 1994-05-03 1997-08-26 Phelps, Jr.; Douglas Wallace Tape application platform and processes therefor
US5548160A (en) * 1994-11-14 1996-08-20 Micron Technology, Inc. Method and structure for attaching a semiconductor die to a lead frame
JP2806328B2 (ja) * 1995-10-31 1998-09-30 日本電気株式会社 樹脂封止型半導体装置およびその製造方法
US5781682A (en) * 1996-02-01 1998-07-14 International Business Machines Corporation Low-cost packaging for parallel optical computer link
US6096165A (en) * 1997-08-07 2000-08-01 Micron Technology, Inc. Method and apparatus for application of adhesive tape to semiconductor devices
US6429515B1 (en) 2000-05-05 2002-08-06 Amkor Technology, Inc. Long wire IC package
US6326235B1 (en) * 2000-05-05 2001-12-04 Amkor Technology, Inc. Long wire IC package fabrication method
JP2010258159A (ja) * 2009-04-23 2010-11-11 Renesas Electronics Corp 半導体装置
TWI641106B (zh) * 2016-12-15 2018-11-11 南茂科技股份有限公司 晶片封裝基板與晶片封裝結構

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0037760A1 (de) * 1980-04-04 1981-10-14 Societe Flonic Karte mit Datenspeicher und eine integrierte Schaltung sowie Massnahmen zum Schutz gegen elektrostatische Ladungen
DE3410196A1 (de) * 1984-03-20 1985-09-26 Siemens AG, 1000 Berlin und 8000 München Leiterband fuer die montage von integrierten schaltkreisen
DE3433779A1 (de) * 1984-09-14 1986-03-27 Robert Bosch Gmbh, 7000 Stuttgart Schutzschicht fuer halbleiterschaltungen

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4867658U (de) * 1971-12-04 1973-08-28
JPS5571498A (en) * 1978-11-24 1980-05-29 Japan Maize Prod Production of finely divided sugar
JPS6225907Y2 (de) * 1980-06-06 1987-07-02
JPS6020946U (ja) * 1983-07-21 1985-02-13 トヨタ自動車株式会社 自動車用小物入れ
JPS6068638A (ja) * 1983-09-26 1985-04-19 Canon Inc チップ−オン−ボ−ド実装基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0037760A1 (de) * 1980-04-04 1981-10-14 Societe Flonic Karte mit Datenspeicher und eine integrierte Schaltung sowie Massnahmen zum Schutz gegen elektrostatische Ladungen
DE3410196A1 (de) * 1984-03-20 1985-09-26 Siemens AG, 1000 Berlin und 8000 München Leiterband fuer die montage von integrierten schaltkreisen
DE3433779A1 (de) * 1984-09-14 1986-03-27 Robert Bosch Gmbh, 7000 Stuttgart Schutzschicht fuer halbleiterschaltungen

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103885520A (zh) * 2008-11-25 2014-06-25 凌力尔特有限公司 一种具有静电屏蔽的温度补偿金属电阻器
CN103885520B (zh) * 2008-11-25 2016-08-17 凌力尔特有限公司 一种具有静电屏蔽的温度补偿金属电阻器

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CA1278618C (en) 1991-01-02
JPH01120041A (ja) 1989-05-12
US4953007A (en) 1990-08-28
AU1913888A (en) 1989-01-27
EP0300632A3 (de) 1990-12-12
JPH0563101B2 (de) 1993-09-09

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