EP0295001B1 - Anordnung für CMOS-integrierten Schaltungsaufbau eines logischen Baumes mit Eingangsbelastbarkeit - Google Patents

Anordnung für CMOS-integrierten Schaltungsaufbau eines logischen Baumes mit Eingangsbelastbarkeit Download PDF

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Publication number
EP0295001B1
EP0295001B1 EP88305018A EP88305018A EP0295001B1 EP 0295001 B1 EP0295001 B1 EP 0295001B1 EP 88305018 A EP88305018 A EP 88305018A EP 88305018 A EP88305018 A EP 88305018A EP 0295001 B1 EP0295001 B1 EP 0295001B1
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EP
European Patent Office
Prior art keywords
devices
input
column
terminals
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP88305018A
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English (en)
French (fr)
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EP0295001A3 (en
EP0295001A2 (de
Inventor
Frank E. Barber
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AT&T Corp
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American Telephone and Telegraph Co Inc
AT&T Corp
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Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of EP0295001A2 publication Critical patent/EP0295001A2/de
Publication of EP0295001A3 publication Critical patent/EP0295001A3/en
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Publication of EP0295001B1 publication Critical patent/EP0295001B1/de
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

Definitions

  • This invention relates to integrated circuits and more particularly to digital logic circuit layouts for implementing fan-in logic trees, such as can be used in a crossbar (crosspoint) switch in a telecommunication system for voice, video or data transmission.
  • interconnecting wiring delays in such logic trees caused by differences in relatively long lengths of the interconnecting wiring, produce undesirable signal skews (signal-delay differences) in the outputs of the logic trees. Therefore, it would be desirable to have an integrated circuit layout arrangement for such trees which reduces this skew.
  • the inventive layout for such a logic tree -- composed of a plurality N of logic devices, each of such devices having a first and a second input terminal and an output terminal is characterized in that the plurality comprises seven of such devices sequentially arranged in a column (FIG.
  • the first and second input terminals of the 1st, 3rd, 5th, and 7th devices are separately connected to receive signals emanating from sources that are external to all of the N devices;
  • the output terminals of the 1st and the 3rd device are separately connected to the first and second input terminals, respectively, of the 2nd device;
  • the output terminals of the 5th and 7th devices are separately connected to the first and second input terminals, respectively, of the 6th device;
  • the output terminals of the 2nd and 6th devices are connected to the first and second input terminals, respectively, of the 4th device, and the first and second input terminals of the 1st, 3rd, 4th, 5th, and 7th devices, as well as the output terminals of the 2nd and 6th devices, are all located essentially on a first side of the column; and the first and second input terminals of the 2nd and 6th devices, as well as the output terminals of the 1st, 3rd, 4th, 5th, and 7
  • a fan-in multiplexer logic tree 300 includes a first multiplexer stage having a total of eight NAND gates 100, 101, 102,... 107 in pairs which fans-in to a second multiplexer stage comprising a total of four NAND gates 110, 111, 112, 113, each cascaded in series with an INVERTER gate 200, 201, 202, 203, respectively.
  • these four INVERTER gates in pairs fan-in to a third multiplexer stage comprising a total of two NAND gates 120 and 121, each cascaded in series with an INVERTER gate 210 and 211, respectively.
  • these latter two INVERTER gates in pairs fan-in to a fourth multiplexer stage comprising multiplexer 130 cascaded in series with INVERTER gates 220 and 230 to node N1.
  • the node N1 is connected to a pair of parallel paths to first path containing cascaded INVERTER gates 241, 242, 243, 244, terminating in a first output pad 400, and the second path containing cascaded INVERTER gates 251, 252, 253 terminating in a second output pad 400' which thus supplies the complementary information signal to that developed at the first output pad 400, there being one more inverter in first such path than in the second.
  • each of the NAND gates is symmetrized and each of the INVERTER gates likewise is symmetrized, except that the INVERTER gates in the first and second paths from node N1 to the output pads 400 and 400', respectively, generally are not symmetrized, since none of these INVERTER gates is immediately preceded by a NAND gate that would require compensation by symmetrization.
  • the transistors in the INVERTER gates in the first and second paths are selected to have channel widths such that, in response to an upward -going signal edge at the node N1, the sum of the resulting pull- up delays in the first and second paths are made to be equal, and at the same time the sum of the resulting pull- down delays in these paths are also made to be equal--i.e., the sum of the resulting pull- up delays of INVERTER gates 242 plus 244 is equal to the resulting pull- up delay of the INVERTER gate 252, and moreover at the same time in response to this upward -going signal edge at the node N1 the sum of the resulting pull- down delays of the INVERTER gates 241 plus 243 is equal to the sum of the resulting pull- down delays of the INVERTER gates 251 plus 253.
  • the sum of the resulting pull- up delays of the INVERTER gates 241 plus 243 is made equal to the sum of the resulting pull- up delays of INVERTER gates 251 plus 253, and the sum of the pull- down delays of INVERTER gates 242 plus 244 is made equal to the sum of the resulting pull-down delay of the INVERTER gate 252.
  • the NMOS portion pulls- down the output of the gate in response to an upward -going input
  • the PMOS portion pulls up the output of the gate in response to a downward -going input.
  • the NAND gates 110, 111, 112, 113 in the second stage of the logic tree
  • the INVERTER gates 200, 201, 202, and 203 in such second stage
  • the NAND gates 120, 121 and the INVERTER gates 210 and 211 in the third stage be symmetrized
  • the NAND gate 130 and the INVERTER gate 220 in the fourth stage be symmetrized. In this way, skews will not accumulate over a multiplicity of stages.
  • the NAND gates 100, 101, 102, ... 107 in the first stage
  • a total of eight input pulsed information signals A0, A1, A2, ... A7 are controlled by a total of eight control signals C0, C1, C2, ... C7, respectively.
  • control signals C0, C1, C2, ... C7 are enabled, i.e., enables the corresponding one of the information signals to propagate through that one of NAND gates. For example, if control signal C2 is high and the remaining control signals are low, then A2 and only A2 propagates (as A2 )to the next stage of multiplexer, i.e., propagates to the NAND gate 111 in the second stage of the tree.
  • the output of the NAND gate 103 will be high and hence will enable the NAND gate 111 to pass along the signal A2 to the INVERTER gate 201, and then to pass along the resulting signal A2 to the NAND gate 120 in the third stage, and so forth through the remaining fourth stage (or still further stages, if any).
  • the input information signal A2 and no other can propagate all the way to the output pads 400 and 400' as output information signals A2 and A2 , respectively, if and when C2 is high.
  • any one of the other input information signals can propagate to and arrive as an output information signal and its complement at the output pads 400 and 400', respectively, if and when that other signal's corresponding control signal is high.
  • the previously described fan-in multiplexer logic tree 300 is folded into a compact folded layout scheme in the XY plane (major surface of semiconductor chip).
  • the layout consists essentially of first and second interconnected columns 301 and 302, respectively, in order to minimize signal skews caused by interconnection wiring delays and at the same time economize on semiconductor chip area.
  • the first column 301 contains the first stage and only the first stage of the multiplexer logic tree, consisting essentially of the NAND gates 100, 101, 102, ... 107; whereas the second column 302 contains all the remaining stages of the logic tree.
  • each stage (except the first) consists essentially of half as many NAND gates as the stage immediately preceding it plus an INVERTER gate in cascade with each such NAND gate, and there are a total of (n + 1) stages.
  • the first column 301 has a width (in the X direction) of only one logic gate, i.e., is one NAND gate wide; whereas the second column is at two logic gates wide, i.e., a NAND gate connected in cascade with a INVERTER gate.
  • all the NAND gates 100, 101,... 107 in column 301 are mutually identical, and in column 302 all the NAND plus INVERTER gate cascades are mutually identical.
  • the electrical path length, including both wiring and gate delays, from each input A0, A1, ... A7 to the node N1 is the same for all.
  • the corresponding information signals arrive at node N1 in a correlated manner.
  • FIG. 3 shows an 8 input x 8 output crossbar switching arrangement 500 comprising eight input signal pads I0, I1, I2, ... I7, for receiving eight input information signals; eight input buffers IB0, IB1, IB2, ... IB7 for developing proper signal levels for the eight input information signals A0, A1,... A7; eight multiplexer logic trees 300, 310, 320,...370, each constructed in accordance with the compact folded layout 300 consisting of first and second columns 301 and 302 shown in FIG. 2 together with first and second signal paths (not shown in detail) for developing eight output information signals and their complements at output pads 400, 400', 401, 401',...407, 407'.
  • x 8 64 control signals.
  • a first set of eight of them, designated by ⁇ C ⁇ 0 is delivered to the first stage of logic tree 300, just as C0, C1,...C7, as previously described--i.e., ⁇ C ⁇ 0 is the set formed by C0, C1,...C7.
  • a second set of eight of them, designated by ⁇ C ⁇ 1, are similarly delivered to the first stage of a second logic tree 310; and so forth, until finally an eighth set of eight control signals ⁇ C ⁇ 7 are similarly delivered to the first stage of an eight logic tree 370.
  • each of the input information signals A0, A1,...A7 is connected as an input to the first stages of all the trees 300, 310,...370.
  • a 64 input x 17 output crossbar switch in CMOS technology has been fabricated in a single silicon chip with a minimum feature size of about 1.25 microns and has been successfully tested and operated at data rates as high as 280 megabits per second.
  • FIG.4 A compact folded layout for such a 64 input crossbar switching arrangement is shown in FIG.4 wherein each box in column 601 represents a single NAND gate, and each box in columns 602 and 603 represents a NAND gate plus an INVERTER gate connected in cascade therewith, the structure of each such column for positive values of Y being a mirror image of the structure of such column for negative values of Y.
  • the arrangement 500 enables any input signal to be delivered simultaneously (i.e., to be broadcast) to as many output pads as desired, depending upon the control signals. Note further, that at any instant of time at most one of the first set ⁇ C ⁇ 0 of control signals should be high, plus (if desired) at most one of the second set ⁇ C ⁇ 1, etc., lest more than one of the input signals be delivered to the same output pad at the same time and thereby cause undesired confusion.
  • each of the input pads and each of the output pads in the arrangement 500 ultimately is connected to a subscriber (not shown) in a telecommunication system, either through further electronic means or through electro-optic and optical means, or both, as known in the art.
  • CMOS NAND gates instead of symmetrized CMOS NAND gates, symmetrized CMOS NOR gates can be used, made from conventional CMOS NOR gates by adding PFETs in the PMOS portion.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)

Claims (6)

  1. Logisches Schaltungslayout für einen logischen eingangseitigen Baum (300), der aus einer Vielzahl N von logischen Elementen zusammengesetzt ist, von denen jedes solche Element einen ersten und einen zweiten Eingangsanschluß und einen Ausgangsanschluß hat,
    dadurch gekennzeichnet,
    daß die Vielzahl erste bis siebte solche Elemente (110, 120, 111, 130, 112, 121, 113) enthält, die sequentiell in einer Reihe (302) angeordnet sind, wobei die Reihe in Folge die ersten bis siebten Elemente enthält, die ersten und zweiten Eingangsanschlüsse der ersten, dritten, fünften und siebten Elemente (110 - 113) separat angeschlossen sind, um Signale zu empfangen, die von Quellen ausgehen, die extern von allen N Elementen sind,
    die Ausgangsanschlüsse der ersten und dritten Elemente (110, 111) jeweils separat an die ersten und zweiten Eingangsanschlüsse des zweiten Elements (120) angeschlossen sind,
    die Ausgangsanschlüsse der fünften und siebten Elemente (112, 113) jeweils separat an die ersten und zweiten Eingangsanschlüsse des sechsten Elements (121) angeschlossen sind,
    die Ausgangsanschlüsse der zweiten und sechsten Elemente (120, 121) jeweils an die ersten und zweiten Eingangsanschlüsse des vierten Elements (130) angeschlossen sind,
    die ersten und zweiten Eingangsanschlüsse der ersten, dritten, vierten, fünften und siebten Elemente (110 - 113) sowie die Ausgangsanschlüsse der zweiten und sechsten Elemente (120, 121) alle im wesentlichen auf einer ersten Seite der Reihe angeordnet sind, und
    die ersten und zweiten Eingangsanschlüsse der zweiten und sechsten Elemente (120, 121) sowie die Ausgangsanschlüsse der ersten, dritten, vierten, fünften und siebten Elemente alle im wesentlichen auf einer zweiten Seite der Reihe, gegenüber der ersten Seite von dieser, angeordnet sind.
  2. Layout nach Anspruch 1,
    dadurch gekennzeichnet,
    daß alle solchen, von den ersten bis zu den siebten, logischen Elemente im wesentlichen wechselseitig identisch in der Struktur sind.
  3. Layout nach Anspruch 2,
    dadurch gekennzeichnet,
    daß jedes der ersten bis siebten Elemente im wesentlichen aus einem NAND-Gatter mit zwei Eingängen und einem Inverter mit einem einzelnen Eingang bestehen, wobei der Ausgangsanschluß des NAND-Gatters mit dem Eingangsanschluß des Inverters verbunden ist.
  4. Layout nach Anspruch 1,
    dadurch gekennzeichnet,
    daß die Vielzahl N weiterhin achte bis fünfzehnte solche Elemente sequenziell in der Reihe angeordnet enthält, wobei die Reihe in Folge die ersten bis fünfzehnten Elemente enthält,
    die ersten und zweiten Eingangsanschlüsse der neunten, elften, dreizehnten und fünfzehnten Elemente separat angeschlossen sind, um Signale zu empfangen, die von Quellen ausgehen, die extern von allen N Elementen sind,
    die Ausgangsanschlüsse und die ersten und zweiten Eingangsanschlüsse der neunten bis fünfzehnten Elemente jeweils untereinander in der gleichen Weise verbunden sind, wie die Ausgangsanschlüsse und die ersten und zweiten Eingangsanschlüsse der ersten bis siebten Elemente untereinander jeweils verbunden sind,
       die Ausgangsanschlüsse der vierten und zwölften Elemente jeweils separat an erste und zweite Eingangsanschlüsse des achten Elements angeschlossen sind,
    die ersten und zweiten Eingangsanschlüsse der neunten, elften, zwölften, dreizehnten und fünfzehnten Elemente sowie die Ausgangsanschlüsse der achten, zehnten und vierzehnten Elemente alle im wesentlichen auf der ersten Seite der Reihe angeordnet sind und
    die ersten und zweiten Eingangsanschlüsse der achten, zehnten und vierzehnten Elemente sowie die Ausgangsanschlüsse der neunten, elften, zwölften, dreizehnten und fünfzehnten Elemente alle im wesentlichen auf der zweiten Seite der Reihe angeordnet sind.
  5. Layout nach Anspruch 4,
    dadurch gekennzeichnet,
    daß alle logischen Elemente in der Reihe wechselweise im wesentlichen identisch sind.
  6. Layout nach Anspruch 5,
    dadurch gekennzeichnet,
    daß jedes der ersten bis fünfzehnten Elemente im wesentlichen aus einem NAND-Gatter mit zwei Eingängen und einem Inverter mit einem Eingang bestehen, wobei der Ausgangsanschluß des NAND-Gatters mit dem Eingangsanschluß des Inverters verbunden ist.
EP88305018A 1987-06-08 1988-06-02 Anordnung für CMOS-integrierten Schaltungsaufbau eines logischen Baumes mit Eingangsbelastbarkeit Expired EP0295001B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58968 1987-06-08
US07/058,968 US4849751A (en) 1987-06-08 1987-06-08 CMOS Integrated circuit digital crossbar switching arrangement

Publications (3)

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EP0295001A2 EP0295001A2 (de) 1988-12-14
EP0295001A3 EP0295001A3 (en) 1989-04-26
EP0295001B1 true EP0295001B1 (de) 1992-12-30

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US (1) US4849751A (de)
EP (1) EP0295001B1 (de)
JP (1) JPH0770985B2 (de)
CA (1) CA1292044C (de)
DE (1) DE3877062T2 (de)
HK (1) HK133493A (de)
SG (1) SG60593G (de)

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Publication number Publication date
DE3877062D1 (de) 1993-02-11
EP0295001A3 (en) 1989-04-26
HK133493A (en) 1993-12-10
EP0295001A2 (de) 1988-12-14
JPH0770985B2 (ja) 1995-07-31
CA1292044C (en) 1991-11-12
US4849751A (en) 1989-07-18
JPS63312666A (ja) 1988-12-21
SG60593G (en) 1993-07-09
DE3877062T2 (de) 1993-04-29

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