Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/10—Packet switching elements characterised by the switching fabric construction
  • H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/40—Network security protocols
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q11/00—Selecting arrangements for multiplex systems
  • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q11/00—Selecting arrangements for multiplex systems
  • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
  • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
  • H04Q11/0478—Provisions for broadband connections
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/10—Packet switching elements characterised by the switching fabric construction
  • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/25—Routing or path finding in a switch fabric

Definitions

• SWITCHING SYSTEM The present invention relates to a switching system for switching digital signals applied to any one of a plurality of input terminals thereof to any one of a plurality of output terminals thereof ⁇ said switching system including common switching means* a plurality of input means each coupling one of said input terminals to said common switching means* and a plurality of output means each coupling said common switching means to one of said output terminals.
• Such a switching system is already known in the art» e.g. from the article “ITT 12 ⁇ a »0 Digital Exchange - Digital Switching Network” by J.M. Cotton et al, published in "Electrical Communication”* Volume 56* No. 2/3 - 1981» pages 148 to 160.
• This known system is only able to switch* with a switching quality allowing real time communica ion* signals (e.g. voice) having a same frequency range and generated by signal sources operating at a fixed bitrate* these signals being supplied to the input terminals of the switching system.
• An object of the present invention is to provide a switching system of the above type and with a similar switching quality but which is able to switch signals such as voice* data and video having different frequency ranges and different bitrates.
• each of said input means includes processor means coupled to routing means also included in said input means* said routing means being coupled between said one of said input terminals and said common switching means and being able to route said packets to said processor means or* through said common switching means* to one of said output terminals according to said routing information contained in the header of the packet.
• each of said input means includes input storage means for storing said signals and having input and output portions* said input portion being coupled to said one of said input terminals and operating at the frequency of the signals supplied to said one of said input terminals* and said output portion being coupled to an input of said routing means and operating at said predetermined clock frequency to supply said stored signals to said common switching means.
• input storage means for storing said signals and having input and output portions* said input portion being coupled to said one of said input terminals and operating at the frequency of the signals supplied to said one of said input terminals* and said output portion being coupled to an input of said routing means and operating at said predetermined clock frequency to supply said stored signals to said common switching means.
• the latter frequency* which is also the operating frequency of the common switching means* may be different from the frequency and bitrate of the incoming signals.
• Still another character s ic feature of the present switching system is that the frequencies of at least two of the signals supplied to distinct terminals out of said plurality of input terminals are different. In this way and because the predetermined clock frequency at which the common switching means operate is independent of the frequencies of the signals supplied at the input terminals * the system operates in a fully asynchronous way.
• said predetermined clock frequency of said common switching means is at least equal to the sum of the values of the frequencies of said signals applied to said plurality of input terminals.
• the present invention also relates to a switching system for switching digital signals * grouped in incoming packets having a header* applied to any one of a plurality of input terminals thereof to any one of a plurality of output terminals thereof* said switching system including common switching means* input means coupling said plurality of input terminals to said common switching means* and output means coupling said common switching means to said plurality of output terminals.
• a switching system is already known in the art.
• a drawback of the known system is that when * due to errors * the header becomes faulty it accordingly adversely affects the transmission quality of the system.
• An object of the present invention is to provide a switching system of the above type but with an improved transmission quality.
• this object is achieved due to the fact that said input means include header correction means to correct faulty ones of headers of said incoming packets. Due to the header being corrected the transmission - . - quality of the system is improved.
• a plurality of such switching systems SW are interconnected to constitute a switching network included in a digital telecommunication exchange to which user stations are coupled via asynchronous time division transmission links.
• the switching network is able to establish virtual communication paths for various types of signals such as voice* data and video transmitted by the user stations.
• the input signals applied to the network inputs via an asynchronous time division transmission link are digital signals grouped in packets having a fixed length and comprising a header and data. Each packet or a portion thereof is transmitted in a timeslot of the asynchronous time division transmission link.
• the output signals appearing at the network outputs are also digital signals grouped in packets. The rate of both the input and output digital signals may be variable but has an upper limit of e.g. 280 Megabits/second.
• the above input digital signals are accompanied by a clock signal having a frequency corresponding to the input signal rate and which is necessary to synchronize the tranmission of these signals to the asynchronous time division transmission link.
• This clock signal may be supplied either separately on a different link or is preferably included in the input si gnals .
• the above switching system SW has 8 input terminals RxO to Rx7 and 8 output terminals TxO to Tx7 and further includes a common switching bus SB to which each of the input terminals RxO to Rx7 is coupled via distinct input means or receive circuits* and which is coupled to each of the output terminals TxO to Tx7 via distinct output means or transmit circuits.
• a combination of a receive circuit with a corresponding transmit circuit in a same switching system is called a switch port. Since the 8 receive circuits and the 8 transmit circuits of the switching system SW are respectively identical* only one of each* i .e. only one switch port comprising the receive circuit RC to which the input terminal RxO is connected and the transmit circuit TC connected to the output terminal TxO* is represented in detail.
• the receive circuit RC includes between the input terminal RxO and the switching bus SB the cascade connection of a synchronization circuit SC» an input storage circuit IQ, a header correction circuit HC and a routing circuit RT.
• RC also includes a processor or switch port controller SPC controlling SC and possibly RT.
• An output of RT is connected to SPC and the latter is also b i di rect i onally connected to HC.
• the input storage circuit IQ comprises an input portion controlled via a control terminal II by the synchronization circuit SC* and an output portion controlled via a control terminal 10 by a timing circuit TM coupled to and controlling the switching bus SB.
• the transmit circuit TC includes an identification circuit IC > an output storage circuit OQ and an output clock 0C.
• the switching bus SB is connected to the dent fication circuit IC which is controlled by the timing circuit TM.
• the output storage circuit 0Q comprises an input portion to which the switching bus SB is connected and which is controlled by the identifica on circuit IC via a control terminal 01* and an output portion connected to the output terminal TxO and which is controlled by the output clock OC via a control terminal 00.
• the timing circuit TM is adapted to generate synchronous Time Division Multiplex (TDM) frames comprising 8 timeslots or channels on the switching bus SB.
• TDM Time Division Multiplex
• Each of these timeslots is allocated to one receive circuit and the sampling frequency of the switching bus SB must at least be equal to the sum of the frequencies of the signals at the input terminals.
• this frequency is generally equal to the product of the 8 receive circuits with the above mentioned maximum allowed input rate of the signals at the input terminals RxO to Rx7» i.e. 280 Megabits/second* the sampling frequency of the switching bus SB is then equal to 2*240 Megab ts/second.
• the maximum possible delay for a packet present in the receive circuit RC to be loaded on the switching bus SB is mainly equal to the time spent in waiting until the timeslot corresponding to this particular receive circuit RC appears on the switching bus SB.
• Each of the above input/output terminals of the switching system SW is coupled by an asynchronous time division transmission link to an upstream/downstream located device which may either be another similar switching system or a user station.
• the upstream located device is able to feed digital signals to the input terminals RxO to Rx7 of the switching system SW under the form of packets containing a header and data.
• These packets have* e.g.* a fixed length of 16 bytes two of which being used as header and may be : - control packets which are transmitted to establish and/or to update a virtual communication path in the switching system SW and contain information about this path; - synchronization packets which are used to synchronize the operations of the upstream located device and the switching system SW. At least one of these packets is transmitted within an allocated predetermined time interval ; - normal communication packets which contain communication data.
• the switching system SW also includes input serial-to-parallel and output parallel-to-serial conversion circuits (not shown) in order to first convert the serial input signals in a parallel form and to then convert the parallel form into output serial signals.
• the operation of the above switching system SW is described hereinafter.
• the synchronization circuit SC includes a clock extraction circuit (not shown) which extracts the clock signal from the input digital signals and applies it to the control terminal II of the input portion of the input storage circuit IQ.
• the digital input signals are then loaded into IQ and when the latter contains the digital signals of a complete packet * e.g. 16 bytes* this packet is fed to the header correction circuit HC under the control of the timing circuit TM which operates via the control terminal 10.
• the header of a packet applied to HC might be modified due to errors* e.g. occurring during the transmission of the input digital signals from the upstream located device to the switching system SW.
• errors* e.g. occurring during the transmission of the input digital signals from the upstream located device to the switching system SW.
• the transmission quality of the virtual communication path used is adversely affected. It may even happen that the faulty header is equal to the header of a packet belonging to another virtual communication path so that also the transmission quality of the latter path is adversely affected.
• the purpose of the header correction circuit HC is to improve the overall system quality by correcting the received faulty headers* and to collect information which is indicative of the reliability of the system.
• * HC includes means (not shown) to process the header of a received packet* the data of this packet being directly transmitted to the routing circuit RT. Normal communication packets are then transmitted to the switching bus SB * whereas synchronization or control packets are supplied to the SPC.
• the processing of the header consists of comparing the incoming header with valid headers contained in a table (not shown) or calculated by means of an algorithm. If the incoming header is equal to one of the valid headers* it is correct and therefore is sent to the routing circuit RT.
• control packets and synchronization packets supplied to input terminal RxO of the receive circuit RC are fed through SC* IQ* HC and RT and are finally stored in SPC.
• the latter includes means (not shown) to analyze the packets received and to thereby distinguish between control packets and synchronization packets.
• control packets* which for instance contain information about a virtual communication path to be established* the SPC communicates to the routing circuit RT an outgoing header to be used to replace the incoming header of the incoming packets to route further these packets on the virtual commun cation path. More particularly* the incoming header* the outgoing header and also the address of the transmit circuit of SW forming part of the virtual communication path are stored* as long as this path remains established* in a routing table (not shown) included in the routing circuit RT. In this way* when a virtual communication path has been established the routing circuit RT replaces the incoming header of each incoming packet of that path by the associated outgoing header and transmits the modified packet and the address of the associated transmit circuit to the switching bus SB.
• the routing table RT is then able to substitute the outgoing header for the incoming header without the control of the processor SPC.
• control packets may also be received when a virtual communicat on path is already established. These packets contain then information to update that virtual communication path* i.e. the outgoing header and/or the address stored in the routing table of the routing circuit RT.
• the transmission of the packets on the virtual communication path occurs in a synchronous manner at least one synchron zation packet will be received by SPC within the predetermined time interval allocated to the synchronization packet and no action is taken by SPC.
• the SPC does not receive such a synchronization packet or a signal from the SC indicating that a synchronization packet has arrived within this time interval* it orders the synchronization circuit SC to delay by one or more bits the signals received at the input terminal RxO.
• the packets transmitted by the output portion of the input storage circuit IQ to the routing circuit RT are shifted by as much bits. This operation is repeated until the routing circuit RT recognizes the header of a synchronization packet which is then transmitted to the SPC.
• the header and the data of a same normal communication packet should arrive simultaneously at the switching bus SB. But* since only the header is processed by HC and by RT* it may be subjected to a small delay during its transmission from IQ to SB. Therefore* the data of a packet are latched in IQ for a longer time than the header.
• a possibility to reduce the number of parallel links and thus the dimensions and the control of the switching bus SB is to split the packets of 16 bytes which arrive thereat into four portions of 4 bytes each comprising a part of the header and a part of the data. These four portions are then regrouped in a complete packet of 16 bytes in the output storage circuit 0Q.
• the operation of the transmit circuit TC is considered hereinafter.
• the identification circuit IC forming part of the transmit circuit TC shown is synchronized to the timeslots of the switching bus SB by the timing circuit TM. It is able to read the various addresses of the transmit circuits which have been loaded in these timeslots by the routing circuit RT in the way described above.
• IC* among the addresses read* recognizes the address of its own transmit circuit TC * the header and the data of the packet also loaded in that same timeslot are transferred from the SB to the output storage circuit OQ. This transfer is controlled by IC via the control terminal 01. From there * the packets are transmitted on the asynchronous time division transmission link connected to TxO.
• the ability to change the transmission rate of the input and of the output signals is useful to adapt these rates to the properties of the transmission links and of the coupled devices so that a same switching system SW may be used to switch a wide frequency range of signals such as voice* data and video as mentioned above.

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• 1986
  • 1986-01-24 BE BE2/60910A patent/BE904100A/fr not_active IP Right Cessation
  • 1986-12-22 AU AU66861/86A patent/AU6686186A/en not_active Abandoned
• 1987
  • 1987-01-15 US US07/004,367 patent/US4813037A/en not_active Expired - Lifetime
  • 1987-01-20 JP JP87501162A patent/JPH01501589A/ja active Pending
  • 1987-01-20 WO PCT/EP1987/000027 patent/WO1987004579A1/en active IP Right Grant
  • 1987-01-20 HU HU871038A patent/HU203178B/hu not_active IP Right Cessation
  • 1987-01-20 AU AU70241/87A patent/AU588441B2/en not_active Ceased
  • 1987-01-20 EP EP87901043A patent/EP0290459A1/en active Pending
  • 1987-01-20 BR BR8707537A patent/BR8707537A/pt not_active IP Right Cessation
  • 1987-01-20 ES ES87200083T patent/ES2022868B3/es not_active Expired - Lifetime
  • 1987-01-20 AT AT87200083T patent/ATE62366T1/de not_active IP Right Cessation
  • 1987-01-20 EP EP87200083A patent/EP0231967B1/en not_active Expired - Lifetime
  • 1987-01-20 KR KR1019870700866A patent/KR880701048A/ko not_active Application Discontinuation
  • 1987-01-20 DE DE8787200083T patent/DE3768976D1/de not_active Expired - Lifetime
  • 1987-08-27 NO NO873612A patent/NO873612L/no unknown
  • 1987-09-24 DK DK501987A patent/DK501987A/da not_active Application Discontinuation
• 1988
  • 1988-06-10 FI FI882784A patent/FI90931C/sv not_active IP Right Cessation
  • 1988-07-20 BG BG085005A patent/BG49389A3/xx unknown

Non-Patent Citations (1)

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