EP0276884A1 - Bildersynthetisiergerät - Google Patents

Bildersynthetisiergerät Download PDF

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Publication number
EP0276884A1
EP0276884A1 EP88200089A EP88200089A EP0276884A1 EP 0276884 A1 EP0276884 A1 EP 0276884A1 EP 88200089 A EP88200089 A EP 88200089A EP 88200089 A EP88200089 A EP 88200089A EP 0276884 A1 EP0276884 A1 EP 0276884A1
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EP
European Patent Office
Prior art keywords
image
register
bits
abscissa
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP88200089A
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English (en)
French (fr)
Other versions
EP0276884B1 (de
Inventor
Jean-Claude Société Civile S.P.I.D. Six
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Radiotechnique Compelec RTC SA
Photonis SAS
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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Publication date
Application filed by Radiotechnique Compelec RTC SA, Photonis SAS, Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Radiotechnique Compelec RTC SA
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Publication of EP0276884B1 publication Critical patent/EP0276884B1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Definitions

  • the invention relates to a digital image synthesizer device intended in particular for managing the overlaps of several image planes described line by line according to a television-type scanning system, associated with a microprocessor and at least one image generator which generates at least one image in real time from a pixel memory, device comprising in particular a controller for governing the overlap of a television image by an image plane or of an image plane by another plane image.
  • Such a device is used in particular in video processors of home computers, multi-image cathode ray tube controllers or else video processors for interactive digital audio-disc, called CD-I.
  • the object of the invention is to provide additional means for managing the overlap of one image by another.
  • Means for this are known from the so-called "Antiope" teletext system.
  • a digitally transmitted character matrix can be superimposed on a television picture.
  • this matrix is explored in synchronism with the television scan by an abscissa counter which successively points to the characters in a character memory, where one of the bits of the character description determines whether it is transparent or not. . According to this bit, the television picture is displayed or, on the contrary, replaced by the description of the character for the duration of this character.
  • This system allows parts of images (Antiope characters) generated by the device to be inserted into an image (television image) which is not generated by the device.
  • the format of the superimposed characters is fixed once and for all.
  • the objects to be represented are stored in memories each corresponding to a degree of priority, and one generates in a memory image a pixel map of the image. For this, we search for each pixel position if there is an object in the memory with maximum priority, in which case it is displayed, otherwise we search in the memory with the next priority and so on. It is also advisable during the filling of the image memory by an object, to search for each pixel if it does not correspond to the beginning of another object in a higher priority memory, in which case we will read from this pixel the contents of this last memory.
  • the device according to the invention makes it possible to vary the priorities of the different images during a line and to modify the priorities during the return between one line and the next, because very little data is sufficient to obtain this effect.
  • the device according to the invention is notably remarkable in that it comprises a so-called region register containing a series of words comprising in particular an abscissa value, means for reloading this register from the image generator during the returns of scan, a current abscissa counter of the displayed pixels, a pointer counter of the words in the region register, an abscissa value comparator which compares the content of the current abscissa counter with the abscissa contained in the word pointed in the region register by the word counter, and produces, when there is identity, a signal which triggers the establishment of one of at least two predetermined types of overlapping of the image planes, and increments the word counter of the re register of regions.
  • the device advantageously comprises a register known as types of recoveries, in which at least two of the above-mentioned predetermined types of recovery are defined and this register is divided into several parts, one part being constituted by a first set of bits contained in the register. of regions, another part being formed by a second set of controller control bits, the first set of bits being an operation code which can cause the change of a conditional bit, called of regions, to each state of which corresponds a type of overlap defined by the second set of bits.
  • a register known as types of recoveries in which at least two of the above-mentioned predetermined types of recovery are defined and this register is divided into several parts, one part being constituted by a first set of bits contained in the register. of regions, another part being formed by a second set of controller control bits, the first set of bits being an operation code which can cause the change of a conditional bit, called of regions, to each state of which corresponds a type of overlap defined by the second set of bits.
  • one of the types of overlapping of the image planes is an overlapping by a series of pixels whose color remains constant between two abscissa identity signals.
  • the words in the region register advantageously include the indication of the image concerned, in order to allow the processing of two image planes with the same region register.
  • FIG. 1 the device according to the invention is indicated by the reference 1. It is used in combination with a microprocessor 24, itself connected by its bus with an image generator 2, 3, 4 which generates in real time that is to say in synchronism with a scanning by successive lines of the television type, successive words each of which defines a pixel of the image.
  • This generator consists here of a master processor 2 which builds an image from descriptive elements of objects stored in a pixel memory 3 to which it is connected by a bus 11, and of an identical slave processor 2B associated to a 3B memory.
  • the master processor is also associated with a graphics processor 4 which is connected to the main bus and also to the bus 11 of the memory, and subtracts certain repetitive operations to increase the power of the master processor.
  • Such processors are described for example in the documents FR-A-2,569,020 and EP-A-0145046.
  • the slave processor is so called only because its clock and its synchronization are imposed on it by the master processor. It generates images whose content is independent of those of the master processor.
  • the device 1 generates the red, green, blue components of a composite image, on three analog RGB outputs, to attack a television set or a monitor equipped with video inputs for the three colors.
  • the device processes several images in parallel and finally combines them by making overlaps or additions with the pixel values, and this pixel by pixel.
  • the device is controlled by control bytes passing through the pixel input ports during control sequences, during the scan back periods.
  • the two input streams can be processed in various ways to generate 1 to 3 images, depending on the mode chosen.
  • the overlay of television images is controlled by the device.
  • the master processor 2 supplies the device 1 with bytes of data describing in particular the pixels of an image via an 8-wire connection P0-7 and the rhythm necessary for reading this data is transmitted by a PCLK1 connection.
  • the slave processor 2B supplies the data for another image via the connections P8-15 and PCLK2.
  • FIG. 2 represents in more detail the content of the device 1 of FIG. 1. It is divided into two roughly identical channels # 1 and # 2 each corresponding to at least one image. The elements of channel # 2 which correspond to those of channel # 1 have the same references with an additional index B.
  • the device comprises as input a multiplexer 5 to which the pixel bytes in P0-7 and P8-15 are brought, and the clocks PCKL1-2.
  • bytes P0-7 are used by channel # 1
  • bytes P8-15 are operated by channel # 2.
  • the data from the multiplexer 5 pass for each channel by a "latch" circuit 8, 8b which maintains the value of the bits until the validation of the following ones.
  • the data is brought to the color decoders 15, 16, 15B, 16B, the outputs of which are applied to output multiplexers 18, 18B governed by a controller 19 for overlapping the image by the other, and a MODE register.
  • the latter is constituted and connected in a known manner in computer science to most of the elements of the figure to set up the different modes of operation which will be described later. It is not shown in order not to complicate the figure. For the same reason, some secondary interconnections are not shown.
  • the outputs of the multiplexers 18, 18b are finally brought to an adder-converter 22 which digitally adds the images of two channels, then converts the digital data into red, green, blue analog values present on the connections R, G, B respectively which are directly applicable to the video stages of a color television or monitor.
  • an adder-converter 22 which digitally adds the images of two channels, then converts the digital data into red, green, blue analog values present on the connections R, G, B respectively which are directly applicable to the video stages of a color television or monitor.
  • Two weighting circuits 20, 20B also governed by the controller 19 each provide the adder 22 with a so-called weighting digital value by which the latter multiplies the color amplitude data of each channel before adding them.
  • these weighting values are 1/0 or 0/1 to choose the image of channel # 1 or that of channel # 2 respectively.
  • intermediate values for example 0.5 / 0.5, provide a mixture of the two images at will, for example to create a crossfade effect.
  • CLK image line synchronization signals are supplied by the master processor of FIG. 1 to an internal clock circuit 6 which synchronizes the functions of the device.
  • the input data can define the color of a pixel according to several methods:
  • each pixel is defined by a set of 8 bits representing a color code. This bit set is therefore used to point an address into a fast RAM which provides the color values.
  • a fast RAM which provides the color values.
  • Such a system which is called a palette, and bears the indication CLUT1 or CLUT2 (Color Look Up Table in English), is referenced 15, 15B in FIG. 2.
  • each byte of channel # 1 defines two pixels with 4 bits per pixel and the palette CLUT1 is divided under the command of the MODE register into two blocks each corresponding to 4 address bits which provides two images which can each present 16 different colors.
  • This variant can be used to provide two different images at the output of channel # 1.
  • Another method for defining the color consists, as in television, in providing separately the so-called "Y" luminance and two color differences called U and V.
  • the absolute value is given once at the start of each line to readjust the values in the event of an error during a line.
  • This way is called DYUV. It requires only one byte per pixel, the data Y, U and V being coded each by means of four bits, and the data U and V being transmitted each on four bits, in only one byte in two only, in turn.
  • a DYUV1 or DYUV2 decoder (reference 16, 16B) performs the decoding in this process, which is used when processing natural images with subtle colors.
  • a third method used in the case of ordinary synthetic images consists in directly coding the colors red, green, blue (direct RGB) by means of 5 bits per color, plus 1 bit of transparency, which constitutes 16-bit words.
  • inputs B0-7 and B8-15 are used together and therefore only provide the input capacity for a single image.
  • the two processors 2 and 2B in FIG. 1 work in parallel to each supply half of the bits). This unique image is of course added to the image of outdoor television.
  • the color code does not pass through a decoder since it corresponds directly to the coding necessary for the input of the output multiplexers.
  • the decodings used in the other methods require a certain time. To ensure the synchronism of the "direct RGB" images with the images obtained by the other methods, it is therefore necessary to delay them.
  • two shift registers "FIFO" for First In, First Out
  • FIFO for First In, First Out
  • an external circuit of the so-called PLL type controlled by the synchronization of the television, provides the device with general synchronization which is ahead of that from television.
  • the outputs of the various color decoders are connected to inputs of the multiplexer 18 or 18B which transmits one or the other of the signals.
  • an entry indicated with a zero permanently deletes the image of a channel.
  • Various configurations can be programmed by loading the mode register. This last group of bits defining the mode of channel # 1 and channel # 2, and the data sources for each channel. The two data streams of each 8 bits in parallel can be combined or separated. We define successive planes as well as a background and a foreground.
  • Channel # 1 is rather used to define the foreground image and can be programmed for trans put the data in one of the following ways: - out of order - an image from DYUV1, - an image from the CLUT1 palette - two images from the CLUT1 palette - an image from the CLUT2 palette
  • Channel # 2 is instead used to set the background and can be programmed to transmit data in one of the following ways: - out of order - an image from DYUV2 - an image from the CLUT2 palette - a direct RGB image, from FIFO registers
  • the CLUT1 decoder can provide two images, it is therefore up to three images which can be represented for example on the screen of a television superimposed on the image of the television.
  • a cursor movable in the foreground can be provided. It is generated by a generator 23 which provides the adder 22 with a square of 16 ⁇ 16 pixels each defined by a single bit, and which is always superimposed on any other image when it is present.
  • the images generated are therefore combined to define the final image by superimposing up to 5 different planes which are: - the cursor map - a foreground (channel # 1) - a second foreground (channel # 1) - a background (channel # 2) - the plane of the television picture.
  • a first function of the device consists in defining what is the relative position of each intermediate plane.
  • a second function is to define transparent areas in the planes so that the planes behind them can be seen.
  • Figure 3 gives a very simple example with two planes.
  • the front plan F is transparent at the level of a rectangle through which appears the rear plane B.
  • a particular color has the meaning: "transparent". It is a color defined by its red green blue components. It is therefore at the exit of the palette that we can search if this color is present.
  • This is the function of the three "Comp" comparators referenced 17, 170, 17B. These comparators check at each pixel whether the color corresponds to a predetermined color, in which case the pixel is transparent. The comparators then deliver a signal brought to the recovery controller 19 which programs the corresponding multiplexer 18, 18B so that it ceases to transmit the image during the display duration of the pixel in question.
  • a VDS output of the recovery controller is connected to the adhoc pin of the peri-television socket of the television to ensure the switching between the television image and that (s) from the device.
  • the transparency of the plans can also be controlled according to a coding mechanism whose implementation device constitutes the main object of the present invention.
  • transition points are defined during each scan line and at these transition points the display mode changes.
  • the horizontal position of these points, and the nature of the display change can also be defined during the sweep returns.
  • a region register 13 is used. It is so named because it allows you to define regions in the image.
  • This register contains for example 8 words of 24 bits. One of these words is illustrated in FIG. 4. It contains 4 bits CH0-3 which represent an action to be undertaken, 10 bits RL0-9 which represent an abscissa expressed in number of pixels and 7 optional bits PA0-6. Three X bits are unused.
  • An abscissa counter 7 (FIG. 2) linked to the internal clock 6 makes it possible to know at all times what is in the line the number of the pixel being processed.
  • a counter 10 points to a word in the region register. This counter is reset on each line feed.
  • a comparator 12 receives on the one hand the current abscissa from the counter 7 and on the other hand the abscissa registered in the bits RL0-9 of the word pointed in the region register 13 by the counter-pointer 10. The bits CH0-3 of this word are also transmitted to the controller 19 by the connection 25.
  • the comparator 12 constantly compares the two abscissas and when there is identity of the abscissas, it delivers on the connection 26 a signal which is brought to the controller 19, which performs the action described by the bits CH0-3, and to the pointer 10 words from the region register to increment it. It is therefore a new abscissa which is henceforth compared by the comparator 12, with a new action to be undertaken during the identity of the abscissas and so on until the last word, or until the end of the line.
  • the recovery controller 19 comprises in a register at least one so-called "region" bit.
  • region bit
  • one mode is chosen by programming, for example using a set of 4 bits per plane, called bits T, loaded by the master processor during a time of scan return, and these four bits indicate the meaning of the region bit.
  • An example indicating different possible programming is indicated by table I which relates to four bits T10-13 contained in a register of the controller 19 and relating to the foreground. There are of course two other groups of four bits each concerning one of the other planes.
  • BR the region bit BT: bit No. 16 showing transparency in RGB direct mode
  • CT the bit delivered by the transparent color comparators.
  • the one of the two which is concerned is defined by one of the optional bits of the words of the region register (PA6).
  • the new weighting is indicated by other optional bits (PA0-5).
  • PA0-5 the set of bits CH0-3 of the region word and of the bits T constitutes a register of the types of overlap in which at least two predetermined types of overlap of the planes are defined.
  • this register may not exist: it is then defined once for all in the controller 19 that, for example if the bit of regions is at zero, the pixel concerned is transparent, and vice versa.
  • the action to be undertaken can be defined directly by a group of bits in the words of the region register. Then the type register is entirely contained in the region register.
  • the channel # 1 being controlled by a single region bit, in the case where the CLUT1 palette provides two foreground images, the latter are affected together. This does not prevent that there are differences between the transparencies of these first two planes if provision is made for conditions of interpretation (table I) of the bit of region different for each of these two planes.
  • the 8 words of the region register are in practice grouped in 2 ⁇ 4, each of the groups of four addressing a channel. We can therefore define two windows (4 transitions) per plane. However, since the operation code contains the channel to be assigned, each word can also be addressed to one channel or the other. We can for example use the 8 words of the region register for the same channel, which allows to define 4 windows. In all cases the set of transitions of the set of planes, i.e. of the displayed image, is equal to the number of regions (at least as regards the action of the region controller ).
  • a region relating to channel # 1 is a rectangle in which there is transparency and outside of which there is for example the DYUV mode.
  • the region bit changes and we return to the display of the plane F.
  • a second region bit concerning channel # 2 that is to say the background, defines a transparent circle through which we would see the television image.
  • the device with the region register makes it possible to cover a line part with a series of pixels whose color remains constant between two abscissa identity signals of the comparator 12, which creates additional monochrome objects of any shape and possibly mobile.
  • the data to reload the region register 13 and possibly reprogram the controller 19 are introduced into the device by the same inputs P0-7 and / or P8-15 as the pixels. These inputs are in fact unused during the scanning returns, since the pixels are transmitted in real time, that is to say during the forward periods of the scanning.
  • the inputs WR1 and WR2 are used to indicate to the input multiplexer 5 that this is such data and no longer image pixels.
  • - the mode register This allows for example to have at the top of an image a part in subtle colors obtained via a DYUV decoder, and at the bottom a synthetic image part of subtitling obtained in direct RGB mode.
  • - the content of a palette.
  • the cursor in the generator 23 that is to say a group of 32 bytes defining 16 ⁇ 16 pixels, a color (4 bits) and coordinates X, Y.
  • processor 2 have 32 bits. They are introduced into system 1 by halves, that is to say by 16 bits both on the inputs P0-7 and P8-15 together. In these words, four bits for example define the operation to be carried out, that is to say in general the register for receiving the information, and the other 28 bits represent said information itself.
  • - change semi-permanent data such as the color of the monochrome frame which possibly surrounds the image.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
  • Image Generation (AREA)
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EP88200089A 1987-01-27 1988-01-20 Bildersynthetisiergerät Expired - Lifetime EP0276884B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8700917A FR2610160B1 (fr) 1987-01-27 1987-01-27 Dispositif synthetiseur d'images
FR8700917 1987-01-27

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EP0276884A1 true EP0276884A1 (de) 1988-08-03
EP0276884B1 EP0276884B1 (de) 1992-04-15

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EP88200089A Expired - Lifetime EP0276884B1 (de) 1987-01-27 1988-01-20 Bildersynthetisiergerät

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US (1) US4866524A (de)
EP (1) EP0276884B1 (de)
JP (1) JPS63193177A (de)
KR (1) KR970000824B1 (de)
DE (1) DE3869974D1 (de)
FR (1) FR2610160B1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0669019A4 (de) * 1992-11-12 1995-07-03 Marquette Electronics Inc Steuerungsvorrichtung fur rechneranzeige mit fenstern.
EP0840276A2 (de) * 1996-11-01 1998-05-06 Texas Instruments Incorporated Fensterverarbeitung in einem Bildschirmanzeigensystem
EP0840277A2 (de) * 1996-11-01 1998-05-06 Texas Instruments Incorporated Fensterverarbeitung in einem Bildschirmanzeigesystem
US6310657B1 (en) 1996-11-01 2001-10-30 Texas Instruments Incorporated Real time window address calculation for on-screen display

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4947257A (en) * 1988-10-04 1990-08-07 Bell Communications Research, Inc. Raster assembly processor
US5128766A (en) * 1989-11-30 1992-07-07 Goldstar Co., Ltd. Multiple television receiver with teletext function
US5327243A (en) * 1989-12-05 1994-07-05 Rasterops Corporation Real time video converter
US5226177A (en) * 1990-03-27 1993-07-06 Viewfacts, Inc. Real-time wireless audience response system
DE69328386T2 (de) * 1992-09-30 2000-08-24 Hudson Soft Co Ltd Bildverarbeitungsgerät
US5572235A (en) * 1992-11-02 1996-11-05 The 3Do Company Method and apparatus for processing image data
US5604514A (en) * 1994-01-03 1997-02-18 International Business Machines Corporation Personal computer with combined graphics/image display system having pixel mode frame buffer interpretation
US5502504A (en) * 1994-04-28 1996-03-26 Prevue Networks, Inc. Video mix program guide
US5877741A (en) * 1995-06-07 1999-03-02 Seiko Epson Corporation System and method for implementing an overlay pathway
JP2861890B2 (ja) * 1995-09-28 1999-02-24 日本電気株式会社 カラー画像表示装置
US5990928A (en) * 1997-05-30 1999-11-23 Rockwell International Corporation Method and apparatus for receiving broadcast entertainment transmissions at a moving receiver station
US6678009B2 (en) * 2001-02-27 2004-01-13 Matsushita Electric Industrial Co., Ltd. Adjustable video display window
US6990338B2 (en) * 2001-06-11 2006-01-24 The Boeing Company Mobile wireless local area network and related methods
US8780128B2 (en) * 2007-12-17 2014-07-15 Nvidia Corporation Contiguously packed data
KR101035171B1 (ko) * 2009-12-28 2011-05-17 대원강업주식회사 차량용 백 테이블

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317114A (en) * 1980-05-12 1982-02-23 Cromemco Inc. Composite display device for combining image data and method
GB2144952A (en) * 1983-07-08 1985-03-13 Sharp Kk Multiwindow display circuit
WO1986005910A1 (en) * 1985-04-03 1986-10-09 British Telecommunications Public Limited Company Video display apparatus

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3674930A (en) * 1969-10-02 1972-07-04 Massachusetts Inst Technology Video pointer
US3833760A (en) * 1973-02-27 1974-09-03 Ferranti Ltd Television systems
GB1434783A (en) * 1973-03-09 1976-05-05 Nat Res Dev Apparatus and methods for computer graphics
US3911419A (en) * 1973-11-23 1975-10-07 Xerox Corp Controller for cursor positioning on a display medium
US4208675A (en) * 1978-03-20 1980-06-17 Agence Nationale De Valorization De La Recherche (Anvar) Method and apparatus for positioning an object
DE2939458A1 (de) * 1979-09-28 1981-05-21 Siemens Ag System zur lokalisierung von bereichen bei gemischter text-/bildbearbeitung am bildschirm
DE2939489A1 (de) * 1979-09-28 1981-05-14 Siemens Ag System zur lokalisierung von bereichen bei gemischter text-/bildbearbeitung am bildschirm
SE428161B (sv) * 1981-10-14 1983-06-06 Philips Svenska Ab Anleggning for atergivning av valbar bakgrundsinformation kombinerad med valbar overlagringsinformation pa en bildskermsanordning samt anvendning av en dylik presentationsanleggning
FR2569020B1 (fr) * 1984-08-10 1986-12-05 Radiotechnique Compelec Procede pour creer et modifier une image synthetique
US4639765A (en) * 1985-02-28 1987-01-27 Texas Instruments Incorporated Synchronization system for overlay of an internal video signal upon an external video signal
JP2650186B2 (ja) * 1985-06-26 1997-09-03 三菱電機株式会社 静止画映像信号処理装置
JPS62153893A (ja) * 1985-12-27 1987-07-08 株式会社日立製作所 文字図形表示装置
US4768083A (en) * 1987-04-29 1988-08-30 Rca Licensing Corporation Digital TV having on-screen display feature

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317114A (en) * 1980-05-12 1982-02-23 Cromemco Inc. Composite display device for combining image data and method
GB2144952A (en) * 1983-07-08 1985-03-13 Sharp Kk Multiwindow display circuit
WO1986005910A1 (en) * 1985-04-03 1986-10-09 British Telecommunications Public Limited Company Video display apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0669019A4 (de) * 1992-11-12 1995-07-03 Marquette Electronics Inc Steuerungsvorrichtung fur rechneranzeige mit fenstern.
EP0669019A1 (de) * 1992-11-12 1995-08-30 Marquette Electronics, Inc. Steuerungsvorrichtung fur rechneranzeige mit fenstern
EP0840276A2 (de) * 1996-11-01 1998-05-06 Texas Instruments Incorporated Fensterverarbeitung in einem Bildschirmanzeigensystem
EP0840277A2 (de) * 1996-11-01 1998-05-06 Texas Instruments Incorporated Fensterverarbeitung in einem Bildschirmanzeigesystem
EP0840276A3 (de) * 1996-11-01 1999-06-23 Texas Instruments Incorporated Fensterverarbeitung in einem Bildschirmanzeigensystem
EP0840277A3 (de) * 1996-11-01 1999-06-23 Texas Instruments Incorporated Fensterverarbeitung in einem Bildschirmanzeigesystem
US6310657B1 (en) 1996-11-01 2001-10-30 Texas Instruments Incorporated Real time window address calculation for on-screen display
US6452641B1 (en) 1996-11-01 2002-09-17 Texas Instruments Incorporated Method and apparatus for providing and on-screen display with variable resolution capability

Also Published As

Publication number Publication date
DE3869974D1 (de) 1992-05-21
JPS63193177A (ja) 1988-08-10
KR880009518A (ko) 1988-09-15
FR2610160B1 (fr) 1989-03-24
EP0276884B1 (de) 1992-04-15
KR970000824B1 (ko) 1997-01-20
FR2610160A1 (fr) 1988-07-29
US4866524A (en) 1989-09-12

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