EP0256904B1 - Verfahren zur Herstellung von BiCMOS-Strukturen von hoher Leistungsfähigkeit mit Polysilizium-Emittern und Transistorbasen aus Siliziden - Google Patents

Verfahren zur Herstellung von BiCMOS-Strukturen von hoher Leistungsfähigkeit mit Polysilizium-Emittern und Transistorbasen aus Siliziden Download PDF

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EP0256904B1
EP0256904B1 EP87401630A EP87401630A EP0256904B1 EP 0256904 B1 EP0256904 B1 EP 0256904B1 EP 87401630 A EP87401630 A EP 87401630A EP 87401630 A EP87401630 A EP 87401630A EP 0256904 B1 EP0256904 B1 EP 0256904B1
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layer
region
conductivity type
regions
forming
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EP0256904A1 (de
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Prateep Tuntasood
Juliana Manoliu
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Definitions

  • This invention relates to processes for manufacturing integrated circuits, and to a process for simultaneously fabricating bipolar and complementary field effect transistors in a semiconductor substrate. More particularly, the invention relates to the fabrication of such devices having lower base resistance and a polysilicon emitter, and to the fabrication of a completed BiCMOS structure having very high performance.
  • CMOS complementary metal oxide semiconductor
  • Bipolar and complementary metal oxide semiconductor (CMOS) technologies have each been independently understood for many years.
  • BiCMOS bipolar output drivers may be employed with CMOS memories to provide more drive current.
  • MOS slows down as temperature rises while bipolar speeds up
  • a CMOS bipolar combination may be employed to make devices less speed sensitive to temperature.
  • Combining high performance bipolar devices with MOS transistors on the same integrated circuit allows a combination of the high-packing density of MOS devices with the high speed of bipolar and permits the integration of complex functions with high yields.
  • the CMOS transistors with their inherently low power requirements have large noise margins, while the bipolar devices have an advantage in switching speed and greater current drive per unit area.
  • US-A-4,484,388 discloses a method for forming a Bi-CMOS structure including a vertical npn-transistor and CMOS transistors on a common semiconductor substrate.
  • a p-type epitaxial layer is formed on a p-type silicon substrate with a plurality of n+-type buried layers therein.
  • N-type wells are formed to extend to the n+-type buried layers.
  • Field oxide films are formed to define an n-type element region for the npn-transistor, an n-type element region for the PMOS-transistor, and a p-type element region for the NMOS-transistor.
  • a gate oxide layer for the CMOS is formed on the surfaces of all element regions.
  • a p-type active base region for the npn-transistor is formed by boron ion implantation, and an emitter electrode comprising an arsenic-doped polysilicon layer contacts the base region.
  • CMOS gate electrodes exhibit low resistance due to phosphorus and/or arsenic doping.
  • the emitter electrode is utilized as a diffusion source to form an n-type emitter region. Boron ion implantation results simultaneously in a p+ -type external base region and p+-type source and drain regions of the PMOS-transistor while phosphorus ion implantation results in an n+-type collector contact region and n+-type source and drain regions of the NMOS-transistor. With few masking steps, the device performance does not satisfy, and the document teaches multiple masking steps in order to achieve improved performance.
  • FR-A-2 134 360 discloses a method for fabricating monolithic semiconductor devices including the following steps: Provision of a semiconductor substrate of a first conductivity type, introduction thereinto of two impurities of opposite conductivity and of different diffusion rate at predetermined zones, forming of an epitaxial layer of the first conductivity type on the substrate, treatment of the substrate including the epitaxial layer so as to cause complete rediffusion of one of the impurities through all of the epitaxial layer to reach its surface opposite the interface with the substrate, and forming at a predefined site of the surface a bipolar transistor. At other sites of the device, field effect transistors may be formed.
  • the two impurities may be arsenic and phosphorus, respectively.
  • the base of the bipolar transistor may be formed in a single diffusion step simultaneously with source and drain of a first field effect transistor, and the emitter of the bipolar transistor may be formed in a single diffusion step simultaneously with source and drain of the second field effect transistor.
  • CMOS complementary metal-oxide-semiconductor
  • our method of fabricating a BiCMOS semiconductor structure on a first conductivity substrate begins with the formation of an opposite conductivity buried layer by the steps of introducing into at least one first region of the substrate a first impurity of N conductivity type, typically arsenic, and then introducing into the first region a second impurity of N conductivity type, typically phosphorus. Then, a blanket implantation of the substrate with P conductivity type impurity which will form the P buried layers beneath the P wells of the structure is performed. The P wells are used for fabrication of NMOS devices. An epitaxial layer is formed over the substrate, and parts of the epitaxial layer overlying the buried layers are doped with N conductivity type impurity.
  • the structure is then heated to cause the N conductivity type impurity regions in the epitaxial layer and in the substrate to diffuse to contact each other.
  • this process results in the fabrication of buried layers which have low resistance, yet high diffusivity to lower the capacitance between the substrate and the buried layers.
  • the process assures that the preferably N type buried layers join with the N conductivity type well formed in the epitaxial layer for the P channel MOS devices and NPN bipolar devices. Accurate control of the N well dopant and fabrication of the buried layers in a shorter time minimize the effects of prolonged high-temperature processing.
  • the method then includes the steps of forming an insulating layer over the surface of the silicon layer, and forming a conductive protective layer, typically polycrystalline silicon, over all of the insulating material.
  • the insulating layer then is removed from the surface of the epitaxial silicon layer in the bipolar region and first conductivity type impurity is introduced into a part of the bipolar area to define the base. Additional conductive material is deposited over at least the bipolar region, and all of the protective layer is removed from the insulating layer except where gates and the emitter are desired. The sources and drains then are doped.
  • the initially formed insulating layer will provide the gate oxide, while the protective layer provides the polycrystalline silicon electrodes for the MOS devices.
  • the single mask defines both the base of the bipolar devices and distinguishes the bipolar devices from the CMOS devices. Later in the process a single mask defines both the gates and the emitter for the structure.
  • the protective layer not only serves as the gate electrodes, but also protects the gate oxide from the effect of subsequent processing to prevent the etching of openings in the gate oxide in places other than desired.
  • the semiconductor structure from our process has a lower base resistance for the bipolar devices and is fabricated in a smaller area. The reduced area lowers the capacitance and increases the speed of the circuit. Forming the additional protective material adjacent the field oxide creates a walled emitter structure, while providing less sensitivity to alignment tolerances.
  • front-end and back-end processes are used to form the semiconductor structure through the buried layers and epitaxial layer, while the back-end processes are used to complete the structure.
  • back-end processes are used to complete the structure.
  • a single front-end process may be combined with any one of a variety of back-end processes while a single back-end process may be combined with any one of a variety of front-end processes.
  • Figure 1 is a cross-sectional view of a semiconductor substrate 10 having a crystalline orientation of ⁇ 100>, and which has been doped with P conductivity type impurity to a resistivity of 11-18 ohm centimeters.
  • the silicon substrate may be protected with a thin layer of silicon dioxide and alignment marks formed therein. This step may be eliminated if the later-formed buried layer regions are to be used for alignment.
  • Mask 15 typically will comprise photoresist, applied and defined using well known photolithographic or other techniques. Openings are made in mask 15 wherever an N conductivity type buried layer is desired. N type buried layers are desired wherever the P channel MOS devices and NPN bipolar devices will be formed. No N type buried layer is fabricated where N channel MOS devices are desired.
  • a first N conductivity type impurity is implanted, followed in the preferred embodiment by a second N conductivity type impurity implanted in the same region.
  • the N type impurity dopants are shown as regions 18 in Figure 1.
  • the first N type impurity is phosphorus introduced with a dosage of 3x1013 to 3x1014 atoms per square centimeter, while the second impurity is arsenic at a dosage of 1x1015 to 1x1016 atoms per square centimeter.
  • the arsenic lowers the resistance of the buried layer, the higher diffusivity of phosphorus allows it to diffuse further into the substrate (as well as into an overlying epitaxial layer), to lower the capacitance between the substrate and the buried layer in the bipolar devices.
  • the double implant also assures that the N well implant in the epitaxial layer and in the buried layer join during subsequent thermal processing. This advantage is discussed further below.
  • a blanket implant of P conductivity type impurity 12 is introduced across the entire surface of the substrate. This impurity ultimately will form a P conductivity type buried layer for the N channel CMOS transistors.
  • an upper portion 12 of substrate 10 is doped with 3x1012 to 5x1013 atoms per square centimeter of boron.
  • epitaxial layer 21 is deposited across the silicon substrate 10 in the manner shown in Figure 2.
  • epitaxial layer 21 is undoped, and about 1 to 2 ⁇ m (microns) thick.
  • the formation of such epitaxial layers is well known.
  • a thin layer of protective silicon dioxide (not shown) is formed by oxidizing the upper surface of the epitaxial layer.
  • an N well mask 24 is formed across the upper surface of the epitaxial layer (or silicon dioxide) to define the regions where N conductivity type wells are desired in the epitaxial layer. As shown in Figure 2, such wells are desired for electrical isolation of the PMOS and NPN devices.
  • the N well mask comprises photoresist, which may be patterned using the same mask as the N type buried layers. Alternatively, and as shown in Figure 3 by the relative dimensions of the N-wells and buried layers, an oversize mask may be used.
  • the N conductivity type wells are implanted, preferably using phosphorus and a dose of 1-2x1012 atoms per square centimeter.
  • the surface of the epitaxial layer 21 is again cleaned and reoxidized by heating it to a temperature of 900°C for 30-60 minutes to form about 25-50 nm (250-500 Angstroms) of silicon dioxide 33 across the entire epitaxial layer 21.
  • a layer of silicon nitride 35 approximately 120-170 nm (1200-1700 Angstroms) thick is deposited, preferably using chemical vapor deposition, across the surface of silicon dioxide 33.
  • silicon nitride layer 35 is removed from the surface of the silicon dioxide 33 wherever regions of field oxide 39 are desired.
  • the field oxide is formed at the intersections of the N wells 27 and 28 with the P well 30.
  • regions of silicon dioxide are annular when viewed from above and serve to separate the N and P wells from each other at the surface.
  • Additional regions of field oxide 39 are formed within the N and P wells themselves, for example, as shown in N well 28 for the NPN transistor, to allow a connection to the buried collector, which connection is isolated from the extrinsic base.
  • the field oxide allows an isolated tap to the substrate, as it does in the P well 30.
  • a field implant may be performed if desired. Such an implant assists in preventing channel inversion at the silicon dioxide-silicon interface resulting from impurity in the silicon dioxide field regions.
  • the field implant employs boron and a dose of 5x1012 to 2x1013 atoms per square centimeter. Unlike prior art processes, no mask is required for this implant. Our process uses the nitride layer 35 as the mask and later process steps compensate for the P type dopant beneath the field regions.
  • the structure is raised to a temperature of about 1050-1100°C for 1-2 hours in Nitrogen to diffuse the P and N conductivity type impurities employed to form the buried layers and wells. Then, the field is oxidized to create silicon dioxide regions 39. In the preferred embodiment such regions are approximately 600 nm (6000 Angstroms) thick formed by heating the structure to about 900°C for 400 minutes. The appearance of the structure following this process is shown in Figure 3. Note that the phosphorus has diffused up from the buried layer to contact the downwardly diffusing N well.
  • the BiCMOS process of our invention as thus far performed provides several unique advantages over prior art processes.
  • the arsenic lowers the resistance of the buried layer 18, while the phosphorus lowers substrate/buried layer capacitance and assures that the N well implant 27 and buried layer 18 join during a relatively short thermal process.
  • our process minimizes the exposure of the structure to prolonged high temperatures and the resulting degradation, while speeding manufacture of the circuit.
  • an undoped silicon epitaxial layer we allow accurate control of the P well dopant.
  • the process allows minimizing the resistance of both the P and N wells, yet maintaining the doping concentrations thereof at a sufficiently low amount to minimize capacitance between the wells. High levels will lower performance of the bipolar devices and lower breakdown voltages for the CMOS devices.
  • Our process prevents diffusion between the N and P wells to permit a closer spacing of those wells for denser CMOS structures.
  • the thin silicon dioxide layer 33 and silicon nitride layer 35 are removed from the surface of the structure.
  • a layer of gate oxide 100 is formed by heating the substrate in an oxidizing ambient to a temperature of 900°C for approximately 2-4 minutes.
  • a relatively thin layer of protective material typically polycrystalline silicon 30-100 nm (300-1000 Angstroms) in thickness, is deposited across the entire surface of the structure.
  • Polycrystalline silicon layer 103 is formed using a well known chemical vapor deposition processes. This first layer of polycrystalline silicon protects the gate oxide for the fabrication of subsequent MOS devices and prevents the etching of openings in the gate oxide in places other than where the gate oxide is to be removed.
  • a photoresist mask 108 is defined across the surface of the structure, and using well known techniques, an oversized opening is created where the base of the NPN transistor is to be formed.
  • the exposed polysilicon 103 is etched away using well known techniques, and the bipolar base is implanted with boron, typically with a dose of on the order of 1x1013 to 1x1014 atoms per square centimeter at 40-100 KeV.
  • base region 110 is formed beneath the thin oxide 100 in the manner depicted in Figure 6.
  • the gate oxide is removed from the surface of the NPN transistor area.
  • a layer of conductive material 103 also polycrystalline silicon, is deposited across the entire surface of the structure.
  • layer 103 will be thinner than on other regions of the structure. Because the gate oxide was removed from the surface of the NPN device area, the polycrystalline silicon is deposited directly on the silicon in that region.
  • Polysilicon layer 103 is then implanted with arsenic to lower its resistance. In the preferred embodiment, a dose of 1x1015 to 1x1016 atoms per square centimeter is used.
  • a new mask 114 is formed to protect regions where gates of the CMOS devices and a walled emitter of the bipolar device are desired.
  • a single mask defines both the gates and the emitter.
  • the exposed portions of polysilicon layer 103 are removed using well known chemical or plasma processes.
  • the resulting structure is shown in Figure 8.
  • the silicon dioxide acts as an etch stop and prevents further etching.
  • the absence of the gate oxide layer allows the etchant to attack the underlying silicon and results in a slight overetching of the epitaxial silicon, typically about 300-1000 Angstroms. This overetching results from the need to assure complete removal of the undesired polysilicon 103 from the CMOS device areas and the necessity therefore to extend the etching operation.
  • a layer of silicon dioxide (not shown) about 1000-3000 Angstroms thick then is formed across the upper surface of the exposed polysilicon by chemical vapor deposition or other known techniques. Using well known anisotropic etching processes, most of the silicon dioxide is etched from the surface of the structure to leave only oxidized sidewall spacer regions such as base contact spacer 132 and source/drain contact spacer regions 135. In the preferred embodiment such spacer regions will be about 1000-3000 Angstroms wide.
  • N conductivity type impurity is implanted through the mask openings.
  • a first dose of phosphorus of 1x1013 to 1x1014 atoms per square centimeter followed by a second dose of arsenic of 6x1015 atoms per square centimeter at 100 KeV are employed.
  • Two impurities are used to form a lightly doped drain type structure because the phosphorus will diffuse under the spacer oxide 135 toward the channel.
  • the implant forms a collector contact 115 for the bipolar transistor, a substrate tap 118 for the P channel MOS device, and source/drain regions 120 for the N channel MOS device.
  • a first light dose of N type impurity is introduced before formation of the spacer regions and a second dose of N type impurity is introduced after formation of the spacer regions.
  • a P type impurity implant preferably boron at a dose of 3x1015 atoms per square centimeter and an energy of 50 KeV, is employed to form the P type source and drain 124 of the P channel device and the substrate tap 127 of the N channel device.
  • the NPN base and P channel source and drain are separately implanted, their performance may be independently optimized.
  • the P and N conductivity type implants are annealed by heating the structure to a temperature of 900°C for 30-90 minutes. During annealing the impurity in the polysilicon contact 103 to the bipolar transistor will diffuse into the epitaxial silicon to form the emitter 130.
  • an extrinsic base region implant to lower the base resistance may be performed at this stage of the process by masking all of the structure except for the base region and then introducing additional impurity. If this step is performed, a dose of 5x1014 to 2x1015 atoms per square centimeter of boron is employed. The spacer 132 prevents the implant from being placed too close to the emitter.
  • silicide forming metal is deposited across the upper surface of the structure and the structure heated to cause the metal to react with the underlying silicon, both polycrystalline and monocrystalline, to form regions of metal silicide. Unreacted metal then is removed selectively by a wet chemical etch. Any metal which will react with silicon to form a silicide may be employed; however, in the preferred embodiment, approximately 50-100 nm (500-1000 Angstroms) of platinum are sputtered onto the surface and the structure heated to 400-450°C for 5-30 minutes to form platinum silicide. Platinum silicide forms excellent contacts to P type regions.
  • Silicide region 136 is an electrical contact via polycrystalline silicon 103 to emitter 130 (as well as to any other component such as a nearby resistor formed on field oxide 39), while silicide region 137 is a contact to base region 110.
  • the collector contact is silicide contact 138.
  • silicide regions 139 provide source/drain contacts, while silicide 140 contacts the gate, and silicide 141 is a substrate tap.
  • silicide 142 contacts the source/drain regions, while silicide 143 contacts the gate, and silicide 144 connects to the substrate tap.
  • the appearance of the structure after formation of the silicide is depicted in Figure 10.
  • the structure may be completed by fabrication of metal connections using conventional techniques.
  • the process of our invention provides many advantages over prior art processes. Using a single mask to distinguish the bipolar devices from the CMOS devices, that is, the base mask, and only a single mask to define both the gates and the emitter, high performance devices may be fabricated. Furthermore, the first layer of polycrystalline silicon protects the gate oxide for subsequent MOS devices.

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Claims (15)

  1. Ein Verfahren für die Herstellung einer Halbleiterstruktur in einer Siliciumschicht mit einer oberen Oberfläche und mit einem ersten Bereich (30) eines ersten Leitfähigkeitstyps sowie eines zweiten und eines dritten Bereichs (27, 28) eines zweiten Leitfähigkeitstyps, welcher erste, zweite und dritte Bereich an der Oberfäche voneinander durch Feldbereiche (39) aus Isoliermaterial getrennt sind, die in die Schicht eingesetzt sind, welches Verfahren umfaßt:
       Bilden einer isolierenden Schicht (100) über der Oberfläche der Siliciumschicht;
       Bilden einer Schutzschicht (103) aus leitendem Material über der gesamten isolierenden Schicht mit Ausnahme eines ersten Abschnitts des dritten Bereichs;
       Einführen einer Dotierung (110) eines Leitfähigkeitstyps in den ersten Abschnitt des dritten Bereichs;
       Verwenden der Schutzschicht als Maske für den Abtrag der isolierenden Schicht von der Oberfläche der Siliciumschicht in dem ersten Abschnitt des dritten Bereichs;
       Aufbringen zusätzlichen leitfähigen Materials über mindestens den ersten Abschnitt des dritten Bereichs;
       Abtragen der Schutzschicht (103) von der isolierenden Schicht mit Ausnahme eines ersten Abschnitts des dritten Bereichs, eines ersten Abschnitts des zweiten Bereichs und eines zweiten Abschnitts des dritten Bereichs, wobei der erste Abschnitt jedes der ersten und zweiten Bereiche von den Feldbereichen beabstandet ist, wobei zumindest ein Teil des zweiten Abschnitts des dritten Bereichs den ersten Abschnitt des dritten Bereichs überlappt; und
       Einführen einer Dotierung (124) ersten Leitfähigkeitstyps in den zweiten Bereich mit Ausnahme der Stelle, wo er von der Schutzschicht überlagert ist, und einer Dotierung (120) zweiten Leitfähigkeitstyps in den ersten Bereich mit Ausnahme der Stelle, wo er von der Schutzschicht überlagert ist.
  2. Ein Verfahren nach Anspruch 1, ferner umfassend, nach dem Schritt des Aufbringens zusätzlichen leitfähigen Materials, den Schritt des Dotierens zumindest des zusätzlichen leitfähigen Materials zur Absenkung seines Widerstandes.
  3. Ein Verfahren nach Anspruch 2, ferner umfassend, nach dem Schritt des Abtrags der Schutzschicht (103), den Schritt des Erhitzens der Struktur zum Bewirken der Diffusion eines Teils der in dem leitfähigen Material enthaltenen Dotierung in dem dritten Bereich.
  4. Ein Verfahren nach Anspruch 1, bei dem der Schritt der Bildung einer Isolierschicht (100) das Oxidieren der Siliciumschicht umfaßt.
  5. Ein Verfahren nach Anspruch 1, bei dem der Schritt der Bildung einer Schutzschicht (103) das Bilden einer Schicht aus polykristallinem Silicium umfaßt.
  6. Ein Verfahren nach Anspruch 5, bei dem der Schritt des Aufbringens von zusätzlichem leitenden Material das Aufbringen zusätzlichen polykristallinen Siliciums umfaßt.
  7. Ein Verfahren nach Anspruch 5, bei dem der Schritt der Bildung einer Schutzschicht (103) das Aufbringen einer Schutzschicht über der gesamten Struktur umfaßt und danach den Abtrag der Schutzschicht von dem ersten Abschnitt des dritten Bereiches.
  8. Ein Verfahren nach Anspruch 1, bei dem der Schritt der Bildung einer Isolierschicht (100) eine Schicht aus Isoliermaterial ergibt zum Trennen mindestens einer Gate-Elektrode eines Feldeffekttransistors von dem darunterliegenden Substrat.
  9. Ein Verfahren nach Anspruch 1,
       bei dem die eingesetzten Feldbereiche (39) aus Siliciumdioxid bestehen,
       bei dem die isolierende Schicht (100) über der Siliciumschichtoberfläche aus Siliciumdioxid besteht, das eine Gate-Isolationsschicht bildet,
       bei dem die Schutzschicht (103) aus leitendem Material eine Schicht aus polykristallinem Silicium ist,
       bei dem der erste Abschnitt des dritten Bereichs eine Basis eines bipolaren Transistors definiert, welche Basis gebildet wird durch den Schritt des Einführens der Dotierung (110) ersten Leitfähigkeitstyps in den ersten Abschnitt des dritten Bereiches,
       bei dem das zusätzliche leitende Material polykristallines Silicium ist und aufgebracht wird auch über der Schicht aus polykristallinem Silicium,
       bei dem der erste Abschnitt des ersten Bereiches eine Gate-Elektrode definiert, der erste Abschnitt des zweiten Bereiches eine weitere Gate-Elektrode definiert, der zweite Abschnitt des dritten Bereiches einen Emitterkontakt definiert, und
       bei dem der Schritt des Einführens der Dotierung (124) ersten Leitfähigkeitstyps in den zweiten Bereich eine Source und einen Drain definiert, und der Schritt des Einführens einer Dotierung (120) zweiten Leitfähigkeitstyps in den ersten Bereich eine weitere Source und einen weiteren Drain definiert.
  10. Ein Verfahren nach Anspruch 1, bei dem die Siliciumschicht eine obere Oberfläche aufweist und einen ersten Bereich (30) eines ersten Leitfähigkeitstyps und zweite und dritte Bereiche (27, 28) eines zweiten Leitfähigkeitstyps aufweist, wobei der erste, der zweite und der dritte Bereich an der Oberfläche voneinander durch Feldbereiche (39) aus isolierendem Material getrennt sind, das in die Schicht eingesetzt ist, wobei die Struktur gebildet wird durch ein Verfahren, das umfaßt:
       Einführen einer ersten Dotierung zweiten Leitfähigkeitstyps in mindestens eine erste Zone eines Substrats,
       Einführen einer zweiten Dotierung zweiten Leitfähigkeitstyps in die erste Zone,
       Bilden einer Epitaxialschicht (21) über dem Substrat, wobei so die genannte Siliciumschicht erzeugt wird,
       Einführen einer Dotierung zweiten Leitfähigkeitstyps in mindestens einen ersten Teil der Epitaxialschicht, der die erste Zone des Substrats überlagert, und
       Erhitzen der Struktur zum Bewirken einer Diffusion der Dotierung zweiten Leitfähigkeitstyps in der Epitaxialschicht und in dem Substrat zum Inkontaktbringen miteinander.
  11. Ein Verfahren nach Anspruch 10, bei dem der Schritt des Einführens der Dotierung zweiten Leitfähigkeitstyps in mindestens einen ersten Teil der Epitaxialschicht (21) das Einführen von Dotierung zweiten Leitfähigkeitstyps in ein Paar von beabstandeten Bereichen der Epitaxialschicht umfaßt zum Definieren einer ersten und einer zweiten Wanne (27, 28), wobei das Paar von beabstandeten Bereichen getrennt ist durch einen Zwischenbereich der Epitaxialschicht von entgegengesetztem Leitfähigkeitstyp zum Definieren einer dritten Wanne (30).
  12. Ein Verfahren nach Anspruch 11, dem der Schritt der Bildung einer Schicht (33) aus Isoliermaterial über der Epitaxialschicht folgt.
  13. Ein Verfahren nach Anspruch 12, bei dem der dritte Bereich mit der ersten Wanne (28) zusammenfällt.
  14. Ein Verfahren nach Anspruch 13, bei dem das Einführen der Dotierung ersten Leitfähigkeitstyps in die erste Wanne durch den ersten Abschnitt hindurch erfolgt.
  15. Ein Verfahren nach einem der Ansprüche 11 bis 14 einschließlich des Schrittes der Bildung elektrischer Verbindungen zu jeder der Wannen.
EP87401630A 1986-07-16 1987-07-10 Verfahren zur Herstellung von BiCMOS-Strukturen von hoher Leistungsfähigkeit mit Polysilizium-Emittern und Transistorbasen aus Siliziden Expired - Lifetime EP0256904B1 (de)

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US06/887,007 US4727046A (en) 1986-07-16 1986-07-16 Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases

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