EP0245346A1 - Procede et appareil d'interface entre des signaux analogiques et un bus de systeme - Google Patents

Procede et appareil d'interface entre des signaux analogiques et un bus de systeme

Info

Publication number
EP0245346A1
EP0245346A1 EP19860906414 EP86906414A EP0245346A1 EP 0245346 A1 EP0245346 A1 EP 0245346A1 EP 19860906414 EP19860906414 EP 19860906414 EP 86906414 A EP86906414 A EP 86906414A EP 0245346 A1 EP0245346 A1 EP 0245346A1
Authority
EP
European Patent Office
Prior art keywords
signals
interface
providing
data
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19860906414
Other languages
German (de)
English (en)
Inventor
Ian Hardie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Burr Brown Ltd
Original Assignee
Burr Brown Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burr Brown Ltd filed Critical Burr Brown Ltd
Publication of EP0245346A1 publication Critical patent/EP0245346A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter

Definitions

  • This invention relates generally to an apparatus providing an interface between devices having analog output signals and a system signal bus for exchanging digital signals with a central processing unit.
  • processing apparatus that can manipulate the data in a predetermined manner.
  • the interface unit are fixed, either during the manufacture of the unit or else are controllable by switches. However, the interface unit can receive signals from the monitored devices that are to be processed in a plurality of modes.
  • a transient data capture mode in which a group of data is acquired for a predetermined period of time
  • the changing of the inode of operation of the interface unit has in the past required manipulation of the interface unit, an activity that can - -
  • an interface unit multiplexer capable of receiving a plurality of analog signals, a sample and hold amplifier for storing a quantity related to a selected analog signal 25.at a predetermined time, an analog to digital converter for providing a digital signal related to the amplitude of the sampled analog signal, a data memory unit for storing the digital value of the signal prior to placing the value on the signal data bus for transmission to the central processing unit, and control circuits for determining the mode of operation of the associated interface apparatus and for providing a sufficient programmable timer.
  • the control circuits include a clock, a control unit for controlling the operation of the remaining units, and an apparatus for 5. providing an interrupt request and related data to the central processing unit.
  • the control circuits permit each analog signal applied to the interface apparatus to be monitored in the most appropriate manner.
  • Interrupt circuits are provided to inform the central processing unit of the availability of data signals in the 10. interface apparatus.
  • Figure 1 is a general block diagram showing the position of the interface unit with respect to the analog input signals and the data bus.
  • Figure 2 is a block diagram showing the principal components of the interface unit. 20.
  • Figure 3a is a diagram showing the location of signals entered in the control registers to control the signal processing.
  • Figure 3b is a diagram showing the location of signals in the interface unit to be transmitted to the central processing unit.
  • Figures 4a-4d, 5a-5d, and 6a-6c together comprise a detailed 25. schematic diagram of the interface unit of the present invention.
  • Figures 7a-7c illustrate the orientation of Figures 4a-4d, 5a-5c, and 6a-6c respectively.
  • FIG. 30 Referring to Figure 1, the general position of the interface unit of the present invention with respect to the remainder of the system is shown. Signals are provided by the devices or apparatus being monitored. These signals are typically signals extracted from or related directly to the signal operation of the monitored apparatus. The signals are typically in analog form and unsuitable for direct 5.application to a system data bus requiring'a digitally formatted signal group.
  • the interface apparatus couples the analog signals to the system data bus 11.
  • the system data bus is coupled to central processing unit 9.
  • the multiplexer 21 receives one or more analog input signals at the input terminal of multiplexer 21. A selected one of these analog signals is transmitted to the output terminal of multiplexer 21.
  • a latch circuit can be included to control the operation of the multiplexer without the requirement of continuous
  • the signal at the output terminal of multiplexer 21 is applied to sample and hold amplifier 22.
  • the sample and hold amplifier 22 applies an output signal to an analog to digital converter 23, and the output signal of the analog to digital converter 23 is applied to data
  • the control logic unit 29 is coupled to the multiplexer 21, the sample and hold amplifier 22, the analog to digital converter 23, the data memory unit 24, and the data register 25.
  • the control logic unit 29 receives signals from a clock 29a and from control registers 28.
  • the control registers 28 receive signals from address and decoder unit 27 and exchange signals with data transceiver 26.
  • the address and decoder unit 27 also applies signals to data register 25 and to interrupt register 41.
  • the interrupt register 41 exchanges signals with data transceiver 26 and applies signals to interrupt request and '
  • the interrupt request and vector unit 41 applies signals to the system data bus 11.
  • the address and decoder unit receives signals from the system data bus 11 and determines whether the signals are intended for the selected interface unit and to what location in the selected interface unit the incoming data signals are
  • the write date memory configuration is shown. (The base address of the interface unit can be selectable by jumper connections) .
  • the data can occupy four consecutive word locations.
  • the first word location includes the start conversion 5.
  • data, while the second word includes the control register data.
  • the third word includes the number of blocks and the conversion period, while the fourth word includes an enable signal, interrupt level, and an interrupt status/ID information. These signals are stored in the system memory in the central processing unit. 10.
  • Three registers that control the operation of the interface unit are a general register, conversion period/number of blocks register, and an interrupt register.
  • the read data memory configuration is shown.
  • the first word includes data register info ⁇ nation, while 15. the second word includes data associated with the status register.
  • the third and fourt words include information identical with the write configuration. This data group is stored in the system memory in the central processing unit.
  • Figures 4a-4d illustrate the address and address modifier decod ⁇ ing circuitry (including elements 49-56 and 58), the status register (including element 60), the control register (including element 61), 25. the timer (including elements 63 and 65), the block counter (includ ⁇ ing elements 64 and 66) , the data latch (including element 84 and 85) the interrupt logic (including the various integrated circuits shown in Figs. 4a to 4d) and the data transceiver (including elements 94 and 95) .
  • FIG. 5a-5c illustrate the analog inputs (including elements 100) , the multiplexer (including element 74) , the sample-and-hold circuit (including element 87) , the analog-to-digital converter (including element 85) , the memory buffers (including element
  • FIG. 5d illustrates the clock circuit (including elements 140 and 141).
  • Figures 6a-6c illustrate analogue to digital control circuitry 10. the data memory unit and the memory control circuits.
  • this circuit comprises three eight-bit magnitude comparators 50, 52 and 54 ( Figure 4a) . These devices monitor address 15. bits A03-A23 and the AS, LWORD and IAC signals. The address bits supply one input to a two-input comparator within comparators 50, 52 and 54, while the other input is switched to either +5 volts or ground through jumpers 51, 53 and 55.
  • the address modifier PROM 49 may be mounted in a socket for appropriate user programming in order to provide the desired res- - 7 - ponse to address modifier codes.
  • a preferred embodiment of the invention includes three control/status registers- Data is latched into the control registers by a 5. WRITE operation to the board, whereas data is output from the status registers by a READ operation.
  • the first control/status register is an eight-bit circuit comprising an ectal buffer 60 and an octal latch 61.
  • the second control/status register is a 16-bit circuit comprising two 10. eight-bit latch-readback registers 63 and 64. The conversion period of the board is determined by the latched outputs of register 63. These outputs are connected to the data inputs of an eight-bit counter 65. When enabled, counter 65 counts down from the preloaded value until at zero a signal is produced 15. which begins the A/D conversion process and reloads the counter 65 to its predetermined value.
  • the block size of the memory is determined by the latched outputs of register 64. These outputs are compared to the eight most significant bits of one of the memory address counters 20. (A or B) by an eight-bit comparator 66.
  • the third control/status register is a sixteen-bit circuit comprising two eight-bit latch/raadback registers 67 and 69, and it contains the interrupt information for the board.
  • An interrupt status/ID byte is latched into register 67, and the 25.
  • interrupt request level is latched into register 69.
  • a LOW level is clocked through - 8 - circuit 71 to enable an interrupt request from circuit 70.
  • the level of inter ⁇ rupt being serviced is indicated on address lines A01, A02 and A03. This address information is compared ⁇ to the generated interrupt 5. level'by comparator 72, and if the request and service levels match the interrupt status/ID byte stored in register 67, it is enabled onto bits D00-D007 of the data bus (connector Pi, Figure 4d).
  • plsx ⁇ r 74 and buffer amplifier 76 are tracking the next channel to be converted.
  • a channel select comparator 82 is used to clear the counter 79 each time the selected number of channels have been accessed.
  • analog-to-digital converter 85 it can be jumpered for a 0 to 10 volt, plus-or-minus 5 volt, or plus- or-minus 10 volt operation by properly arranging jumpers J8 and ' J9.
  • the gain and offset of the A/D 85 are adjustable by - 9 - means of resistors 91-93.
  • the twelve-bit output of the A/D 85 is stored in one of the two swinging buffer memories depending upon which data bus buffers are enabled. If data bus buffers 97 and 98 are enabled, the data is stored in memory B, whereas 5. if data bus buffers 101 and 102 are enabled, the data is stored in memory A.
  • the data memory it is arranged as two 16 x 12 bit swinging buffers, memory B comprising circuits 107-109 and memory A comprising circuits 104-106. Data is written to and read from 10. these memories using appropriate control sequences stored in PALS. .
  • PAL A produce a control sequence that inputs data from the A/D converter ' 85 to the memory location addressed by address counters A or B «- 15.
  • PAL B produce a control sequence that outputs data from the memory addressed by address counters A or B to the system data bus.
  • the multiplexer In the inventive interface unit, the multiplexer, sample and hold apparatus, analog to digital converter, and buffer memory
  • the 20. unit can be typically implemented by components known in the related art. However, control of the components is performed by means of the control logic unit in response to signals from the central processing unit.
  • the timing and control logic unit is provided with a software programmable timer based on clock 29a
  • control logic unit permits the user to select between an internal or an external trigger, between normal and event trigger in an internal mode, between a continuous or tran-
  • sient data acquisition mode and .between an interrupt or polling response mode.
  • continuous mode of data acquisition signals from the moni ⁇ tored device are storedr ' -in separate portions of the data memory unit, and the portions of the data memory unit are alternatively applied to the 5- system data bus.
  • the user can select the number of input channels monitored by the interface unit and the mode of operation when each channel is being monitored.
  • An interrupt signal is generated and applied to the central processing unit when data is available in the
  • interface unit for transfer to the central processing unit.
  • the user can also select between a disable or enable mode for the board.
  • the mode of the interface unit is controllable, permitting flexibility in operation by the user. This control can be effected, in the present invention by loading the control register
  • control logic unit can determine, for example, if a continuous or transient mode of operation is to be employed to monitor output signals.
  • the control apparatus further includes apparatus for signalling the presence of an interrupt event identified by the interface unit.
  • the disclosed apparatus can change the mode of monitoring a device (under control of the central processing unit). This flexibility permits the monitoring of expected transient events by the use of the interface unit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Communication Control (AREA)

Abstract

Une unité d'interface entre des signaux analogiques provenant d'un dispositif sous contrôle et un bus de données de signaux numériques comprend un multiplexeur, un amplificateur échantilloneur-bloqueur, un convertisseur analogique-numérique, une unité de mémoire tampon et des circuits de commande. Ces circuits de commande répondent aux signaux provenant d'une unité de traitement centrale et peuvent commander les paramètres de fonctionnement de l'unité d'interface, y compris une horloge de logiciel programmable. Les circuits de commande peuvent également produire des signaux d'interruption.
EP19860906414 1985-11-09 1986-11-07 Procede et appareil d'interface entre des signaux analogiques et un bus de systeme Withdrawn EP0245346A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8527676 1985-11-09
GB858527676A GB8527676D0 (en) 1985-11-09 1985-11-09 Interfacing between analog signals & system bus

Publications (1)

Publication Number Publication Date
EP0245346A1 true EP0245346A1 (fr) 1987-11-19

Family

ID=10587993

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19860906414 Withdrawn EP0245346A1 (fr) 1985-11-09 1986-11-07 Procede et appareil d'interface entre des signaux analogiques et un bus de systeme

Country Status (4)

Country Link
EP (1) EP0245346A1 (fr)
JP (1) JPS63500341A (fr)
GB (1) GB8527676D0 (fr)
WO (1) WO1987003114A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2188806B (en) * 1986-04-05 1989-11-01 Burr Brown Ltd Method and apparatus for improved interface unit between analog input signals and a digital signal bus
CA2014252A1 (fr) * 1989-06-27 1990-12-27 Sang Pak Systeme de saisie analogique-numerique
US5081454A (en) * 1990-09-04 1992-01-14 Motorola, Inc. Automatic a/d converter operation using programmable sample time
DE69126386T2 (de) * 1990-09-04 1997-12-18 Motorola Inc Automatische Auswahl von externen Multiplexerkanälen durch A/D-Wandlerintegrationsschaltung
EP0474026B1 (fr) * 1990-09-04 2000-03-15 Motorola, Inc. Système de convertisseur analogique-numérique utilisant des mots de contrôle de conversion
IE913900A1 (en) * 1990-12-28 1992-07-01 Eaton Corp Sure chip plus
JPH04290310A (ja) * 1991-03-19 1992-10-14 Fujitsu Ltd アナログ・デジタルコンバータ
US5302952A (en) * 1992-08-28 1994-04-12 Motorola, Inc. Automatic A/D converter operation with pause capability

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1981002479A1 (fr) * 1980-02-28 1981-09-03 Intel Corp Appareil de commande de l'interface d'un microprocesseur
JPS57129521A (en) * 1981-02-05 1982-08-11 Fuji Electric Co Ltd Analog-to-digital converting system
JPS5833751A (ja) * 1981-08-25 1983-02-28 Mitsubishi Electric Corp 電子計算機用アナログ入力読込装置
JPS58165141A (ja) * 1982-03-24 1983-09-30 Toshiba Corp アナログ入力方式
JPS59231641A (ja) * 1983-06-15 1984-12-26 Yokogawa Hokushin Electric Corp アナログ入力制御装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8703114A1 *

Also Published As

Publication number Publication date
GB8527676D0 (en) 1985-12-11
JPS63500341A (ja) 1988-02-04
WO1987003114A1 (fr) 1987-05-21

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