EP0221303B1 - Attribution automatique d'adresses d'E/S - Google Patents

Attribution automatique d'adresses d'E/S Download PDF

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Publication number
EP0221303B1
EP0221303B1 EP86112765A EP86112765A EP0221303B1 EP 0221303 B1 EP0221303 B1 EP 0221303B1 EP 86112765 A EP86112765 A EP 86112765A EP 86112765 A EP86112765 A EP 86112765A EP 0221303 B1 EP0221303 B1 EP 0221303B1
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EP
European Patent Office
Prior art keywords
bit
address
devices
bus
unique identifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP86112765A
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German (de)
English (en)
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EP0221303A2 (fr
EP0221303A3 (en
Inventor
David Elgar Aakre
Douglas John Abrahamson
Neil Clair Berglund
Vincent Alfred Bettermann
Lloyd Stephen Heim
Kenneth Ardelle Moe
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International Business Machines Corp
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International Business Machines Corp
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Publication date
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Publication of EP0221303A3 publication Critical patent/EP0221303A3/en
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Publication of EP0221303B1 publication Critical patent/EP0221303B1/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection

Definitions

  • This invention relates to the assignment of addresses to devices connected to a system by a bus, and in particular, automatic assignment of the addresses by the system in an efficient manner.
  • bus attached devices such as tapes, disk drives, monitors and other I/O devices require an address in order to be selected and used by the system.
  • the address is predetermined and fixed by either physical location on the bus or by manual setting of switches or jumper wires.
  • Many standard buses are not architected to use physical location to determine addresses, and manual setting of switches or jumper wires is prone to error even when performed by trained service personnel.
  • U S -A-4,360,870 describes a central processing unit which assigns addresses to I/O devices by first describing a device type and then assigning the addresses as a function of priority as established by the I/O devices of that type. This assignment scheme is dependent upon an established priority within a type of I/O device. It also requires the customer to have knowledge as to what types of devices are attached and to establish a priority for each I/O device.
  • IBM Technical Disclosure Bulletin, Vol. 24, No. 7B, December 1981, " Programmable Assignment of Device Addresses” discloses a method of assigning addresses where the I/O devices are serially connected by a line.
  • the addresses are assigned as a function of a priority wiring scheme and serial propagation. These methods are not available for use with many standard busses without undesirable alteration of the standard bus.
  • An automatic address assignment system has a plurality of I/O devices coupled to a bus. Each I/O device has a unique fixed length identifier and is capable of responding to information on the bus as a function of the identifier. The system selects the first bit in the identifier and transmits a binary value, '0' or '1' to the I/O devices. All devices having identifiers with a first bit matching the transmitted binary value respond. If no devices respond, the system transmits the opposite binary value for the selected identifier bit. If one or more devices respond, the system selects the next identifier bit and transmits a binary value again.
  • the automatic address assignment does not require a user to set any switches, or place an I/O device in any predetermined sequence on installation.
  • An I/O device can be added at any time and will be automatically assigned an address.
  • FIG. 1 A preferred embodiment of a computer system having automatic address assignment for its peripheral devices is indicated generally at 10 in Fig. 1.
  • the system 10 comprises a host processor unit 12 coupled by a communicative means such as bus 14 to a plurality of input/output processors 16, 18,...N.
  • I/O processor 16 is in turn coupled to peripheral devices 20, 22,...M by a communicative means such as a device bus 26.
  • I/O processor 18 is also coupled to peripheral devices 28, 30,...P by a similar second device bus 32.
  • Automatic address assignment is accomplished by I/O processors 16, 18,...N in operation with their corresponding peripheral devices.
  • Host 12 could also use automatic assignment to assign addresses to I/O processors 16, 18,...N if desired.
  • Device busses 26 and 32 preferably comprise parallel buses having 24 signal lines: One interrupt line: ATTENTION. Three outbound tag lines: SELECT OUT, HOST OUT, SYNC OUT. Two inbound tag lines: DFC IN (device functional controller in), SYNC IN Two bi-directional busses, 9 bits each: BUS A (bits 0-7 plus parity), BUS B (bits 0-7 plus parity).
  • Normal device bus protocol assumes that peripheral device addresses are already assigned. Since at the start of operating a system, the addresses are not already assigned, a means of automatically assigning the addresses is provided.
  • An alternative device bus protocol is provided to perform the automatic assignment and is referred to as maintenance mode. 18 of the 24 bus lines are divided into 6 groups of 3 lines each. Each one of the groups is operated as one signal line in the maintenance mode protocol. Majority voting of the three lines allows redundancy in the case of a single line failure which provides fault tolerant characteristics.
  • the device bus line assignments for the maintenance mode protocol is indicated in the following Table 1:
  • Each peripheral device comprises a device functional controller (DFC) which is indicated generally at 40 in Fig. 2 and controls communication between IOP 16 and peripheral device 20 in Fig. 1.
  • Device bus 26 is coupled to drivers and receivers indicated at 42. The drivers and receivers both provide and detect signals on the individual lines of device bus 26 to enable communication.
  • a link adapter 44 is coupled to the drivers/receivers 42 by a bus 46. Link adapter 44 contains control logic for executing device bus 26 protocols, and in normal operation, contains the device bus address so that bus selection and information transfer can occur.
  • Information is transferred across the device bus between the IOP and the DFC utilizing a random access memory 48 which is coupled to the link adapter 44 by a bus 50.
  • a microprocessor 52 is also coupled to bus 50 and controls information transfer to and from memory 48.
  • each device that requires an address activates its 'Attention In' line.
  • the system sets the three outbound tag lines to a master reset state.
  • a maintenance mode facility indicated at 56 becomes active and a maintenance mode shift register 58 becomes ready to receive maintenance mode commands.
  • Register 58 is coupled to link adapter 44 by a line 59, and receives the maintenance mode commands from link adapter 44.
  • the maintenance mode facility 56 is coupled to register 58 by a bus 62 to receive the commands.
  • a non-volatile memory 60 is coupled to line 50 and contains a unique identifier for the peripheral device 20.
  • Each peripheral device contains a unique machine-readable identifier in its non-volatile memory.
  • the unique identifier is preferably a 48 bit binary string defining the manufacturer, unit type, and serial number of the peripheral device.
  • IOP 16 In maintenance mode and when the command to perform address assignment is activated, IOP 16 selects each identifier bit position, one at a time, and the maintenance mode facility 56 accesses the identifier bit string from the non-volatile memory 60.
  • the maintenance mode facility compares the identifier bit value with the value solicited by the IOP and either responds positively, if the values match, or drops out of automatic addressing mode if the values do not match. If the maintenance mode facility responds positively to all bits in the unique identifier, it remains the only facility still selected and the IOP sends the command to shift the assigned address into the maintenance shift register. The maintenance mode facility then moves the assigned address into the link adapter logic and the automatic address assignment is completed for the device.
  • the maintenance mode facility in the DFC 40 will no longer respond to the commands for automatic addressing unless the assigned address is reset.
  • Automatic address assignment is based on a portion of the device's vital product data contained in the non-volatile memory 60.
  • This vital product data comprises a 4 digit (2 byte) unit type field which is associated with the device when the customer orders the device with customer selected options, and an 8 digit (4 byte) serial number field which is the unique serial number for the particular device.
  • the two fields are concatenated to form the unique identifier.
  • Each device (up to eight in this embodiment), as it becomes operational, activates the ATTENTION line of the device bus.
  • the associated IOP responds to the ATTENTION line with a Power on Status poll to determine the address of the device looking for service.
  • the address is normally presented at that time as a radial address as 1 of 8 bits (0-7) on the B bus.
  • Automatically assignable devices that do not have addresses assigned will return the Parity bit as their radial address, thereby telling the IOP that at least one device needs an address assigned.
  • devices with fixed addresses or automatically assignable devices which already have addresses assigned communicate their addresses to the IOP.
  • a device with an address will respond to a "power on" poll by driving one of the bus B "in" lines which corresponds to its address. Thus, when assigning addresses, the IOP will not use any of the already assigned addresses.
  • the IOP then uses the maintenance mode protocol and issues an EXTENDED ORDER command.
  • This command tells automatically assignable devices which do not have addresses assigned, to stay selected and proceed with the bit query/elimination process the next time Enable Out is raised.
  • the IOP then drops Enable out.
  • a Read Sequence is signaled to the devices, Enable Out is raised and the bit query/elimination process begins.
  • Timing relationships are indicated in Fig. 3 for the bit query/elimination process.
  • Data Out is set to a "1", then Clock Out is raised by the IOP. All devices with the first bit of their identifier equal to the level of Data Out must respond with Response In.
  • the first bit to be compared is the highest order bit of the Unit Type field, bit 0.
  • the IOP delays a predetermined number of microseconds, XX, (a function of hardware speed) after raising DATA OUT, and looks for RESPONSE IN active. If RESPONSE IN is active, CLOCK OUT is dropped and DATA OUT remains active. When the IOP drops CLOCK OUT, it also stores the value of DATA OUT so that it can accumulate the bit pattern of the identifier and remember which device address it assigned to that identifier.
  • the device drops RESPONSE IN and looks at the state of DATA OUT. If the state of DATA OUT is the same as the value of the first bit of that device's unique identifier, and the device had responded to the IOP, that device may remain selected in maintenance mode. At the same time, all other devices which are still selected, look at the state of DATA OUT and make the same comparison. If the state of DATA OUT and the value of the bit are not the same, the device must eliminate itself from this execution of the bit query/elimination process. The devices that eliminate themselves must not re-enter the bit query/elimination process until the process is restarted.
  • the query and elimination process continues with the next bit. There is a predetermined delay, ZZ, between the time the IOP drops CLOCK OUT and raises the next CLOCK OUT.
  • Each raising of CLOCK OUT indicates to the devices still selected that the next bit of the unique identifier is being interrogated. Again, the device must compare the value of the next bit of its unique identifier, and the value of DATA OUT, and decide whether RESPONSE IN should be raised. Also, each device has to do the compare to DATA OUT at the time CLOCK OUT is dropped to decide if it should remain selected or must drop out of maintenance mode. This process continues until all 48 bits have been interrogated. At this point only one device remains selected, since each device has a unique 48 bit sequence.
  • Each device must be designed such that it will use the 48 bits of unique identifier data first, then concatenate zeros on the end of that data (add zeros to the low order end of the bit string), and therefore assume that any bits queried beyond the initial 48 bits are all zeros.
  • the device should assume that it must keep doing the bit query sequence as long as the ENABLE OUT line remains active while the CLOCK OUT sequence is continuing. This capability allows the possibility of expanding the length of the unique identifier, should that become necessary in future releases.
  • Enable Out is dropped by the IOP, the device that remains isolated after the bit query sequence must assume that it is selected and accept the next order as a command.
  • the IOP indicates a write sequence, raises Enable Out, and passes a Source/Sink order to the selected device.
  • the Source/Sink order indicates the address register as the destination for the bus address. Address '0000'B is assumed by all automatically assignable devices as the address of the device address register.
  • the Enable Out line is dropped, another write sequence is indicated, and a Data Transfer order is sent to the device.
  • the Data Transfer order contains a 3 bit device address which is written into the device address register.
  • After Enable Out is dropped, the device receiving the address no longer reacts to the address assignment command.
  • the IOP then continues to address the other devices that do not have addresses, or stop the process if all devices are addressed.
  • the IOP determines if any more devices need address assignment by doing another power poll and looking for a parity bit returned.
  • the IOP determines that the address of any of the devices needs to be changed, maintenance mode is entered, and only the device which needs to change will be selected. At that time, a new address is assigned using the Source/Sink order, and the Data Transfer order.
  • Configuration of the bus may be different.
  • the addressing scheme could also be modified such that when a single device responds to the bit query, it is immediately assigned an address. Further intelligence built into the process could keep track of bit patterns unsuccessfully tried before, so as not to repeat unnecessary patterns.
  • each remaining device transmits its unique identifier on the bus and receives from the bus at the same time. If the received data at a device does not match its transmitted identifier, the device raises the parity bit to indicate that more than one device remains and to continue the bit query sequence. If the parity bit is not raised, there is only one device in contention and it is assigned an address.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Claims (2)

  1. Procédé pour attribuer des adresses à une pluralité de dispositifs d'entrée/sortie (20, 22, ..., M ; 28, 30, ..., P) reliés par un bus (26, 32) ayant des lignes multiples, à un contrôleur (16, 18), dans lequel chaque dispositif d'entrée/sortie comporte un identificateur particulier comprenant une chaîne de bits, caractérisé en ce qu'il comprend les étapes consistant à :
    (a) monter un signal sur une première ligne du bus par un dispositif d'entrée/sortie lorsqu'il devient fonctionnel ;
    (b) envoyer une interrogation d'état auxdits dispositifs d'entrée/sortie si la première ligne dudit bus est montée ;
    (c) détecter les signaux sur les lignes particulières du bus d'adresses montés par les dispositifs d'entrée/sortie en réponse à ladite interrogation d'état indiquant quelles adresses sont déjà affectées et un desdits signaux indiquant qu'au moins un dispositif d'entrée/sortie a besoin qu'on lui affecte une adresse ;
    (d) envoyer un ordre à chaque dispositif d'entrée/sortie pour répondre aux signaux d'affectation d'adresses, si bien que seulement les dispositifs d'entrée/sortie qui n'ont pas déjà d'adresses affectées restent sélectionnés pour répondre aux signaux d'affectation d'adresses ;
    (e) envoyer un bit de données d'identification ;
    (f) amener chaque dispositif d'entrée/sortie à répondre audit bit de données d'identification s'il concorde avec un bit correspondant dudit identificateur particulier dans un dispositif d'entrée/sortie qui reste toujours sélectionné pour répondre aux signaux d'affectation d'adresses ;
    (g) amener chaque dispositif d'entrée/sortie à arrêter de répondre aux signaux d'affectation d'adresses si ledit bit des données d'identification ne concorde pas avec un bit correspondant dudit identificateur particulier pour chaque dit dispositif d'entrée/sortie ;
    (h) modifier la valeur du bit de la donnée d'identification si aucun dispositif d'entrée/sortie n'a répondu à l'étape f ;
    (i) répéter les étapes e à h pour un nombre prédéterminé de bits égal au moins à la longueur de l'identificateur particulier le plus long ;
    (j) affecter une adresse non précédemment affectée au seul dispositif d'entrée/sortie qui répond toujours aux signaux d'affectation d'adresses, et
    (k) répéter les étapes b à j jusqu'à ce que tous les dispositifs d'entrée/sortie présentent des adresses qui leurs sont affectées.
  2. Procédé selon la revendication 1, dans lequel lorsque le nombre prédéterminé de bits d'identification est plus grand que l'identificateur particulier d'un dispositif d'entrée/sortie, le dispositif d'entrée/sortie répondra bien que son identificateur particulier ait des valeurs binaires de zéro pour les bits d'identification qui dépassent le nombre de bits de l'identificateur particulier.
EP86112765A 1985-10-28 1986-09-16 Attribution automatique d'adresses d'E/S Expired - Lifetime EP0221303B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US791884 1985-10-28
US06/791,884 US4730251A (en) 1985-10-28 1985-10-28 Automatic I/O address assignment

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EP0221303A2 EP0221303A2 (fr) 1987-05-13
EP0221303A3 EP0221303A3 (en) 1989-10-18
EP0221303B1 true EP0221303B1 (fr) 1993-04-14

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US (1) US4730251A (fr)
EP (1) EP0221303B1 (fr)
JP (1) JPH0762837B2 (fr)
CA (1) CA1252904A (fr)
DE (1) DE3688277T2 (fr)

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Also Published As

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DE3688277T2 (de) 1993-10-28
JPH0762837B2 (ja) 1995-07-05
DE3688277D1 (de) 1993-05-19
EP0221303A2 (fr) 1987-05-13
EP0221303A3 (en) 1989-10-18
JPS62102349A (ja) 1987-05-12
CA1252904A (fr) 1989-04-18
US4730251A (en) 1988-03-08

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