FI19991735A - Menetelmä ja laite tietokonejärjestelmän toimintavarmuuden parantamiseksi - Google Patents

Menetelmä ja laite tietokonejärjestelmän toimintavarmuuden parantamiseksi

Info

Publication number
FI19991735A
FI19991735A FI991735A FI19991735A FI19991735A FI 19991735 A FI19991735 A FI 19991735A FI 991735 A FI991735 A FI 991735A FI 19991735 A FI19991735 A FI 19991735A FI 19991735 A FI19991735 A FI 19991735A
Authority
FI
Finland
Prior art keywords
reliability
improving
computer system
computer
Prior art date
Application number
FI991735A
Other languages
English (en)
Swedish (sv)
Inventor
Marko Karppanen
Original Assignee
Nokia Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Networks Oy filed Critical Nokia Networks Oy
Priority to FI991735A priority Critical patent/FI19991735A/fi
Priority to AU65734/00A priority patent/AU6573400A/en
Priority to DE60003209T priority patent/DE60003209T2/de
Priority to EP00953203A priority patent/EP1222543B1/en
Priority to PCT/FI2000/000689 priority patent/WO2001013231A1/en
Publication of FI19991735A publication Critical patent/FI19991735A/fi
Priority to US10/073,241 priority patent/US20020129303A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
FI991735A 1999-08-16 1999-08-16 Menetelmä ja laite tietokonejärjestelmän toimintavarmuuden parantamiseksi FI19991735A (fi)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FI991735A FI19991735A (fi) 1999-08-16 1999-08-16 Menetelmä ja laite tietokonejärjestelmän toimintavarmuuden parantamiseksi
AU65734/00A AU6573400A (en) 1999-08-16 2000-08-14 Method and device for improving the reliability of a computer system
DE60003209T DE60003209T2 (de) 1999-08-16 2000-08-14 Verfahren und vorrichtung zur verbesserung der zuverlässigkeit eines computersystems
EP00953203A EP1222543B1 (en) 1999-08-16 2000-08-14 Method and device for improving the reliability of a computer system
PCT/FI2000/000689 WO2001013231A1 (en) 1999-08-16 2000-08-14 Method and device for improving the reliability of a computer system
US10/073,241 US20020129303A1 (en) 1999-08-16 2002-02-13 Method and device for improving the reliability of a computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI991735A FI19991735A (fi) 1999-08-16 1999-08-16 Menetelmä ja laite tietokonejärjestelmän toimintavarmuuden parantamiseksi

Publications (1)

Publication Number Publication Date
FI19991735A true FI19991735A (fi) 2001-02-17

Family

ID=8555159

Family Applications (1)

Application Number Title Priority Date Filing Date
FI991735A FI19991735A (fi) 1999-08-16 1999-08-16 Menetelmä ja laite tietokonejärjestelmän toimintavarmuuden parantamiseksi

Country Status (6)

Country Link
US (1) US20020129303A1 (fi)
EP (1) EP1222543B1 (fi)
AU (1) AU6573400A (fi)
DE (1) DE60003209T2 (fi)
FI (1) FI19991735A (fi)
WO (1) WO2001013231A1 (fi)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6766479B2 (en) 2001-02-28 2004-07-20 Stratus Technologies Bermuda, Ltd. Apparatus and methods for identifying bus protocol violations
US6996750B2 (en) * 2001-05-31 2006-02-07 Stratus Technologies Bermuda Ltd. Methods and apparatus for computer bus error termination
US7689875B2 (en) * 2002-04-25 2010-03-30 Microsoft Corporation Watchdog timer using a high precision event timer
US8020149B2 (en) 2006-08-04 2011-09-13 Apple Inc. System and method for mitigating repeated crashes of an application resulting from supplemental code

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4773005A (en) * 1984-09-07 1988-09-20 Tektronix, Inc. Dynamic address assignment system
US4675813A (en) * 1985-01-03 1987-06-23 Northern Telecom Limited Program assignable I/O addresses for a computer
US4730251A (en) * 1985-10-28 1988-03-08 International Business Machines Corporation Automatic I/O address assignment
US4964038A (en) * 1987-10-28 1990-10-16 International Business Machines Corp. Data processing system having automatic address allocation arrangements for addressing interface cards
US4951283A (en) * 1988-07-08 1990-08-21 Genrad, Inc. Method and apparatus for identifying defective bus devices
GB2249460B (en) * 1990-09-19 1994-06-29 Intel Corp Network providing common access to dissimilar hardware interfaces
JP2658697B2 (ja) * 1991-12-11 1997-09-30 富士通株式会社 ウォッチ・ドック・タイマ回路
JP2750315B2 (ja) * 1993-05-14 1998-05-13 インターナショナル・ビジネス・マシーンズ・コーポレイション 識別子の指定方法およびコンピュータ・システム
EP0653704A1 (en) * 1993-11-05 1995-05-17 Advanced Micro Devices, Inc. System and method for configuring expansion cards in a computer
US5649096A (en) * 1993-11-22 1997-07-15 Unisys Corporation Bus request error detection
JPH07271711A (ja) * 1994-03-28 1995-10-20 Toshiba Corp コンピュータシステム
US5586253A (en) * 1994-12-15 1996-12-17 Stratus Computer Method and apparatus for validating I/O addresses in a fault-tolerant computer system
US5875301A (en) * 1994-12-19 1999-02-23 Apple Computer, Inc. Method and apparatus for the addition and removal of nodes from a common interconnect
US5636342A (en) * 1995-02-17 1997-06-03 Dell Usa, L.P. Systems and method for assigning unique addresses to agents on a system management bus
US5701409A (en) * 1995-02-22 1997-12-23 Adaptec, Inc. Error generation circuit for testing a digital bus
US5729762A (en) * 1995-04-21 1998-03-17 Intel Corporation Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent
JPH0948164A (ja) * 1995-08-04 1997-02-18 Ricoh Co Ltd プリンターをベースとした拡張型多機能システム
US5852617A (en) * 1995-12-08 1998-12-22 Samsung Electronics Co., Ltd. Jtag testing of buses using plug-in cards with Jtag logic mounted thereon
US5790870A (en) * 1995-12-15 1998-08-04 Compaq Computer Corporation Bus error handler for PERR# and SERR# on dual PCI bus system
US6032271A (en) * 1996-06-05 2000-02-29 Compaq Computer Corporation Method and apparatus for identifying faulty devices in a computer system
US6000043A (en) * 1996-06-28 1999-12-07 Intel Corporation Method and apparatus for management of peripheral devices coupled to a bus
US6397268B1 (en) * 1996-10-01 2002-05-28 Compaq Information Technologies Group, L.P. Tracking PCI bus numbers that change during re-configuration
US5978938A (en) * 1996-11-19 1999-11-02 International Business Machines Corporation Fault isolation feature for an I/O or system bus
US5933614A (en) * 1996-12-31 1999-08-03 Compaq Computer Corporation Isolation of PCI and EISA masters by masking control and interrupt lines
US6338150B1 (en) * 1997-05-13 2002-01-08 Micron Technology, Inc. Diagnostic and managing distributed processor system
US6122677A (en) * 1998-03-20 2000-09-19 Micron Technology, Inc. Method of shortening boot uptime in a computer system
US6223299B1 (en) * 1998-05-04 2001-04-24 International Business Machines Corporation Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables
US5991900A (en) * 1998-06-15 1999-11-23 Sun Microsystems, Inc. Bus controller
US6311242B1 (en) * 1998-08-27 2001-10-30 Apple Computer, Inc. Method and apparatus for supporting dynamic insertion and removal of PCI devices
US6292910B1 (en) * 1998-09-14 2001-09-18 Intel Corporation Method and apparatus for detecting a bus deadlock in an electronic system
US6324663B1 (en) * 1998-10-22 2001-11-27 Vlsi Technology, Inc. System and method to test internal PCI agents
US6240478B1 (en) * 1998-10-30 2001-05-29 Eaton Corporation Apparatus and method for addressing electronic modules
US6470382B1 (en) * 1999-05-26 2002-10-22 3Com Corporation Method to dynamically attach, manage, and access a LAN-attached SCSI and netSCSI devices
US6597700B2 (en) * 1999-06-30 2003-07-22 Nortel Networks Limited System, device, and method for address management in a distributed communication environment
US6629166B1 (en) * 2000-06-29 2003-09-30 Intel Corporation Methods and systems for efficient connection of I/O devices to a channel-based switched fabric
US6745270B1 (en) * 2001-01-31 2004-06-01 International Business Machines Corporation Dynamically allocating I2C addresses using self bus switching device
US6766479B2 (en) * 2001-02-28 2004-07-20 Stratus Technologies Bermuda, Ltd. Apparatus and methods for identifying bus protocol violations

Also Published As

Publication number Publication date
EP1222543A1 (en) 2002-07-17
DE60003209T2 (de) 2004-04-08
AU6573400A (en) 2001-03-13
US20020129303A1 (en) 2002-09-12
EP1222543B1 (en) 2003-06-04
WO2001013231A1 (en) 2001-02-22
DE60003209D1 (de) 2003-07-10

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