EP0202166A1 - Virtuelle Bildspeicherschaltung für vielfache Bildfenster - Google Patents

Virtuelle Bildspeicherschaltung für vielfache Bildfenster Download PDF

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Publication number
EP0202166A1
EP0202166A1 EP86401008A EP86401008A EP0202166A1 EP 0202166 A1 EP0202166 A1 EP 0202166A1 EP 86401008 A EP86401008 A EP 86401008A EP 86401008 A EP86401008 A EP 86401008A EP 0202166 A1 EP0202166 A1 EP 0202166A1
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EP
European Patent Office
Prior art keywords
address
image memory
memory
indirection table
interface
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Granted
Application number
EP86401008A
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English (en)
French (fr)
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EP0202166B1 (de
Inventor
Ciaran O'donnell
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O'DONNELL, CIARAN
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O'Donnell Ciaran
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports

Definitions

  • the present invention relates to a virtual image memory circuit allowing multi-windowing.
  • the circuit of the invention is associated with a point addressing screen (in Anglo-Saxon terminology “raster screen” or "bitmap screen”) which uses a two-dimensional coordinate system.
  • the circuit of the invention comprises a two-dimensional image memory, the addressing of which is carried out according to a coordinate system similar to that used for the addressing of the screen.
  • This memory is larger than the screen size. It can thus memorize a set of images of which only a few are displayed, in whole or in part, at a given instant.
  • a window is defined as a surface of finite dimension and any shape of a two-dimensional display space.
  • the screen is considered as a rectangular window on this display space. Any number of windows can be defined on the display space, these may be separate, or overlap, partially or completely. These windows constitute areas onto which images contained in the image memory are projected.
  • the invention relates to a virtual image memory circuit.
  • virtual refers to the fact that an image of the image memory can be projected onto a window separate from the window represented by the screen, and thus not be viewed.
  • window designates in the rest of the text both a finite surface of the display space and the image projected on this surface.
  • a first multi-window method is described in the article "WINDX-Windows for the UNIX environment" by Peter Colins presented at USENIX conference, Salt Lake City, 1984.
  • the image memory is divided into rectangular cells of 8 "16 elementary image points.
  • a page is defined as a rectangular set of cells.
  • the content of a page is viewed through a screen window, which maps a rectangular region of the page to a rectangular region of the image. Several windows can be created simultaneously on the screen.
  • Each window is defined by a set of pointers designating cells in a page of the image memory.
  • the addressing of the image memory by the video generator delivering the video signal to the screen is therefore carried out by means of an indirection table containing said pointers.
  • This indirection table allows you to quickly modify an image displayed on the screen. Indeed, the modification of the image displayed in a window of the screen is obtained without any physical movement of cells in the image memory, but simply by a modification of the content of the pointers of the indirection table associated with this window.
  • This indirection table also allows better management of the image memory because the white areas, generally large, that a displayed image contains, can be represented in the image memory by a single cell designated by each of the pointers which correspond to white cells on the screen.
  • the main drawback of this system is that the processor which manages the accesses, in writing or in reading, to the image memory does not pass through the indirection table but on the contrary directly addresses the image memory.
  • This structure also has the defect that the processor does not directly know the displayed image but must read the content of the table of pointers to explicitly know the address of the memory cells making up this displayed image. This necessary reading step considerably limits the speed of modification of the screen content.
  • a virtual memory circuit comprising an image memory and an indirection table in which said indirection table is used only by the processor.
  • a such a virtual memory circuit is used in particular in certain computers of the RID-GE COMPUTERS Company.
  • the use of an indirection table by the processor accessing read and write memory is therefore known.
  • This indirection table constitutes the memory management unit which performs an automatic translation of the addresses used in most advanced processors.
  • the image memory accessed by the processor through the indirection table is copied into a second memory which is addressed only by the video generator.
  • the blocks translated by the indirection mechanism are blocks of fixed size in one dimension - (page), which corresponds to the use of a virtual memory managing a program memory.
  • Each element addressed by this indirection table corresponds to a certain number of entire lines on the screen.
  • To perform a multi-windowing it is necessary to have a two-dimensional cutting, that is to say a cutting where the dimensions of a block in the X and Y dimensions are less than that of a line of characters on the screen.
  • the circuit described in this article has a drawback analogous to that of the circuit described in the previous article, namely that the difference between the modes of access of the processor and the video generator to the image memory does not allow rapid management. and efficient by the processor of the image displayed on the screen.
  • An image memory circuit is also known in which the addressing of the image memory is always done through an indirection table.
  • the processor and the video generator then access the image memory symmetrically.
  • the image memory contains only the image viewed and does not allow multi-windowing.
  • this image has a number of rows or columns which is not of the form 2 ", where n is an integer, direct addressing of the memory by the processor would result in a significant waste of this memory.
  • the indirection table used in this known circuit has the sole purpose of limiting the waste of memory by performing address transcoding.
  • This indirection table consists of a read only memory (ROM) and therefore does not allow the image displayed to be modified by updating this table.
  • the subject of the invention is a virtual image memory circuit which in particular overcomes the drawbacks of the circuits according to the prior art.
  • a first characteristic of the invention resides in the symmetrical addressing of the image memory by the processor and the video generator. This makes it possible to simplify the management of the image memory and in particular any modification by the processor of the image displayed on the screen thanks to the identity of the addressing of the memory by the video generator and the processor.
  • an indirection table made up of a random access memory constitutes the second characteristic of the circuit of the invention.
  • This indirection table contains a set of pointers each designating an area of the image memory. The possibility of modifying the contents of this indirection table allows on the one hand the processor to create multiple windows and on the other hand to modify the windows, visible or not visible on the screen, or to move the visible windows on the screen, without having to physically move the content of the image memory.
  • This indirection table also makes it possible to limit the waste of memory when the number of rows or columns of the affected image is not a power of 2.
  • the interface receives read or write orders from an external processor.
  • it constitutes a buffer for storing the signals delivered by the processor as long as access to the image memory or to the indirection table is not authorized, for example when access is requested by the video generator.
  • It can include a memory management unit that can be addressed by the processor (image memory and main memory).
  • the n elementary blocks displayed on the screen correspond to the first n pointers of the indirection table.
  • the video generator addresses only these n pointers. Addressing is performed periodically to refresh the image.
  • n first pointers of the indirection table we mean the pointers contained in the n lowest addresses of the indirection table.
  • the circuit of the invention further comprises a means arranged between, on the one hand, the video generator and the interface and, on the other hand the indirection table, said means receiving the addresses delivered by said video generator and said interface and decomposing each address into an upper part representing the start address of a block of the image memory and into a lower part representing an index for designating a word of this block, the upper part of an address being received by the indirection table and the lower part by the image memory.
  • the means arranged on the one hand between the video generator and the interface and on the other hand the indirection table comprises a first row address register and a first column address register for receiving the addresses delivered by said video generator, a second row address register and a second column address register for receiving the addresses delivered by said interface and means for concatenating the upper parts of the addresses delivered by a row address register and a column address register and to concatenate the lower parts of the addresses delivered by a row address register and a column address register, the address resulting from the concatenation of the upper parts of the addresses being applied to the indirection table and the address resulting from the concatenation of the lower parts of the addresses being applied to the image memory.
  • FIG. 1 illustrates the correspondence between the elementary blocks of the image memory and the rectangular areas of the screen.
  • This screen 2 is composed of a set of n identical rectangular areas denoted Z ,, Z ,, .... Z n
  • the size of an area corresponds to the size of an elementary block of the image memory.
  • the screen 2 is a subset of a two-dimensional space 3 comprising N identical rectangular areas or N> n.
  • the areas of this space that are not displayed, that is to say that do not correspond to the screen, are used to create virtual windows.
  • a point in space 3 is identified by a virtual address.
  • the image memory 4 is composed of a set of identical rectangular blocks 8.
  • This image memory is of the two-dimensional type, that is to say that the image stored in an elementary block is represented in the same way only when it is displayed in an area of the screen 2. This means that two elementary points located on the screen in two successive lines and on the same column, are stored in the memory 4 in two successive lines and in a same column of an elementary block 8.
  • This two-dimensional structure has the advantage, over a linear memory, of simplifying certain functions such as scrolling an image in a block or in a window.
  • each elementary block 8 of the memory 4 is carried out by a set of pointers forming an indirection table 6.
  • Each pointer comprises two address fields which designate the coordinates of the first word of the first line of a block elementary.
  • a set of n pointers determined from among the N pointers of the indirection table are associated with the zones Z ,, Z 2 , ..., Z n of the screen 2.
  • These pointers are for example the n first pointers of the table indirection, that is to say the pointers corresponding to the first n addresses of this table.
  • the other pointers designate elementary blocks not visible on the screen. The creation, movement or deletion of a window on the screen is thus carried out simply by updating the content of the indirection table.
  • the screen 2 can be composed of 2304 lines, of 1728 image points each. It can be divided into 972 zones of 64x64 image points each, or 36 rows of 27 zones each.
  • the size of the memory is for example 1024 Kmots of 16 bits each, each image point being coded on one bit.
  • This memory is divided into 4096 elementary blocks each consisting of 64 lines of 4 words.
  • the indirection table has 4096 addresses, each containing a pointer designating an elementary block of the memory.
  • the first 1152 addresses for example, correspond to the elementary blocks displayed on the screen; the other pointers correspond to the virtual zone containing the windows not displayed.
  • FIG. 2 shows a diagrammatic drawing of a virtual image memory circuit according to the invention.
  • This circuit mainly comprises the image memory 4, the indirection table 6, a video generator 10, an interface 12 and a means 26. It also includes a data bus 14 to which the image memory 4 is connected, the video generator 10, the interface 12 and, through a latch 16, the indirection table 6. It finally comprises several address buses 18, 20, 22 and 24 respectively connecting the interface 12 to the means 26, the generator video at means 26, means 26 at the indirection table 6, and the indirection table 6 at the image memory 4.
  • the addressing of the image memory 4 by the video generator 20 and the interface 12 is done via the indirection table 6.
  • the means 26 receives virtual addresses delivered by the video generator 10 and the interface 12, that is to say addresses expressed according to the two-dimensional display space.
  • the interface 12 delivers virtual addresses designating any image element of the display space.
  • the addresses delivered by the video generator can only designate the picture elements corresponding to the screen, that is to say to a determined window of the display space.
  • the addresses received by the means 26 are broken down into a high address and a low address, the first designating an area number of the display space and the second designating a word in this area.
  • the upper address is transmitted, by bus 22, to the indirection table 6 which delivers to the image memory 4 the physical address of the block corresponding to this area.
  • the low address is transmitted directly to the image memory 4 by the bus 23; it constitutes an address index of the zone and the block.
  • the video generator 10 In refresh mode, the video generator 10 successively delivers the virtual addresses of the words whose coordinates are contained within the limits of the screen. Each virtual address corresponds, via the indirection table 6, to a physical address of the image memory 4. The word contained at this address is received by the video generator 10 by the data bus 14. The words thus received from the image memory are then transmitted in the form of a video signal S to a display means.
  • the interface 12 delivers a virtual address on the address bus 20.
  • This virtual address can designate any word of the display space, corresponding to the screen or to a window that is not displayed.
  • the interface 12 can also address the indirection table 6.
  • the selection of the image memory 4 or of the indirection table 6 is ensured by selection signals CSM or CST transmitted by the interface 12.
  • the interface 12 can read or write to the image memory, the data transmission being carried out by the data bus 14.
  • the virtual address delivered by the interface 12 is used to designate a pointer to the indirection table, the data transmission being carried out by the buses 14 and 24, the lock 16 being on.
  • the modification of the content of the indirection table 6 by the interface 12 makes it possible to modify the organization of the windows and in particular the image displayed on the screen very simply, without it being necessary to physically move data in the image memory.
  • the video generator 10 and the interface 12 accessing the image memory in the same way, a modification of the content of the indirection table is transparent to the video generator.
  • the main control signals emitted by the interface 12 have been indicated in FIG. 2. These are CSM and CST to select the image memory and the indirection table respectively, RD / WR to indicate whether the access is in read or write, RAFO and RAF1 which commands the replacement of the last word sent by the video generator respectively by the value "0" or the value "1".
  • the processor addresses the central memory and the image memory in a conventional manner via a memory management unit.
  • the main memory contains programs and data; it is one-dimensional.
  • the image memory contains picture elements; it is two-dimensional. Access to the two memories is therefore not identical.
  • the addressing by the memory management unit is direct.
  • the memory management unit is connected directly to the memory circuit and a conditioned permutation means is arranged between the processor and the memory management unit.
  • This permutation means is designed to be transparent for the received address signal or to exchange bits of this address signal as indicated above.
  • the state of the permutation means can be controlled simply by state of an unused bit of the virtual address.
  • This permutation means can be implemented by two multiplexers controlled simultaneously, the first of which receives the bits of ranks N, N + 1, ..., N + L + 1 on a first input and the bits of ranks M, M + 1, ..., M + L + 1 on a second input, and the second of which receives the rank bits M, M + 1, ..., M + L + 1 on a first input and the bits N, N + 1 , ..., N + L + 1 on a second input.
  • the other address bits are not affected by the permutation means.
  • the interface 12 can comprise in series the conditioned permutation means and the memory management unit; the address bus 20 is then also directly connected to the central memory.
  • the memory management unit is connected at the input directly to the processor. Its address output is connected directly to the central memory and is connected to the image memory by a means operating a fixed permutation between the bits of ranks N, N + 1, ..., N + L + 1 and the bits of rank M, M + 1, ..., M + L + 1.
  • This permutation means can be only virtual, the permutation consisting only in modifying the connections of the address lines of the bus 20 on the input pins of the means 26.
  • the interface 12 only includes a memory management unit.
  • Bus 20 is connected to the central memory without permutation of address lines and to means 26, for addressing the image memory, with permutation of certain address lines.
  • FIG. 3 illustrates an embodiment of the means 26. This comprises two address registers 28 and 30 receiving the virtual row and column addresses delivered by the video generator 10, and two address registers 32 and 34 receiving the row and column virtual addresses delivered by the interface 12.
  • the addresses received by each register comprises a top part and a bottom part.
  • the upper parts of the line addresses are delivered by the register 28 or by the register 32 on an address bus 40.
  • the upper parts of the column addresses are delivered by the register 30 or by the register 34 on a bus d address 42.
  • the addresses present on these buses 40, 42 are concatenated to constitute an address for accessing the indirection table 6.
  • the address bus 22 results from the juxtaposition of the address buses 40, 42.
  • the lower parts of the row addresses are delivered by registers 28 and 32 on an address bus 44
  • the lower parts of the column addresses are delivered by registers 30 and 34 on an address bus 46.
  • These lower parts of row and column addresses constitute an index for designating a word from the memory block selected by the upper parts of the addresses of lines and columns.
  • the bus 23 delivering this index to the image memory 4 results from the juxtaposition of the address buses 44, 46.
  • FIGS. 4a to 4c and 5a to 5c respectively show the formats of the addresses delivered by the interface and by the video generator.
  • a 4 MB image memory organized in 32-bit words. This memory is divided into 128 ⁇ 128 bit blocks; a block is therefore represented by 128 lines of 4 words.
  • the screen has a resolution of 2304 lines of 1728 image points.
  • FIGS. 4a, 4b and 4c respectively illustrate the format of the address delivered by the video generator, and the addresses received by the indirection table and the image memory.
  • the address delivered by the video generator has 4 fields: a PY field indicating a number of block rows, an INDY field indicating a line number in a block, a PX field indicating a number of blocks in a row of blocks, and an INDX field indicating a word number in a line of a block.
  • the PY and INDY fields are received in register 28 and the PX and INDX fields by register 30.
  • the INDY and INDX fields comprise 7 bits (for 128 lines) and 2 bits - (for 4 words per line) respectively.
  • the PY and PX fields have 8 and 4 bits respectively. Of these, only the 5 least significant bits of PY are used, in order to address one of the 18 rows on the screen. The 4 least significant bits of PX are used to address one of the 14 tiles in a row of tiles on the screen.
  • the PX and PY fields are concatenated to form a selection address in the indirection table.
  • the content of this address is concatenated with the fields INDY and INDX to constitute the physical address @M of a word in the image memory (FIG. 4c).
  • the address delivered by the interface is broken down into 4 fields like the address delivered by the video generator. These 4 fields represented in FIG. 5a are identical to those in FIG. 4, the only difference being that the three most significant bits of PY are not necessarily zero. If they are zero, the address delivered by the interface is an address corresponding to a word displayed on the screen. More precisely, when the three most significant bits of PY are zero, the interface accesses one of the first n addresses of the indirection table, which corresponds to one of the blocks projected on the screen. If one of these three bits is non-zero, the address delivered by the interface corresponds to any word in the memory.
  • This word can be displayed on the screen because the indirection table is not used bijectively, a pointer from one of the first n addresses and a pointer from another address can designate the same block.
  • a pointer from one of the first n addresses and a pointer from another address can designate the same block.
  • all the windows are virtual; during access, it ignores whether all or part of the window it addresses is visible or not.
  • access to the first n addresses of the indirection table is only carried out to update the pointers after a modification of the organization of a window - (scrolling, for example) or after the reorganization of the presentation of the windows on the screen.
  • the PY and INDY fields are received in the address register 32 and the PX and INDX fields in the register 34.
  • the PX and PY fields are grouped together (FIG. 5b) to form an access address to the indirection table.
  • the content of this address is concatenated with the fields INDY and INDX to constitute the physical address @M of a word in the image memory (FIG. 5c).
  • FIG. 6a shows the image memory 4 of the circuit of the invention. This memory includes three windows 48, 50 and 52.
  • Window 48 represents the image displayed on the screen. This window is made up of n identical rectangular blocks of the image memory, each block being identified by a pointer from the indirection table. The blocks displayed on the screen are, for example, those designated by the first n pointers of the indirection table.
  • the windows 50 and 52 are also each composed of a set of identical rectangular blocks of the image memory, each block being identified by a pointer from the indirection table.
  • a window can be represented with a different shape in the image memory and on the screen.
  • Each window is made up of independent rectangular tiles, each associated with a pointer.
  • Each block of a window can thus be projected on the screen independently of the other blocks of the window.
  • a window made up of contiguous blocks of the image memory can thus appear in the form of disjoint zones on the screen and conversely a set of disjoint blocks of the image memory can be displayed on the screen in the form of a rectangle.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Memory System (AREA)
  • Image Generation (AREA)
EP86401008A 1985-05-15 1986-05-12 Virtuelle Bildspeicherschaltung für vielfache Bildfenster Expired - Lifetime EP0202166B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8507412A FR2582132B1 (fr) 1985-05-15 1985-05-15 Circuit de memoire d'image virtuelle permettant le multifenetrage
FR8507412 1985-05-15

Publications (2)

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EP0202166A1 true EP0202166A1 (de) 1986-11-20
EP0202166B1 EP0202166B1 (de) 1990-10-31

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EP86401008A Expired - Lifetime EP0202166B1 (de) 1985-05-15 1986-05-12 Virtuelle Bildspeicherschaltung für vielfache Bildfenster

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US (1) US4815010A (de)
EP (1) EP0202166B1 (de)
JP (1) JPH079570B2 (de)
DE (1) DE3675253D1 (de)
FR (1) FR2582132B1 (de)

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EP0617400A2 (de) * 1989-07-28 1994-09-28 Hewlett-Packard Company Verfahren und Einrichtung zur Beschleunigung von Bildfenstern in graphischen Systemen
US5477242A (en) * 1994-01-03 1995-12-19 International Business Machines Corporation Display adapter for virtual VGA support in XGA native mode

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JP3724578B2 (ja) * 2003-07-18 2005-12-07 セイコーエプソン株式会社 半導体装置及びその制御方法
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Publication number Priority date Publication date Assignee Title
EP0617400A2 (de) * 1989-07-28 1994-09-28 Hewlett-Packard Company Verfahren und Einrichtung zur Beschleunigung von Bildfenstern in graphischen Systemen
EP0617400A3 (de) * 1989-07-28 1995-04-26 Hewlett Packard Co Verfahren und Einrichtung zur Beschleunigung von Bildfenstern in graphischen Systemen.
EP0534139A2 (de) * 1991-09-20 1993-03-31 International Business Machines Corporation Neue Video-Misch-Technik mit JPEG-komprimierten Daten
EP0534139A3 (de) * 1991-09-20 1995-02-15 Ibm
US5477242A (en) * 1994-01-03 1995-12-19 International Business Machines Corporation Display adapter for virtual VGA support in XGA native mode

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Publication number Publication date
JPH079570B2 (ja) 1995-02-01
JPS62222289A (ja) 1987-09-30
FR2582132A1 (fr) 1986-11-21
DE3675253D1 (de) 1990-12-06
EP0202166B1 (de) 1990-10-31
FR2582132B1 (fr) 1987-07-17
US4815010A (en) 1989-03-21

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