EP0173245A1 - Dispositif de mémoire semi-conducteur comportant une couche en silicium polycristallin - Google Patents

Dispositif de mémoire semi-conducteur comportant une couche en silicium polycristallin Download PDF

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Publication number
EP0173245A1
EP0173245A1 EP85110521A EP85110521A EP0173245A1 EP 0173245 A1 EP0173245 A1 EP 0173245A1 EP 85110521 A EP85110521 A EP 85110521A EP 85110521 A EP85110521 A EP 85110521A EP 0173245 A1 EP0173245 A1 EP 0173245A1
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EP
European Patent Office
Prior art keywords
layer
region
silicon layer
high resistance
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP85110521A
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German (de)
English (en)
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EP0173245B1 (fr
Inventor
Fujio C/O Patent Division Masuoka
Kiyofumi C/O Patent Division Ochii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication date
Priority claimed from JP59175412A external-priority patent/JPS6153763A/ja
Priority claimed from JP59175413A external-priority patent/JPS6153764A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0173245A1 publication Critical patent/EP0173245A1/fr
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Publication of EP0173245B1 publication Critical patent/EP0173245B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Definitions

  • This invention relates to a semiconductor device comprising a high resistance layer made of polycrystal silicon.
  • E/R type static memory cell is known as a semiconductor static memory cell.
  • the E/R type static memory cell comprises a high resistance element made of polycrystal silicon.
  • the E/R type static memory cell comprises a flip-flop, an access gate and a pair of load resistors of a high resistance.
  • the flip-flop comprises MOS (metal oxide semiconductor) transistors 1 and 2 of an enhancement type.
  • the access gate comprises MOS transistors 3 and 4 of an enhancement type.
  • the load resistors comprise resistors 3 and 4.
  • Vcc and Vss denote high and low power source potentials, respectively.
  • B and B indicate bit lines.
  • W denotes a word line.
  • reference numeral 10 denotes a word line layer.
  • First polycrystal silicon layer 11 is highly doped with an impurity and has a low resistance.
  • Second polycrystal silicon layer 12 comprises high resistance region 12A, and low resistance region 12B, highly doped with an impurity. Silicon layer 11 and high resistance region 12A contact each other within contact hole 131. Bit line layers 14 1 and 142, made of aluminium, cross over contact holes 13 1 and 13 2 .
  • Low resistance region 12B is used as a Vcc line.
  • Reference numeral 15 denotes N conductivity type, impurity diffused semiconductor regions.
  • reference numeral 21 denotes N conductivity type substrate.
  • P conductivity type well layer 22, made of single crystal silicon, is formed on substrate 21.
  • N + conductivity type, impurity diffused regions 15 are formed in well layer 22.
  • Reference numeral 23 denotes gate insulation film made of Si0 2 .
  • Reference numeral 24 denotes field insulation film made of Si0 2 .
  • Silicon layer 11 is formed on semiconductor region 15.
  • Reference numeral 25 denotes field insulation film made of SiO 2 , having contact hole 131 formed therein. Insulation film 26, made of Si0 2 , is formed on insulation film 25 and silicon layer 12.
  • Bit line layer 14 1 contacts N conductivity type, impurity diffused region 15, and extends onto insulation film 25.
  • Passivation film 27 is formed on bit line layer 14 1 .
  • insulation film 26, made of SiO 2 , bit line layer 14 1 and passivation film 27 are formed after insulation film 25 is formed.
  • Forming insulation film 26, bit line layer 14 1 and passivation film 27 comprises a thermal treatment step.
  • the thermal treatment diffuses impurities, doped in low resistance region 12B, into high resistance region 12A by the portion whose length is shown by Ll.
  • the thermal treatment also diffuses impurities, doped in low resistance layer 11, into high resistance region 12A by the portion whose length is shown by L2. Therefore, the effective region of high resistance region 12A is shortened by the portions whose lengths are shown by Ll and 12. The length of the effective region is shown by L0.
  • the effective region of silicon layer 12 determines the power consumption in the memory cell. The shorter the effective region is, the larger the power consumption is. In order to reduce the power consumption, it is necessary to make silicon layer 12 longer. This, however, makes the memory cell size large and the packing density low.
  • This invention has been achieved in consideration of the above-mentioned circumstances, the object being to provide a semiconductor device in which the length of the effective high resistance region of the polycrystal silicon layer, used as a resistor, is increased without increasing the size of the memory cell.
  • FIG. 1 An embodiment according to the invention will now be described with reference to Figs. 4 and 5.
  • the invention of this and all subsequently described embodiments applies to an E/R (enhancement/resistor) type static memory cell, a circuit diagram of which is shown in Fig. 1.
  • E/R enhanced/resistor
  • FIG. 1 For brevity of illustration, the same reference numerals are employed for the same components throughout the prior art depicted in Figs. 2 and 3, as well as for all the embodiments of the invention.
  • reference numeral 10 is a word line layer.
  • First polycrystal silicon layer 11 is highly doped with an impurity, and has a low resistance.
  • Second polycrystal silicon layer 12 comprises high resistance region 12A and low resistance region 12B.
  • Low resistance region 12B is highly doped with an impurity, and constitutes a Vcc line.
  • Layer 31 1 made of metal (for example, tungsten) having a high melting point, is formed in contact hole 13 1 .
  • a metal silicide layer having a high melting point may be employed in place of Metal layer 31 1 .
  • Such a metal or metal silicide ohmically contacts the single crystal silicon or polycrystal silicon.
  • Silicon layer 11 is connected to high resistance region 12A of silicon layer 12, with metal layer 31 1 provided therebetween.
  • Layers 14 1 and 14 2 constituting bit lines made of, for example, aluminium, cross over contact holes 13, and 13 2' respectively.
  • Reference numerals 15 denote N + conductivity type, impurity diffused semiconductor regions. In Fig.
  • reference numeral 21 denotes N conductivity type substrate made of single crystal silicon.
  • P conductivity type well layer 22, made of single crystal silicon is formed in substrate 21.
  • N + conductivity type, impurity diffused regions 15, made of single crystal silicon, are formed in well layer 22.
  • Reference numeral 23 denotes gate insulation film made of SiO 2 .
  • Reference numeral 24 denotes field insulation film made of SiO 2 .
  • Silicon layer 11 is formed on semiconductor region 15.
  • Reference numeral 25 denotes field insulation film made of SiO 2 and having, therein, contact hole 13 1 .
  • Metal layer 31 1 is formed in contact hole 13 1 .
  • Metal layer 31 1 can be provided by a known method by which metal is deposited only on a portion of an exposed surface of silicon layer 12. One example of such a method is disclosed in T. Moriya, S. Shima, Y. Hazuki, M. Chiba and M. Kashiwagi, "A PLANAR METALLIZATION PROCESS, ITS INTERCONNEC
  • High resistance region 12A of silicon layer 12, is connected to low resistance silicon layer 11 with metal layer 31 1 provided therebetween. That is, silicon layer 11 is formed on one surface of metal layer 31 1 , provided in contact hole 13 1 , and high resistance region 12A is formed on the other surface of metal layer 31 1 .
  • Insulation film 26, made of SiO 2 is formed on insulation film 25 and silicon layer 12.
  • Bit line layer 14 1 contacts N conductivity type, impurity diffused region 15, and extends onto insulation film 25.
  • Passivation film 27 is formed on bit line layer 14 1 .
  • insulation film 26, bit line layers 14 1 , 14 2 and passivation film 27 are formed after silicon layer 12 is formed.
  • Forming insulation film 26, bit line layers 14 1 , 14 2 and passivation film 27 comprises a thermal treatment step. If no barrier were provided between silicon layer 11 and high resistance region 12A of silicon layer 12, the thermal treatment would diffuse an impurity, doped in silicon layer 11, into high resistance region 12A of silicon layer 12.
  • metal layer 31 1 is provided between silicon layer 11 and high resistance region 12A. Therefore, an impurity doped in silicon layer 11 is prevented from diffusing into high resistance region 12A. Therefore, an ineffective region, whose length is shown by L2 in Figs. 2 and 3, is not produced.
  • the length of the effective region of high resistance region 12A is increased_without increasing the memory cell size.
  • low resistance silicon layer 11, provided in the embodiment in Figs. 4 and 5, is not provided, and metal layer 31 1 contacts N semiconductor region or single crystal region 15 of a low resistance. If no barrier were provided between low resistance semiconductor region 15 and high resistance region 12A, of silicon layer 12, the thermal treatment described in the first recited embodiment would diffuse an impurity, doped in semiconductor region 15, into high resistance region 12A of silicon layer 12.
  • metal layer 31 1 is provided between semiconductor region 15 and high resistance region 12A, preventing an impurity doped in semiconductor region 15 from diffusing into high resistance region 12A. Therefore, the ineffective region, whose length is shown by L2 in Figs. 2 and 3, does not appear.
  • metal layer 31 1 extends from the inside of contact hole 31 1 onto the upper surface of the insulation film 25.
  • High resistance region 12 is connected to low resistance silicon layer 11 with metal layer 31 1 provided therebetween. Therefore, as in the embodiments described above, metal layer 31, acts as a barrier to diffusion of an impurity, preventing an impurity doped in silicon layer 11 from diffusing into high resistance region 12A, so that an ineffective region, whose length is shown by L2 in Figs. 2 and 3, will not be produced.
  • metal layer 31 1 extends from the inside of contact hole 31 1 onto the upper surface of the insulation film 25.
  • High resistance region 12 is connected to low resistance semiconductor region 15 with metal layer 31 1 provided therebetween. Therefore, as in the embodiment of Fig. 6, metal layer 31 1 acts as a barrier to diffusion of an impurity, preventing an impurity doped in semiconductor region 15 from diffusing into high resistance region 12A. Therefore, an ineffective region, whose length is shown by L2 in Figs. 2 and 3, is not produced.
  • low resistance region 12A used as a Vcc line and provided in the embodiment in Figs. 4 and 5, is not provided.
  • layer 41 made of a metal having a high melting point, is provided under the region of high resistance silicon layer 12 where a Vcc line is usually provided. (Layer 41 may be provided before forming silicon layer 12, and metal silicide having a high melting point may be employed in place of the metal of layer 41.) Therefore, an ineffective region whose length is shown by Ll in Figs. 2 and 3 will not appear.
  • low resistance region 12A used as a Vcc line and provided in the embodiment in Fig. 6, is not provided.
  • layer 41 made of a metal having a high melting point, is provided under the region of high resistance silicon layer 12 where a Vcc line is usually provided.
  • Layer 41 may be made of a metal silicide having a high melting point, in place of the metal having a high melting point.
  • an ineffective region whose length is shown by L1 in Figs. 2 and 3 will not appear.
  • Other elements are substantially the same as in the embodiment of Fig. 6, and, therefore, the descriptions thereof are omitted.
  • metal layer 31 1 extends from the inside of contact hole 311 onto the upper surface of the insulation film 25.
  • High resistance region 12 is connected to low resistance silicon layer 11 with metal layer 31 1 provided therebetween. Therefore, as in the preceding embodiments, metal layer 31 1 acts as a barrier to diffusion of an impurity, preventing an impurity doped in silicon layer 11 from diffusing into high resistance region 12A. Therefore, an ineffective region, whose length is shown by L2 in Figs. 2 and 3, will not be produced.
  • metal layer 31 1 extends from the inside of contact hole 31 1 onto the upper surface of the insulation film 25.
  • High resistance region 12 is connected to low resistance semiconductor region 15 with metal layer 31 1 provided therebetween. Therefore, as in the embodiment of Fig. 6, metal layer 311 acts as a barrier to diffusion of an impurity, preventing an impurity doped in semiconductor region 15 from diffusing into high resistance region 12A. Therefore, an ineffective region, whose length is shown by L2 in Figs. 2 and 3, will not be produced.
  • a semiconductor device in which the effective region of the high resistance polycrystal silicon layer, forming a resistor, can be increased without increasing the cell size.
EP85110521A 1984-08-23 1985-08-21 Dispositif de mémoire semi-conducteur comportant une couche en silicium polycristallin Expired EP0173245B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP59175412A JPS6153763A (ja) 1984-08-23 1984-08-23 半導体装置
JP59175413A JPS6153764A (ja) 1984-08-23 1984-08-23 半導体装置
JP175413/84 1984-08-23
JP175412/84 1984-08-23

Publications (2)

Publication Number Publication Date
EP0173245A1 true EP0173245A1 (fr) 1986-03-05
EP0173245B1 EP0173245B1 (fr) 1989-03-29

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EP85110521A Expired EP0173245B1 (fr) 1984-08-23 1985-08-21 Dispositif de mémoire semi-conducteur comportant une couche en silicium polycristallin

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US (1) US4903096A (fr)
EP (1) EP0173245B1 (fr)
DE (1) DE3569172D1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0365690A1 (fr) * 1988-05-07 1990-05-02 Seiko Epson Corporation Dispositif a semi-conducteurs et memoire a semi-conducteurs
EP0368646A1 (fr) * 1988-11-10 1990-05-16 Seiko Epson Corporation Dispositif semi-conducteur
EP0437307A2 (fr) * 1990-01-12 1991-07-17 Paradigm Technology, Inc. Résistance de charge de polysilicium de résistance élevée
US5168076A (en) * 1990-01-12 1992-12-01 Paradigm Technology, Inc. Method of fabricating a high resistance polysilicon load resistor
EP0517408A1 (fr) * 1991-06-03 1992-12-09 STMicroelectronics, Inc. Cellule et structure Sram avec des dispositifs de charge polycristallins à canal p
US5254870A (en) * 1988-05-07 1993-10-19 Seiko Epson Corporation Static random access memory having memory cells with electric field shielding for cell load resistances
US5691559A (en) * 1988-11-10 1997-11-25 Seiko Epson Corporation Semiconductor devices with load elements

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214304A (en) * 1988-02-17 1993-05-25 Fujitsu Limited Semiconductor device
US5247198A (en) * 1988-09-20 1993-09-21 Hitachi, Ltd. Semiconductor integrated circuit device with multiplayered wiring
US5179434A (en) * 1988-12-22 1993-01-12 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US5138425A (en) * 1989-05-23 1992-08-11 Seiko Epson Corp. Semiconductor integrated circuit device with nitride barrier layer ion implanted with resistivity decreasing elements
US5146309A (en) * 1989-06-23 1992-09-08 Sgs-Thomson Microelectronics, Inc. Method for forming polycrystalline silicon contacts
JPH03120828A (ja) * 1989-10-04 1991-05-23 Nec Corp 半導体装置及びその製造方法
US5021849A (en) * 1989-10-30 1991-06-04 Motorola, Inc. Compact SRAM cell with polycrystalline silicon diode load
US5151387A (en) 1990-04-30 1992-09-29 Sgs-Thomson Microelectronics, Inc. Polycrystalline silicon contact structure
EP0482556A1 (fr) * 1990-10-22 1992-04-29 Nec Corporation Elément de résistance en polysilicium et dispositif à semi-conducteur l'utilisant
JP2748070B2 (ja) * 1992-05-20 1998-05-06 三菱電機株式会社 半導体装置およびその製造方法

Citations (4)

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Publication number Priority date Publication date Assignee Title
EP0032025A1 (fr) * 1979-12-30 1981-07-15 Fujitsu Limited Dispositif semiconducteur et son procédé de fabrication
EP0087979A2 (fr) * 1982-03-03 1983-09-07 Fujitsu Limited Dispositif mémoire semi-conducteur
EP0097918A1 (fr) * 1982-06-25 1984-01-11 Matsushita Electronics Corporation Dispositif semi-conducteur et procédé pour sa fabrication
EP0098737A2 (fr) * 1982-06-30 1984-01-18 Fujitsu Limited Dispositif semi-conducteur

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54110068U (fr) * 1978-01-20 1979-08-02
JPS5745967A (en) * 1980-09-04 1982-03-16 Toshiba Corp Semiconductor device
US4488166A (en) * 1980-12-09 1984-12-11 Fairchild Camera & Instrument Corp. Multilayer metal silicide interconnections for integrated circuits
US4528582A (en) * 1983-09-21 1985-07-09 General Electric Company Interconnection structure for polycrystalline silicon resistor and methods of making same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0032025A1 (fr) * 1979-12-30 1981-07-15 Fujitsu Limited Dispositif semiconducteur et son procédé de fabrication
EP0087979A2 (fr) * 1982-03-03 1983-09-07 Fujitsu Limited Dispositif mémoire semi-conducteur
EP0097918A1 (fr) * 1982-06-25 1984-01-11 Matsushita Electronics Corporation Dispositif semi-conducteur et procédé pour sa fabrication
EP0098737A2 (fr) * 1982-06-30 1984-01-18 Fujitsu Limited Dispositif semi-conducteur

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
THIN SOLID FILMS, vol. 104, no. 1/2, June 1983, pages 89-99, Lausanne, CH, Elsevier Sequoia, NL; R.J. SCHUTZ: "Tin as a diffusion barrier between CoSi2 or PtSi and aluminum" *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0365690A1 (fr) * 1988-05-07 1990-05-02 Seiko Epson Corporation Dispositif a semi-conducteurs et memoire a semi-conducteurs
EP0365690A4 (en) * 1988-05-07 1991-11-27 Seiko Epson Corporation Semiconductor device and semiconductor memory device
US5254870A (en) * 1988-05-07 1993-10-19 Seiko Epson Corporation Static random access memory having memory cells with electric field shielding for cell load resistances
EP0368646A1 (fr) * 1988-11-10 1990-05-16 Seiko Epson Corporation Dispositif semi-conducteur
US5691559A (en) * 1988-11-10 1997-11-25 Seiko Epson Corporation Semiconductor devices with load elements
EP0437307A2 (fr) * 1990-01-12 1991-07-17 Paradigm Technology, Inc. Résistance de charge de polysilicium de résistance élevée
EP0437307A3 (en) * 1990-01-12 1991-10-30 Paradigm Technology, Inc. High resistance polysilicon load resistor
US5168076A (en) * 1990-01-12 1992-12-01 Paradigm Technology, Inc. Method of fabricating a high resistance polysilicon load resistor
US5172211A (en) * 1990-01-12 1992-12-15 Paradigm Technology, Inc. High resistance polysilicon load resistor
EP0517408A1 (fr) * 1991-06-03 1992-12-09 STMicroelectronics, Inc. Cellule et structure Sram avec des dispositifs de charge polycristallins à canal p

Also Published As

Publication number Publication date
DE3569172D1 (en) 1989-05-03
EP0173245B1 (fr) 1989-03-29
US4903096A (en) 1990-02-20

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